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international conference on Advanced Computing and Communication Systems (ICACCS)

作者： S. Dhanasekar P. Malin Bruntha T. Mary Neebha N. Arunkumar N. Senathipathi C. Priya Sri Eshwar College of Engineering Coimbatore India Karunya Institute of Technology and Sciences Coimbatore India P.A College of Engineering and Technology Pollachi India Karpagam College of Engineering and Technology Coimbatore India

An area effective Orthogonal Frequency Division Multiplexing (OFDM) transceiver design with Multi-radix FFT/IFFT algorithm is introduced for wireless applications. the Pseudo-Random Binary Sequence (PRBS) will be sent as input to OFDM Transmitter, which is passed on using orthogonal frequency. Inverse Fast Fourier Transform (IFFT) and Fast Fourier Transform (FFT) processors employ a significant role in OFDM transceiver design, which increases the area and power in the silicon area. the Multi-radix algorithms like Radix-2², Radix- 2³, Radix-2⁴ are used in the FFT/IFFT processors to decrease computational complexity. the FFT/IFFT algorithms use Urdhva Tiryakbhyam Vedic multipliers to decrease the undesired multiplication steps. To increase the speed of the multiplier, compressor adders will be introduced which reduces carry delay. the Vedic multiplier-based Multi-radix FFT/IFFT algorithms save hardware area in a silicon chip. the proposed OFDM transceiver design is implemented using Virtex-2 XC2V500-6 fg256 field programmable Gate Array (FPGA) device has achieved 41974-input Lookup Tables (LUTs), 2217 slices. It is operated with a maximum clock frequency of 155.35 MHz. the Multi-radix FFT/IFFT-based OFDM transceiver design reduces 84.4% slices, 68.1% 4-input LUTs and it occupies 62. 3K gates. the multi-carrier modulation technique used in the OFDM transceiver design enhances high-speed data transmission in wireless communication.

关键词： Wireless communication Program processors Frequency modulation OFDM logic gates Transceivers Silicon

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Resilient training of neural network classifiers with approximate computing techniques for hardware-optimised implementations

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IET COMPUTERS AND DIGITAL TECHNIQUES 2019年第6期13卷 532-542页

作者： Torres, Vitor Ferreira Torres, Frank Sill Univ Fed Minas Gerais Grad Program Elect Engn Av Antonio Carlos 6627 BR-31270901 Belo Horizonte MG Brazil DFKI GmbH Cyber Phys Syst Bibliothekstr 5 D-28359 Bremen Germany

As Machine Learning applications increase the demand for optimised implementations in both embedded and high-end processing platforms, the industry and research community have been responding with different approaches to implement these solutions. this work presents approximations to arithmetic operations and mathematical functions that, associated with a customised adaptive artificial neural networks training method, based on RMSProp, provide reliable and efficient implementations of classifiers. the proposed solution does not rely on mixed operations with higher precision or complex rounding methods that are commonly applied. the intention of this work is not to find the optimal simplifications for specific deep learning problems but to present an optimised framework that can be used as reliably as one implemented with precise operations, standard training algorithms and the same network structures and hyper-parameters. By simplifying the 'half-precision' floating point format and approximating exponentiation and square root operations, the authors' work drastically reduces the field programmable gate array implementation complexity (e.g. -43 and -57% in two of the component resources). the reciprocal square root approximation is so simple it could be implemented only with combination logic. In a full software implementation for a mixed-precision platform, only two of the approximations compensate the processing overhead of precision conversions.

关键词： field programmable gate arrays learning (artificial intelligence) floating point arithmetic neural nets resilient training neural network classifiers approximate computing techniques hardware-optimised implementations high-end processing platforms research community arithmetic operations mathematical functions customised adaptive artificial neural networks training method mixed operations complex rounding methods optimal simplifications specific deep learning problems optimised framework precise operations standard training algorithms network structures half-precision floating point square root operations field programmable gate array implementation complexity reciprocal square root approximation software implementation mixed-precision platform precision conversions machine learning applications

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Invited tutorial: OpenCL design flows for Intel and Xilinx FPGAS: Using common design patterns and dealing with vendor-specific differences 6

Invited tutorial: OpenCL design flows for Intel and Xilinx F...

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6th international Workshop on FPGAs for Software Programmers, FSP 2019, co-located with international conference on field programmable logic and applications, FPL 2019

作者： Kenter, Tobias Paderborn Center for Parallel Computing Department of Computer Science Paderborn University Warburger Str. 100 Paderborn33098 Germany

ISBN: (纸本)9783800750467

An increasing fraction of new results in the reconfigurable computing domain are obtained with the help of high level synthesis tools. Among the more popular tools are the OpenCL based Xilinx SDAccel and Intel FPGA SDK for OpenCL. Since they are building upon the same programming model and source language, one would hope for portability between different OpenCL based FPGA designs. However, the vast majority of published research is only optimized for one vendor tool and FPGA family. In this manuscript, we want to broaden that scope and provide practical guidance for both tool chains. We outline the common underlying design philosophy and goals of high level synthesis for FPGAs on an abstract level, before proceeding to an example-driven discussion of tool features and concepts. We present design patterns that work well for both tools and thus can promote portability of OpenCL based FPGA designs. We outline how tool differences that can be overcome for portability, or used for further optimized tool-specific designs. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： field programmable gate arrays (FPGA)

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A field programmable Process-In-Memory Architecture Based on RRAM Technology

A Field Programmable Process-In-Memory Architecture Based on...

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international conference on Mechanical, Control and Computer Engineering (ICMCCE)

作者： Yuan Liang Longxiang Yin Ning Xu School of Computer Science and Technology Wuhan University of Technology Wuhan China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Information Engineering Wuhan University of Technology Wuhan China

Conventional reconfigurable architectures, e.g., field-programmable Gate Array (FPGA), are confronted with the inflexibility of the on-chip local memory architecture and the scarce memory resource, which result in the inflexibility to deal with the current memory-thirsty data-intensive applications. Emerging nonvolatile devices, such as resistive random-access memory (RRAM), can operate in a logic-in-memory way, i.e., they can act as both a nonvolatile memory element and a switch, and thus, have the potential to provide higher flexibility and data processing ability. We propose a field-programmable logic-in-memory architecture based on RRAM technology, which is a two-dimensional tile array, where each tile is an RRAM-based crossbar array and can be remolded into three basic modes including logic, interconnect and memory. We further develop a specific adaptive algorithm for placement and routing, which can well exploit the logic-in-memory architecture characteristics. Comparing with traditional FPGAs, our architecture shows 1.9x lower power consumption, 2.8x lower delay, and 5.6x higher performance.

关键词： Nonvolatile memory Computer architecture Switches Routing Delays System-on-chip Reconfigurable architectures

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FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation

FPGA Accelerator for Stereo Vision using Semi-Global Matchin...

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international conference on field programmable logic and applications

作者： Shashwat Shrivastava Ziaul Choudhury Shashwat Khandelwal Suresh Purini Computer Systems Group International Institute of Information Technology Hyderabad India

ISBN: (数字)9781728199023

ISBN: (纸本)9781728199030

In this paper, we propose a fully parallel and pipelined architecture for stereo vision on FPGAs using Semi-Global Matching with Census Transform being used underneath. Further, we extend the above streaming architecture so that multiple pixels can be processed in a data parallel fashion. We expose this data parallelism through dependency relaxation. this establishes a trade-off between accuracy and throughput of the hardware. We tested the proposed architecture on Virtex-7 FPGA using KITTI 2012 and KITTI 2015 datasets. On images of resolution 1280x960, with 64 disparity levels, we are able to run our hardware design at 100 MHz. At this frequency, our design is able to process 322 frames per second which is 1.6 times faster than the state-of-the-art SGM implementation on FPGA. Our system can be scaled to a higher resolution image.

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Accelerating human activity recognition systems on FPGAS through a DSL approach 6

Accelerating human activity recognition systems on FPGAS thr...

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6th international Workshop on FPGAs for Software Programmers, FSP 2019, co-located with international conference on field programmable logic and applications, FPL 2019

作者： Fernandes, Daniel A.P.L. Cardoso, João M.P. Faculdade de Engenharia Universidade do Porto Porto Portugal INESC TEC Porto Portugal

ISBN: (纸本)9783800750467

Data analytics is the process of drawing conclusions based on thorough examination of data. It is usually accomplished by machine learning techniques and the algorithms involved must often process large datasets. this severely hurts performance. However, due to the amount of parallel work present in the algorithms, targeting these applications to FPGA-based systems can help in this regard. the problem is the programming model employed by FPGAs. Most software developers have little to no knowledge in hardware description languages (HDLs) and even the currently available high-level synthesis (HLS) tools are difficult to master, as these still require much familiarity with the hardware being targeted. One of the most popular solutions to this problem has been the use of domain-specific languages (DSLs), which have been developed in several domains. this paper presents a new DSL for the data analytics domain, focusing FPGA execution. A human activity recognition (HAR) case study is used to both motivate the development of the DSL and evaluate it. Our results show that HAR systems can be targeted to an FPGA using the developed DSL. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： field programmable gate arrays (FPGA)

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Runtime Verification on FPGAs with LTLf Specifications 20

Runtime Verification on FPGAs with LTLf Specifications

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20th international conference on Formal Methods in Computer-Aided Design, FMCAD 2020

作者： Tracy, Tommy Tabajara, Lucas M. Vardi, Moshe Skadron, Kevin University of Virginia CharlottesvilleVA22904 United States Rice University HoustonTX77005 United States

ISBN: (纸本)9783854480426

Runtime verification is a technique that evaluates a system's execution trace at runtime against a formal specification. this approach is particularly useful for safety-critical and autonomous systems to verify system functionality and allow for graceful recovery or intervention in the case of system faults. Specifications are often provided in a high-level form using some type of temporal logic, which can then be compiled into an automaton to be used as a monitor for the system. Existing work has mainly focused on implementing such monitors in software. In recent years there has been extensive research, however, in hardware acceleration of automata applications, which can potentially be extended to runtime monitoring. In this paper, we introduce an open-source framework for translating formulas in Linear Temporal logic over finite traces (LTLf) into automata implementations on FPGAs for high-efficiency and high-performance runtime monitoring. By using the spatial dimension of FPGAs, we run many of these automata in parallel, significantly reducing the latency between violation and monitor report and achieving significant throughput. We compare the performance of four different architectures corresponding to the combinations of deterministic or nondeterministic automata with an explicit or symbolic representation, and determine the design parameters that result in efficient hardware utilization and higher clock frequencies. We found that explicit automata tend to use more hardware resources, in particular Lookup Tables (LUTs), than symbolic automata. An exception to this is in the case of Flip-Flop (FF) usage, where symbolic DFAs tend to use more FF resources than explicit NFAs for smaller designs. We also found that explicit NFAs can run at higher clock frequencies, except for very large automata with high edge densities. Symbolic NFAs use fewer Look-Up Table resources and run at higher clock frequencies than symbolic DFAs, whereas symbolic DFAs required fewer Flip

关键词： field programmable gate arrays (FPGA)

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Accelerating design convergence of automata processing designs with a tiled hierarchy 6

Accelerating design convergence of automata processing desig...

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6th international Workshop on FPGAs for Software Programmers, FSP 2019, co-located with international conference on field programmable logic and applications, FPL 2019

作者： Tracy, Tommy Wadden, Jack Xie, Ted Skadron, Kevin Stan, Mircea University of Virginia CharlottesvilleVA United States University of Michigan Ann HarborMI United States University of Virginia CharlottesvilleVA United States Google Mountain ViewCA United States

ISBN: (纸本)9783800750467

Automata Processing is a parallel processing technique used to compute massive pattern matching queries on an input stream of data;among other applications, it is a popular approach to computing regular expressions. Automata processing with FPGAs achieves high performance by spatially representing these automata and distributing the input stream across all state machines to run in parallel. Existing automata-to-FPGA tools emit one, large, flat design lacking any hierarchy, where all automata sub-components make up one flat RTL file. We found that FPGA toolchains are poorly designed for large, flat designs and result in high synthesis times and poor Quality of Results. this limits the practical usefulness of current automata-on-FPGA approaches. We propose a technique to improve automata-to-FPGA mapping by automatically imposing a design hierarchy without changing RTL functionality, preventing the over-optimization in synthesis that led to excessively long compiler runtimes. We experimentally evaluate our technique by implementing an accelerated Learn to Rank machine learning automata application on FPGAs in Amazon's F1 cloud. We demonstrate successful place-and-route at full frequency of previously unsynthesizable designs and greatly reduced synthesis time (up to 50%) at a cost of a few percentage points more logic resources. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： field programmable gate arrays (FPGA)

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A case study in using OpenCL on FPGAs: Creating an open-source accelerator of the autodock molecular docking software 5

A case study in using OpenCL on FPGAs: Creating an open-sour...

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5th international Workshop on FPGAs for Software Programmers, FSP 2018, co-located with international conference on field programmable logic and applications, FPL 2018

作者： Solis-Vasquez, Leonardo Koch, Andreas Group Darmstadt Germany

ISBN: (纸本)9783800747238

In recent years, OpenCL has been increasingly adopted as it enables software programmers to harness the performance and power efficiency of FPGAs. Despite simplifying the FPGA programming challenge, achieving high performance and energy efficiency with OpenCL is still a difficult task. In order to further contribute to the advance of the OpenCL usage for FPGAs, we utilize a realistic application scenario as our case study: the AutoDock molecular docking software. While OpenCL has proven its effectiveness in accelerating molecular docking on GPUs, for FPGA-based AutoDock accelerators it struggles with difficult design patterns. Besides complex multiple-producers to single-consumer datapaths, these include time-intensive loops with variable runtimes. therefore, this work presents the design and optimization steps for implementing AutoDock in OpenCL targeting an Arria-10 FPGA, as well as a corresponding execution runtime and energy-efficiency evaluation. Applying these techniques improved the performance of the initial OpenCL implementation for FPGAs by three orders of magnitude, with the final version of the code now yielding speed-ups of up to ∼2.7x, and energy-efficiency gains of up to ∼1.8x over the original serial AutoDock version executing on a current-generation CPU∗. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： field programmable gate arrays (FPGA)

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HyperLogLog Sketch Acceleration on FPGA

HyperLogLog Sketch Acceleration on FPGA

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international conference on field programmable logic and applications

作者： Amit Kulkarni Monica Chiosa thomas B. Preußer Kaan Kara David Sidler Gustavo Alonso Systems Group ETH Zürich Switzerland ETH Zurich Switzerland Microsoft Corporation Redmond WA USA

ISBN: (数字)9781728199023

ISBN: (纸本)9781728199030

Data sketches are a set of widely used approximated data summarizing techniques. their fundamental property is sub-linear memory complexity on the input cardinality, an important aspect when processing streams or data sets with a vast base domain such as URLs, IP addresses, user IDs, etc. Among the many data sketches available, HyperLogLog has become the reference for cardinality counting i.e., how many distinct data items there are in a data set. Although it does not count every data item but provides probabilistic guarantees on the result thereby reducing its memory footprint, and the result is often used to analyze data streams. In this paper, we explore how to implement HyperLogLog on an FPGA to benefit from the parallelism available and the ability to process data streams coming from high-speed networks. Our multi-pipelined high-cardinality HyperLogLog implementation delivers 1.8x higher throughput than the best-optimized multi-thread HyperLogLog running on a dual-socket Intel Xeon E5-2630 v3 system with a total of 16 cores and 32 hyper-threads.

关键词： field programmable gate arrays Estimation Data processing Hardware Acceleration throughput TCPIP

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