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Efficient Floating-Point HUB Adder For FPGA

Efficient Floating-Point HUB Adder For FPGA

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international conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech)

作者： Machupalli Lahari Sonali Agrawal Amrita School of Engineering Bengaluru Amrita Vishwa Vidyapeetham India

ISBN: (数字)9781728192871

ISBN: (纸本)9781728192888

the utilization of Floating Point (FP) numbers had increased due to the complications of recent Digital signal processing (DSP) applications. In field-programmable gate arrays, to execute digital signal applications, HUB formats are used. By using this floating-point HUB format, the logic of rounding can be eliminated. the HUB format lessens the resource utilization and increases the speed of floating-point units. At the same time, it is providing the equivalent accuracy when compared to the conventional formats. In this paper, a double path floating-point HUB adder with Spurious Power Suppression Technique (SPST) is proposed. this adder is coded in Verilog, simulated and synthesized using Xilinx ISE 14.2 and Virtex-6 FPGA, xc6vlx240 is used to implement it. the performance of proposed adder is analysed and compared with existing double path HUB adder. the proposed HUB adder with SPST is improved with respect to power and delay as compare to existing HUB adder.

关键词： Adders Computer architecture Delays field programmable gate arrays Power demand logic gates Latches

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A Seamless DFT/FFT Self-Adaptive Architecture for Embedded Radar applications

A Seamless DFT/FFT Self-Adaptive Architecture for Embedded R...

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international conference on field programmable logic and applications

作者： Julien Mazuet Michel Narozny Catherine Dezan Jean-Philippe Diguet Thales LAS-France Élancourt France Lab-STICC CNRS UBO / UBS Brest France

ISBN: (数字)9781728199023

ISBN: (纸本)9781728199030

Radar is one of the domains where adaptability is paramount. Depending on the current system state, the radar algorithms must be adapted. However, most systems include static hardware implementations on FPGA or ASIC to process the massive amount of data from multiple sensors in parallel. the classic approach is to configure hardware logic through registers to switch radar modes, requiring to hardwire all configurations. However, in embedded radar systems the hardware resources are very limited and this solution is not optimal. An innovative solution relies on the FPGA reconfigurable nature to use multiple configurations and limit resources overhead. In this paper, we present a dynamic partial reconfiguration (DPR) application for radar processing, which allows to switch between a classic discrete Fourier transform (DFT) sum and a fast Fourier transform (FFT) to enhance Doppler extraction. Our study explores the pros and cons of both methods. Based on these observations, we propose a decision method for enabling an efficient self-adaptive solution. Finally, we provide a case study with a reconfigurable radar implementation which uses the current system state to take full advantage of both Fourier transform methods.

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logicNets: Co-Designed Neural Networks and Circuits for Extreme-throughput applications

LogicNets: Co-Designed Neural Networks and Circuits for Extr...

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international conference on field programmable logic and applications

作者： Yaman Umuroglu Yash Akhauri Nicholas James Fraser Michaela Blott Xilinx Research Labs Dublin Ireland

ISBN: (数字)9781728199023

ISBN: (纸本)9781728199030

Deployment of deep neural networks for applications that require very high throughput or extremely low latency is a severe computational challenge, further exacerbated by inefficiencies in mapping the computation to hardware. We present a novel method for designing neural network topologies that directly map to a highly efficient FPGA implementation. By exploiting the equivalence of artificial neurons with quantized inputs/outputs and truth tables, we can train quantized neural networks that can be directly converted to a netlist of truth tables, and subsequently deployed as a highly pipelinable, massively parallel FPGA circuit. However, the neural network topology requires careful consideration since the hardware cost of truth tables grows exponentially with neuron fan-in. To obtain smaller networks where the whole netlist can be placed-and-routed onto a single FPGA, we derive a fan-in driven hardware cost model to guide topology design, and combine high sparsity with few-bit activation quantization to limit the neuron fan-in. We evaluate our approach on two tasks with very high intrinsic throughput requirements in high-energy physics and network intrusion detection. We show that the combination of sparsity and few-bit activation quantization results in high-speed circuits with small logic depth and low LUT cost, demonstrating competitive accuracy with less than 15 ns of inference latency and throughput in the hundreds of millions of inferences per second.

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Power-Aware High-Level Synthesis Flow for Mapping FPGA Designs 5

Power-Aware High-Level Synthesis Flow for Mapping FPGA Desig...

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Moratuwa Engineering Research conference (MERCon) / 5th international Multidisciplinary Engineering Research conference

作者： Kanewala, Udaree Gamlath, Kesara Ramanayake, Hasindu Herath, Kalindu Nawinne, Isuru Ragel, Roshan Univ Peradeniya Dept Comp Engn Peradeniya Sri Lanka Nanyang Technol Univ Sch Comp Sci & Engn Jurong West Singapore

ISBN: (纸本)9781728136325

Present field programmable Gate Array (FPGA) manufacturers incorporate multi-millions of logic resources which enables hardware designers to design applications extending to large scales. However, handling such applications by existing FPGA Computer Aided Design (CAD) flow requires more improvement in terms of area, performance and power efficiency considerations. the current CAD flow requires the input design to be in Register Transfer Level (RTL). RTL input designs limit the design productivity only to hardware experts in performing analysis for various optimisations. Optimising RTI, designs manually are increasingly hard. High Level Synthesis (HLS) is an approach capable of increasing the design productivity of hardware applications compared to commonly used Hardware Description Languages (HDLs) and is known to be an intelligent approach for performing optimisations at a higher level of abstraction. In this paper, an approach that follows the HLS flow to cater to the mapping of FPGA applications in a power efficient manner using a communication aware partitioning strategy is proposed. From experiments, it was possible to achieve an average reduction of 8.39% routing thermal power and 3.34% total power using the proposed approach

关键词： field programmable Gate Array High-Level Synthesis Hardware Description Language Register Transfer Level Computer Aided Design Modular Design Methodology Intermediate Representation

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Accelerating Local Laplacian Filters on FPGAs

Accelerating Local Laplacian Filters on FPGAs

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international conference on field programmable logic and applications

作者： Shashwat Khandelwal Ziaul Choudhury Shashwat Shrivastava Suresh Purini Computer Systems Group International Institute of Information Technology Hyderabad India

ISBN: (数字)9781728199023

ISBN: (纸本)9781728199030

Images when processed using various enhancement techniques often lead to edge degradation and other unwanted artifacts such as halos. these artifacts pose a major problem for photographic applications where they can denude the quality of an image. there is a plethora of edge-aware techniques proposed in the field of image processing. However, these require the application of complex optimization or post-processing methods. Local Laplacian Filtering is an edge-aware image processing technique that involves the construction of simple Gaussian and Laplacian pyramids. this technique can be successfully applied for detail smoothing, detail enhancement, tone mapping and inverse tone mapping of an image while keeping it artifact-free. the problem though with this approach is that it is computationally expensive. Hence, parallelization schemes using multi-core CPUs and GPUs have been proposed. As is well known, they are not power-efficient, and a well-designed hardware architecture on an FPGA can do better on the performance per watt metric. In this paper, we propose a hardware accelerator, which exploits fully the available parallelism in the Local Laplacian Filtering algorithm, while minimizing the utilization of on-chip FPGA resources. On Virtex-7 FPGA, we obtain a 7.5x speed-up to process a 1 MB image when compared to an optimized baseline CPU implementation. To the best of our knowledge, we are not aware of any other hardware accelerators proposed in the research literature for the Local Laplacian Filtering problem.

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Multi-channel high-linearity time-to-digital converters in 20 nm and 28 nm FPGAs for LiDAR applications

Multi-channel high-linearity time-to-digital converters in 2...

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international conference on Event-based Control, Communication, and Signal Processing (EBCCSP)

作者： Wujun Xie Haochang Chen Zhenya Zang David Day-Uei Li Faculty of Science University of Strathclyde Glasgow

ISBN: (数字)9781728195810

ISBN: (纸本)9781728195827

this paper proposes a new calibration method, the mixed-binning method, to pursue a TDC with high linearity in field-programmable gate arrays (FPGAs). this method can reduce the nonlinearity caused by large clock skews in FPGAs efficiently. therefore, a wide dynamic range tapped delay line (TDL) TDC has been developed with maintained linearity. We evaluated this method in Xilinx 20nm UltraScale FPGAs and Xilinx 28nm Virtex-7 FPGAs. Results conduct that this method is perfectly suitable for driverless vehicle applications which require high linearity with an acceptable resolution. the proposed method also has great potentials for multi-channel applications, due to the low logic resource consumption. For a quick proof-of-concept demonstration, an 8-channel solution has also been implemented. It can be further extended to a 64-channel version soon.

关键词： field programmable gate arrays Clocks Linearity Calibration Laser radar Table lookup Semiconductor device measurement

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Hardware Accelerator for Edge Detection

Hardware Accelerator for Edge Detection

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IEEE international conference on Intelligent Engineering Systems (INES)

作者： Aous H. Kurdi Janos L. Grantner Ikhlas Abdel-Qader Department of Electrical and Computer Engineering Western Michigan University Kalamazoo MI USA

ISBN: (数字)9781728110592

ISBN: (纸本)9781728110608

Hardware accelerators have been recently proposed for computationally extensive applications like real-time video image processing systems. Contemporary hardware accelerators are implemented by using either field programmable Gate Array (FPGA) or System-on-Chip (SoC) devices. Edge detection is a fundamental task for any image processing system. In this paper, a pipelined architecture for a fuzzy logic edge detection system is proposed. the system has been implemented and tested on various Xilinx 7 Series devices. the hardware accelerator core utilizes a pipeline of seven stages. Depending on the available resources the accelerator system can be made up of several cores operating simultaneously. A single-core implementation of the system can process a 1080P HD test frame at a rate of about 45 frames per second. It outperforms its software counterpart by a factor of ten thousand.

关键词： Hardware Image edge detection Fuzzy logic Pipelines field programmable gate arrays Real-time systems

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A Review of Different Methods of Phase Measurement and its Suitable applications 5

A Review of Different Methods of Phase Measurement and its S...

引用

IEEE 5th international conference for Convergence in Technology (I2CT)

作者： Phillimon, Marim Alan Devi, Salem Devayani Singh, Loitongbam Surajkumar NIT Manipur Dept ECE Imphal 795004 Manipur India

ISBN: (纸本)9781538680759

the phase measurement technique using field programmable Gate Arrays (FPGAs) is a considerable improvement over previously available methods. It involves designing of simple suitable logic core, employing an improved method for sampling, simple design with less hardware and also with the introduction of the XOR-based phase detector to minimize jitter, thus achieving high accuracy and resolution and operate over a large range of frequency which is supported by the FPGA fabric. However, it is important to consider that there are different FPGAs based phase measurement techniques and are used in different applications considering each methods suits better in particular specific application. this paper presents a brief review of various methods for phase measurement, based on FPGA board, using various concepts and techniques in varied fields of science and technology.

关键词： Phase detector phase measurement FPGA-based phase measurement XOR-based phase detector

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FP-Stereo: Hardware-Efficient Stereo Vision for Embedded applications

FP-Stereo: Hardware-Efficient Stereo Vision for Embedded App...

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international conference on field programmable logic and applications

作者： Jieru Zhao Tingyuan Liang Liang Feng Wenchao Ding Sharad Sinha Wei Zhang Shaojie Shen Hong Kong University of Science and Technology Alibaba Group India Institute of Technology Goa

ISBN: (数字)9781728199023

ISBN: (纸本)9781728199030

Fast and accurate depth estimation, or stereo matching, is essential in embedded stereo vision systems, requiring substantial design effort to achieve an appropriate balance among accuracy, speed and hardware cost. To reduce the design effort and achieve the right balance, we propose FP-Stereo for building high-performance stereo matching pipelines on FPGAs automatically. FP-Stereo consists of an open-source hardware-efficient library, allowing designers to obtain the desired implementation instantly. Diverse methods are supported in our library for each stage of the stereo matching pipeline and a series of techniques are developed to exploit the parallelism and reduce the resource overhead. To improve the usability, FP-Stereo can generate synthesizable C code of the FPGA accelerator with our optimized HLS templates automatically. To guide users for the right design choice meeting specific application requirements, detailed comparisons are performed on various configurations of our library to investigate the accuracy/speed/cost trade-off. Experimental results also show that FP-Stereo outperforms the state-of-the-art FPGA design from all aspects, including 6.08% lower error, 2x faster speed, 30% less resource usage and 40% less energy consumption. Compared to GPU designs, FP-Stereo achieves the same accuracy at a competitive speed while consuming much less energy.

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Research and implementation of an automatic simulation tool

Research and implementation of an automatic simulation tool

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international conference on Dependable Systems and their applications (DSA)

作者： Liu Tang You Li Hongwei Wang Huan Zhao Luze Ma Yuming Sun Beijing Sunwise Information Technology Ltd. China

ISBN: (数字)9780738124223

ISBN: (纸本)9781665419536

With the rapidly increasing of space missions, FPGA is more widely used for its ability of single chip approaching 10 million gates of logic and 10 million bits of memory. More and more challenges are posed to FPGA design and verification, with the characteristics of a tight schedule, a burdensome task, momentous responsibilities, etc. A reusable and robust environment for verification is needed to improve the efficiency and quality of verification. In this paper, we present a series of research works, including what kinds of simulation techniques should be used and which methodology should be addressed. By using the Universal Verification Methodology (UVM) template, the verification modeling is done by us, and verification code is generated with FPGA automatic simulation tool (SunwiseFAS). the performance of this tool on automatic constructing simulation environment is presented, too.

关键词： Schedules Space missions Tools logic gates Task analysis field programmable gate arrays

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