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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1845 条记录，以下是21-30 订阅

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5th international Workshop on FPGAs for Software Programmers, FSP 2018, co-located with international conference on field programmable logic and applications, FPL 2018

5th International Workshop on FPGAs for Software Programmers...

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5th international Workshop on FPGAs for Software Programmers, FSP 2018, co-located with international conference on field programmable logic and applications, FPL 2018

ISBN: (纸本)9783800747238

the proceedings contain 9 papers. the topics discussed include: using Linux FIFOs to allow flexible hardware/software communications on reconfigurable systems-on-chip;improved parallelization of legacy embedded software on soft-core MPSoCs through automatic loop transformations;exact mapping of rewritten linear functions to configurable logic;ZUCL: a ZYNQ UltraScale+ framework for OpenCL HLS applications;unfolding and folding: a new approach for code restructuring targeting HLS for FPGAs;HatScheT: a contribution to agile HLS;LeFlow: enabling flexible fpga high-level synthesis of tensorflow deep neural networks;a case study in using OpenCL on FPGAs: creating an open-source accelerator of the AutoDock molecular docking software;and a journey into DSL design using generative programming: FPGA mapping of image border handling through refinement.

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Proceedings - 29th international conference on field-programmable logic and applications, FPL 2019

Proceedings - 29th International Conference on Field-Program...

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29th international conferenceon field-programmable logic and applications, FPL 2019

ISBN: (纸本)9781728148847

the proceedings contain 71 papers. the topic discussed include: reducing dynamic power in streaming CNN hardware accelerators by exploiting computational redundancies;Limago: an FPGA-based open-source 100 GbE TCP/IP stack;a high-performance CNN processor based on FPGA for MobileNets;measuring long wire leakage with ring oscillators in cloud FPGAs;real-time multi-pedestrian detection in surveillance camera using FPGA;pyramid: machine learning framework to estimate the optimal timing and resource usage of a high-level synthesis design;timing-aware routing in the RapidWright framework;and beyond the limits: SHA-3 in just 49 slices.

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90 Degree Video Rotation Design Based on FPGA 5

90 Degree Video Rotation Design Based on FPGA

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5th international conference on Computer Vision, Image and Deep Learning, CVIDL 2024

作者： Mei, Weichun Lu, Zhiyang Yang, Zhengyu Zhu, Genwang Liang, Laili East China Normal University School of Communication and Electronics Engineering Shanghai200241 China

ISBN: (纸本)9798350373820

In order to reduce the resource overhead of video rotation processing without compromising the video display quality, a custom method based on the FPGA platform was adopted to process real-time video streams with 90-degree rotations. the read and write logic design from the FPGA end to the DDR3 SDRAM end was completed, utilizing a three-level cache for ping-pong operation and a multi-channel read/write arbitration module for channel management to achieve real-time image caching. Experimental results indicate that the video rotation scheme designed in this project enables real-time rotation by 90 degrees for videos of arbitrary resolutions without additional DSP and interpolation algorithm logic. It consumes less FPGA logic resources, occupying only 418 Slice LUTs, 494 Slice Registers and 1 DSP resources. the image is clear and smooth, without flickers, jitter and misalignment. It is especially suitable for applications where the digital logic area is tight or the cost is high. © 2024 IEEE.

关键词： field programmable gate arrays (FPGA)

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FPGA-based CNN Acceleration using Pattern-Aware Pruning 6

FPGA-based CNN Acceleration using Pattern-Aware Pruning

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6th international conference on AI Circuits and Systems (AICAS)

作者： Pradels, Leo Filip, Silviu-Ioan Sentieys, Olivier Chillet, Daniel Le Calloch, thibaut Univ Rennes CNRS Inria F-35000 Rennes France Safran Elect & Def F-95610 Eragny France

ISBN: (纸本)9798350383638;9798350383645

While convolutional neural networks (CNNs) have demonstrated exceptional performance in computer vision, optimizing FPGA-based CNN accelerators remains a challenge due to resource constraints. this is especially true for sequential designs, which are limited by external memory access. Despite the benefits of sparsity, most existing sparse accelerators are sequential and memory-bound. We introduce an innovative dataflow CNN architecture enriched with structured sparsity through pattern pruning at tile level. In our approach, pattern pruning serves as a fine-tuning step, effectively reducing FPGA resource consumption, including memory and logic. Experimental results indicate better latency than other dataflow approaches, while maintaining competitive accuracy compared to state-of-the-art unstructured pruning methods. We demonstrate the versatility of our approach in image classification and super-resolution applications, where we achieve a consistent 30 frames per second across a wide range of image sizes on the Set5 dataset.

关键词： field programmable gate arrays (FPGA)

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Design and Simulation of RISC Processor Using Verilog 5

Design and Simulation of RISC Processor Using Verilog

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5th international conference on Inventive Research in Computing applications, ICIRCA 2023

作者： Sudhanya, P. Kumar, Aryan Sharma, Tushar Agrawal, Akshat Srm Institute of Science and Technology Faculty of Engineering and Technology Department of Electronics and Communication Engineering Kattankulathur603203 India

ISBN: (纸本)9798350321425

Reduced Instruction Set Computer (RISC) Processors have recently become quite an important aspect of keeping up with all the advances in technology. this research presents a comprehensive study on the design and simulation of an improved RISC processor architecture on field-programmable Gate Arrays (FPGAs). the objective is to enhance the performance, efficiency, and versatility of RISC processors by incorporating novel design techniques and optimizations. the proposed design mainly focuses on the improved design of the Arithmetic and logic Unit (ALU). the effectiveness of the proposed design is evaluated through extensive simulations. the results demonstrate significant improvements in performance in time and total power. the findings of this study indicate that the improved RISC processor design offers a promising approach to address the increasing demands of modern computing systems. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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Design and Optimization of a Citrus Essential Oil Extraction System by Steam Distillation with Automated Control in Lima, Peru 9

Design and Optimization of a Citrus Essential Oil Extraction...

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9th international conference on Automation, Control and Robotics Engineering (CACRE)

作者： Torres-Taipe, Anderson Luigui Zevallos-Crisostomo, Nikolt Mijail Sullca-Mendoza, Yordan Cesar Berann-Espiritu, Manuel Michael Univ Continental Sch Mechatron Engn Huancayo Peru

ISBN: (纸本)9798350350319;9798350350302

the production of essential oils is widely used in the world to combat various diseases. In addition, these oils are essential in the seasoning and flavoring of food and have applications in the field of cosmetology, helping to reduce environmental pollution by avoiding the use of chemical products. Peru is one of the fourteen most outstanding countries for its rich biodiversity in flora and fauna, and is also the sixth largest exporter of citrus fruits in the world. therefore, a citrus essential oil extraction process is analyzed through the design of an industrial-scale essential oil distillation machine. this design includes the automation of the filling and emptying of the distiller to improve the results, as well as the implementation of a closed-loop control system for cooling. the objective is to facilitate operator control and monitoring of the cooling and water filling process through a control panel. After analyzing the distillation process, an average of 1% to 2% of essential oil and 50% of citrus peel hydrolate has been obtained, setting a new standard in the production of essential oils in the country.

关键词： Steam distillation Natural essences Automated control Essence distillation equipment Citrus peel programmable logic Controller

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FPGA Design of a Reconfigurable UART IP Core and its SoC Implementation for IoT applications 25

FPGA Design of a Reconfigurable UART IP Core and its SoC Imp...

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25th international Multi Topic conference, INMIC 2023

作者： Asad Ali, M. Adeel Pasha, M. Masud, Shahid Ghazali, Fahad Al Department of Electrical Engineering Lahore Pakistan Islamabad Pakistan

ISBN: (纸本)9798350317701

Data interruption during serial transmission is a commonly encountered issue. It is mostly caused by inappropriate buffer size allocation between the two Universal Asynchronous Receiver Transmitter (UART) modules to store the entire data chunk being sent or received. this problem can be mitigated if both modules can communicate with each other to adjust the size of their Transmit (Tx) and Receive (Rx) buffers through either static or dynamic reconfiguration. In our proposed design, both these approaches have been used to modify the typical UART architecture. In the 'Instantiation' mode, the sizes of Tx and Rx buffers are specified statically when the core is instantiated in a project during simulation and synthesis steps. In the 'Runtime' mode, the buffer sizes are dynamically adjusted based on the communication between the CPUs at the two ends. In the later case, the Tx UART modifies its own buffer size and then sends control packets to configure the size of the Rx UART preceding the data transfer. A System-on-Chip (SoC) based on RISC-V SwerRV IP Core and the modified 16550 UART IP Core has been developed, tested, and synthesized for both Artix-7 FPGA and TSMC 180nm ASIC technologies. the design demonstrated correct UART behavior while adding configurable data buffers at both ends to provide non-blocking data transfers up to a buffer size of 32KB. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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Assessing the Robustness of Real-Time Operating System on Soft Processor against Multiple Bit Upset 23

Assessing the Robustness of Real-Time Operating System on So...

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20th ACM international conference on Computing Frontiers, CF 2023

作者： Portaluri, Andrea De Sio, Corrado Sterpone, Luca Dipartimento di Automatica e Informatica Politecnico di Torino Turin Italy

ISBN: (纸本)9798400701405

field-programmable Gate Arrays (FPGAs) are becoming increasingly important for space applications due to their high flexibility, performance, and complexity. In particular, soft-core processors like Xilinx Microblaze are commonly implemented using the programmable logic of FPGAs, making them suitable for embedded applications. However, the netlist of soft microprocessors can be corrupted by the effects of radiation-induced soft errors, in particular Single-Event Effects (SEUs) [1-5]. this work presents a detailed evaluation of the impact of radiation-induced architectural faults affecting the application benchmarks running on the FreeRTOS of the Microblaze embedded soft processor. the effect of Multiple Bits Upsets (MBU) faults during the execution of different software applications on FreeRTOS supported by Microblaze implemented on Zynq-7020 FPGA was evaluated, and the outcome of the software application was investigated. Please, notice that the developed platform is targeting only hardware faults and their impact on the execution of the software running in the operating system. © 2023 Owner/Author.

关键词： Space applications

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A low-cost 4 ps root-mean-square resolution time-todigital converter implemented in a 28 nm field-programmable gate array

A low-cost 4 ps root-mean-square resolution time-todigital c...

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7th international conference on Electronics Technology, ICET 2024

作者： Liu, Jinxin Deng, Peipei Liu, Juan Wang, Ying Microsystem and Terahertz Research Center China Academy of Engineering Physics Chengdu China

ISBN: (纸本)9798350363951

this paper presents the implementation of a 28 nm field-programmable gate array (FPGA)-based time-to-digital converter (TDC), which has both high resolution and low-cost characteristics. Due to the simple TDC structure, only a few resources are required, making it suitable for multi-channel applications. An eight-channel TDC was designed in this study. In addition, an automatic nonlinearity calibration logic is implemented within the FPGA, guaranteeing stable performance of the TDC over a wide temperature range. the test results show that the average bin size of a typical channel is 2.55 ps, and the single-shot precision is better than 4 ps. © 2024 IEEE.

关键词： Calibration

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Advanced Acceleration and Implementation of Convolutional Neural Networks on FPGAs 25

Advanced Acceleration and Implementation of Convolutional Ne...

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25th IEEE international conferences on High Performance Computing and Communications, 9th international conference on Data Science and Systems, 21st IEEE international conference on Smart City and 9th IEEE international conference on Dependability in Sensor, Cloud and Big Data Systems and applications, HPCC/DSS/SmartCity/DependSys 2023

作者： Jensen, Mikkel Jakobsen, Jesper Toft Sharifirad, Iman Boudjadar, Jalil Aarhus University Aarhus Denmark

ISBN: (纸本)9798350330014

In recent years, embedded platforms became attractive targets to deploy machine learning (ML) -empowered control and processing systems. However, securing a high performance executability to satisfy the hard real-time constraints of such systems on resource-limited platforms, such as FPGAs, is a challenging task. this paper introduces a methodology for deploying hardware-accelerated, adaptable convolutional neural networks (CNN) on embedded FPGA platforms. It enables automated synthesis of hardware IPs, instantiation of CNN architectures and mapping of the CNN layers processing to hardware IPs. this will result in iteration-free deployment reducing the expensive cost of HW synthesis, so that the acceleration hardware IPs are synthesized once and configured at runtime following the CNN architecture. To demonstrate the applicability and assess the performance of our deployment model, we implemented and deployed a segment-based acceleration of a image classification CNN on Xilinx ZYBO Z7 FPGA board. Among others, we have analyzed the computation performance, accuracy and trade-offs between CNN size, image segmentation size, resources utilization and scalability. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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