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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1847 条记录，以下是311-320 订阅

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Gray-Code TDC with Improved Linearity and Scalability for LiDAR applications

Gray-Code TDC with Improved Linearity and Scalability for Li...

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international conference on Event-based Control, Communication, and Signal Processing (EBCCSP)

作者： Rui Machado Filipe Serra Alves Jorge Cabral Algoritmi Centre University of Minho Guimarães Portugal International Iberian Nanotechnology Laboratory Braga Portugal

ISBN: (数字)9781728195810

ISBN: (纸本)9781728195827

this paper presents a TDC architecture based on a gray code oscillator with improved linearity, for FPGA implementations. the proposed architecture introduces manual routing as a method to improve the TDC linearity and precision, by controlling the gray code oscillator Datapath, which also reduces the need for calibration mechanisms. Furthermore, the proposed manual routing procedure improves the performance homogeneity across multiple TDC channels, enabling the use of the same calibration module across multiple channels, if further improved precision is required. the proposed TDC channel uses only 16 FPGA logic resources (considering the Xilinx 7 series platform), making it suitable for applications where a large number of measurement channels are required. To validate the proposed architecture and routing procedure, two channels were integrated with a coarse counter, a FIFO memory and an AXI interface, to assemble the pulse measurement unit. A comparison between the default routing implementation and the proposed manual routing has been performed, shown an improvement of 27% on the overall TDC single-shot precision. the implemented TDC achieved a 380 ps RMS resolution, a maximum DNL of 0.38 LSB and a peak-to-peak INL of 0.69 LSB, corresponding to a 21.7% and 70.4% improvement, respectively, when compared to the default design approach.

关键词： Reflective binary codes Clocks Table lookup field programmable gate arrays Laser radar Oscillators Routing

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A Self-Calibrating True Random Number Generator

A Self-Calibrating True Random Number Generator

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international conference on field programmable logic and applications

作者： Adriaan Peetermans Miloš Grujić Vladimir Rožić Ingrid Verbauwhede KU Leuven Leuven Belgium imec-COSIC KU Leuven Kasteelpark Arenberg 10 Leuven-Heverlee Belgium

True Random Number Generators (TRNGs) are essential in all security systems. Unfortunately, large design effort is required to ensure that a TRNG design on a field-programmable Gate Array (FPGA) generates a sufficient entropy density at its output. this design effort relates to the fact that for each FPGA family a manual placement and routing procedure has to be executed. On top of this often comes the additional effort of finding a suitable location inside the target FPGA. this searching procedure has to be repeated for every device separately. In this demo, we show the working of a novel entropy source for the Coherent Sampling Ring Oscillator (COSO) based TRNG. this entropy source eliminates the need for any manual intervention during the implementation process. It generates two oscillating signals that can be matched with a precision of a few picoseconds. A controller regulates this entropy source based on some predefined bounds on the period length difference of the two oscillating signals.

关键词： field programmable gate arrays Generators Entropy Graphical user interfaces Monitoring Manuals Ring oscillators

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Hierarchical Force-Based Block Spreading for Analytical FPGA Placement 28

Hierarchical Force-Based Block Spreading for Analytical FPGA...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Vercruyce, Dries Vansteenkiste, Elias Stroobandt, Dirk Univ Ghent Comp Syst Lab Dept Elect & Informat Syst Ghent Belgium

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Enabling efficient FPGA application development requires fast design compilation to high quality FPGA configurations. Placement and routing are the most challenging compilation steps. A promising trend to accelerate the placement problem is the use of iterative analytical placement techniques. Each iteration in these placers consists of an optimization and a legalization phase. the legalization phase is an important part of the technique, reducing block overlap in the optimized placements. In this work we propose a hierarchical pushing force based block spreader that improves the legalization of CLBs. Overlap is reduced as the blocks push each other away under the influence of gravity, like a drop of water flowing over a surface. the algorithm is designed with parallelism in mind, making it suitable for GPU acceleration. the regularity of FPGAs is exploited to accelerate the calculations. Moreover, it further builds on a hierarchical FPGA CAD tool flow to enhance quality of results and runtime scalability. the spreading legalizer is embedded in the LIQUID placement technique. It replaces the default partitioning-based legalizer for sparse designs. the result is a reduction of 7.4% in post-routing total wire-length, without giving in on runtime. the source code is publicly available in the FPGA CAD framework on Github.

关键词： Force field programmable gate arrays Acceleration Liquids Runtime Annealing Optimization

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DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration 28

DLA: Compiler and FPGA Overlay for Neural Network Inference ...

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28th international conference on field programmable logic and applications (FPL)

作者： Abdelfattah, Mohamed S. Han, David Bitar, Andrew DiCecco, Roberto O'Connell, Shane Shanker, Nitika Chu, Joseph Prins, Ian Fender, Joshua Ling, Andrew C. Chiu, Gordon R. Intel Programmable Solut Grp Toronto ON Canada

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Overlays have shown significant promise for field programmable gate-arrays (FPGAs) as they allow for fast development cycles and remove many of the challenges of the traditional FPGA hardware design flow. However, this often comes with a significant performance burden resulting in very little adoption of overlays for practical applications. In this paper, we tailor an overlay to a specific application domain, and we show how we maintain its full programmability without paying for the performance overhead traditionally associated with overlays. Specifically, we introduce an overlay targeted for deep neural network inference with only 1% overhead to support the control and reprogramming logic using a lightweight very-long instruction word (VLIW) network. Additionally, we implement a sophisticated domain specific graph compiler that compiles deep learning languages such as Caffe or Tensorfiow to easily target our overlay. We show how our graph compiler performs architecture-driven software optimizations to significantly boost performance of both convolutional and recurrent neural networks (CNNs/RNNs) we demonstrate a 3x improvement on ResNet101 and a 12 x improvement for long short-term memory (LSTM) cells, compared to naive implementations. Finally, we describe how we can tailor our hardware overlay, and use our graph compiler to achieve similar to 900 fps on GoogLeNet on an Intel Arria 10 1150 - the fastest ever reported on comparable FPGAs.

关键词： Kernel field programmable gate arrays Artificial neural networks Hardware VLIW Computer architecture

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An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug 28

An FPGA Overlay Architecture Supporting Rapid Implementation...

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28th international conference on field programmable logic and applications (FPL)

作者： Jamal, Al-Shahna Goeders, Jeffrey Wilton, Steven J. E. Univ British Columbia Elect & Comp Engn Vancouver BC Canada Brigham Young Univ Elect & Comp Engn Provo UT 84602 USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

As field-programmable Gate Arrays become more complex, debugging designs implemented on these devices has become increasingly time-consuming. For many types of bugs, simulation is not sufficient, and the only way to uncover the root cause of unexpected behaviour is to run the design in hardware at speed. Many techniques that support on-chip debug have been described;typically, these techniques involve instrumenting the design to increase observability. In this paper, we describe instrumentation that not only increases observability, but that can also be used to control certain aspects of the design. Supported functional changes include applying small deviations in the control flow of the circuit, or the ability to override signal assignments to perform efficient "what if" tests. Our approach uses a novel overlay architecture which allows these changes to be implemented during debug without recompiling the design. Changes can be made in seconds, dramatically reducing the time to perform a debug iteration. Our overlay is specifically optimized for designs created using a high-level synthesis (HLS) flow;by taking advantage of information from the HLS tool, the overhead of the overlay can be kept low.

关键词： Instruments Debugging Tools Hardware System-on-chip Computer bugs field programmable gate arrays

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Automatic BRAM Testing for Robust Dynamic Voltage Scaling for FPGAs 28

Automatic BRAM Testing for Robust Dynamic Voltage Scaling fo...

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28th international conference on field programmable logic and applications (FPL)

作者： Ahmed, Ibrahim Zhao, Shuze Meijers, James Trescases, Olivier Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Recently FPGA researchers have proposed different approaches to enable dynamic voltage scaling (DVS) for FPGAs. While the proposed approaches have shown that DVS is able to significantly reduce FPGA power consumption, most of these solutions were developed only for the soft fabric of the FPGA and hence cannot be deployed for applications that use the FPGA hard blocks such as block RAMs (BRAMs). In this work, we extend a previously proposed offline calibration-based DVS approach to enable DVS for FPGAs with BRAMs;we build testing circuitry to ensure that all used BRAM cells operate safely while scaling V,H, and we develop testing procedures that are able to measure the delay of timing paths that start or end at BRAMs. We extend the CAD tool FRoC to automatically generate calibration designs with BRAM testers along with soft fabric testers to measure the actual.G,, of each application on any chip under different operating conditions;this information is stored in a calibration table that is then used when the application is running to scale Vdd to the minimum value that guarantees safe operation at the desired speed. Using our proposed solution, we show that we can run a discrete Fourier transform core with 32% and 46% power reduction compared to the conventional fixed-voltage operation at the reported F d and at a lower clock frequency, respectively.

关键词： Registers Voltage control field programmable gate arrays Delays Testing Calibration

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Fault Characterization through FPGA Undervolting 28

Fault Characterization Through FPGA Undervolting

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28th international conference on field programmable logic and applications (FPL)

作者： Salami, Behzad Unsal, Osman Cristal, Adrian BSC Barcelona Spain UPC Barcelona Spain

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

the power and energy efficiency of field programmable Gate Arrays (FPGAs) are estimated to be up to 20X less than Application Specific Integrated Circuits (ASICs). What is needed to close this gap is aggressive power/energy savings techniques. A such potentially effective approach is undervolting, which can directly deliver an order of magnitude static and dynamic power savings. However, aggressive undervolting, without accompanying frequency scaling leads to timing related faults, potentially undermining the power savings. Understanding the behavior of these faults and efficiently mitigating them can deliver further power and energy savings in low -voltage designs. In this paper, we conduct a detailed analysis of undervolting FPGA on chip memories (BRAMs). through experimental analysis, we find that lowering the supply voltage until a certain conservative level, V-min, does not introduce any observable fault. For the studied platforms, we measure this voltage guardband gap to be 39% of the nominal level (V-nom = 1V, V-min = 0.61V). Further undervolting corrupts some of data bits stored in BRAMs;however, it also reduces the BRAMs power consumption a further 36.1%. When the voltage is lowered below Vin, the rate of these faults exponentially increases to 0.06 %, by a fully non -uniform distribution over various BRAMs. this paper comprehensively analyzes the behavior of these faults, in terms of rate, type, location, and environmental temperature.

关键词： field programmable gate arrays Circuit faults Voltage measurement Power demand Hardware Standards Temperature

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Resource Reduction of BFGS Quasi-Newton Implementation on FPGA using Fixed-Point Matrix Updating 28

Resource Reduction of BFGS Quasi-Newton Implementation on FP...

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28th international conference on field programmable logic and applications (FPL)

作者： Liu, Jia Liu, Qiang Tianjin Univ Tianjin Key Lab Imaging & Sensing Microelect Tech Sch Microelect Tianjin Peoples R China

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Quasi-Newton (QN) methods are now widely used for NN training due to their high effectiveness. In practice, the iterative process of the QN methods implemented in software is often very time-consuming. To accelerate the training process, floating-point BFGS-QN implementation has been realized on FPGA. By analyzing the performance of the BFGS-QN implementation, it is found that updating the inverse of approximate Hessian matrix B is the most computation and memory intensive part. therefore, a fixed-point hardware design of B matrix updating is proposed in this paper. the fixed-point representation could lead to overflow and underflow during the computation, which degrade the convergence performance of the training process. To address the issues, matrix property checking and precision scaling schemes are proposed, giving a tradeoff between resource and precision. the experimental results show that compared with the single-precision floating-point BFGS-QN, the mixed precision BFGS-QN with fixed-point B matrix updating design achieves up to 10.9% LUTs, 20.2% FFs and 18.1% BRAMs reduction, while the training speed is not satisfied.

关键词： Training field programmable gate arrays Training data Hardware Convergence Artificial neural networks

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Median filtering with very large windows: SKA algorithms for FPGAs 28

Median filtering with very large windows: SKA algorithms for...

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28th international conference on field programmable logic and applications (FPL)

作者： Sherwin, Tyrone Wang, Kevin I-Kai thiagaraj, Prabu Sinnen, Oliver Univ Auckland Dept Elect & Comp Engn Auckland New Zealand Univ Manchester Manchester Lancs England Raman Res Inst Bangalore Karnataka India

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Large scale median filtering algorithms are investigated in the context of the Square Kilometre Array (SKA) pulsar search;a signal processing pipeline estimated to require more than 10POps on 60PB of search data collected per day. Real time performance is needed for rectangular median windows of 63 frequency channels across 1023 time steps, requiring at least 64 million values to be calculated and output per second. this paper proposes an algorithmic approach for large scale median filtering based on existing techniques, providing improvements for the heterogeneous system used and utilising a high-end FPGA accelerator. Taking advantage of OpenCL for rapid parameter sweeping, the design space was explored to find the best algorithmic approach. the evaluation results are promising and show output of up to 993 million values per second on an Arria-10 FPGA, coming close to the limits set by resources and bandwidth. these results are set into relation with GPU and CPU implementations for the same algorithm, taking advantage of the OpenCL portability, achieving up to 16.8 and 9.1Mvalue/s respectively.

关键词： Microsoft Windows Histograms field programmable gate arrays Signal processing algorithms Time-frequency analysis Loading Complexity theory

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Application Partitioning on FPGA Clusters: Inference over Decision Tree Ensembles 28

Application Partitioning on FPGA Clusters: Inference over De...

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28th international conference on field programmable logic and applications (FPL)

作者： Owaida, Muhsen Alonso, Gustavo Swiss Fed Inst Technol Dept Comp Sci Syst Grp Zurich Switzerland

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

In the same way multi-core and CPU clusters are used for large problems, multi-FPGA clusters are needed to tackle applications not fitting within a single FPGA, such as machine learning methods based on large models. Recent FPGA deployments in datacenters offer flexible pools of FPGAs that can be used in different configurations. In addition to those of a typical cluster architecture, FPGA clusters often have added capabilities such as being hosted by large server nodes (e.g., Amazon F1 Instance), or a network backbone directly connecting multiple FPGAs (e.g., Microsoft Catapult). While such designs open up many opportunities, mapping application logic onto a pool of FPGA resources is a non trivial task. It requires partitioning the application across multiple FPGAs, inter-FPGA communication management of multiple data stream classes, and balancing communication-computation bandwidth. In this paper, we explore and develop techniques for mapping a resource-intensive machine learning application, namely inference over decision tree ensembles on a datacenter-grade FPGA cluster. the FPGA cluster is built out of 20 Microsoft Catapult FPGA boards with a flexible inter-FPGA network topology. We developed a lightweight inter-FPGA communication protocol and routing layer to facilitate the communication between different parts of the application. Our evaluation provides insights on the overall performance benefits of the design and outlines some of the techniques needed to efficiently map applications onto a pool of distributed FPGAs.

关键词： field programmable gate arrays Servers Decision trees Distributed databases Bandwidth Machine learning Computer architecture

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