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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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Accelerated Wire-Speed Packet Capture at 200 Gbps 28

Accelerated Wire-Speed Packet Capture at 200 Gbps

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28th international conference on field programmable logic and applications (FPL)

作者： Kekely, Lukas Spinler, Martin Friedl, Stepan Sikora, Jiri Korenek, Jan CESNET Ale Zikova 4 Prague 16000 Czech Republic

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

We present our latest FPGA acceleration card NFB-200G2QL that is specifically designed to enable traffic processing at 200 Gbps. Unique high-speed DMA engines in the FPGA together with highly optimized Linux drivers enable data transfer through PCIe interfaces with minimal CPU overhead. Captured traffic can be independently distributed between individual cores of two physical CPUs (NUMA nodes) without utilization of QPI. As a result, wire-speed packet capture to the host memory from two fully saturated 100 Gbps Ethernet interfaces (QSFP28+ cages) is achieved and various network monitoring applications can utilize the power of the latest FPGAs and CPUs for data processing. this is especially useful when both directions of a single 100GbE link are monitored. the live demonstration shows how the packets are received from two 100 Gbps Ethernet links at wire-speed and captured to the host memory at 200 Gbps without a loss. the opposite direction of communication is also shown, i.e. how the packets are transmitted from the host memory and fully saturate the two 100GbE network interfaces. Achieved speeds are demonstrated by counters and gauges showing generated, received/transmitted and captured packets. We also show statistics of CPU load during the packet capture/transmission for different packet lengths.

关键词： field programmable gate arrays Ethernet throughput Data transfer Standards Acceleration Monitoring

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A FPGA Accelerator for Real-Time 3D Non-Rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random field Generation 28

A FPGA Accelerator for Real-Time 3D Non-Rigid Registration U...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Barrow, Michael Burns, Steven M. Kastner, Ryan Univ Calif San Diego La Jolla CA 92093 USA Intel Corp Hillsboro OR 97124 USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Non-rigid 3D registration is a technique for matching 3D scans of a scene involving deformable objects. Augmented reality, gesture recognition, medical imaging, and many other computer vision and graphics applications require realtime registration to model deformable or articulated objects. Unfortunately, non-rigid registration is a computationally intensive problem that requires careful optimization to maximize throughput and latency. We present a FPGA+CPU accelerator for real-time non-rigid 3D registration based on Tree Reweighted Message Passing (TRW-S). We overcome memory bound issues and scheduling limitations of conventional TRW-S by dynamically generating the Markov Random fields. this, along with a bevy of other architectural optimizations, allows us to almost saturate 1024 multipliers in a Arria 10 at 100MHz. We achieve a 600x speed up over baseline TRW-S and our registration architecture has up to 81x energy reduction over a software implementation of our algorithm. We demonstrate the performance of our system by performing real-time (20 scan per second) registration on a complicated surgical scene.

关键词： field programmable Gate Array (FPGA) 3D Non-Rigid Registration Sequential Tree Reweighted Message Passing (TRW-S) Dynamic Markov Random field (MRF)

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Towards Efficient Convolutional Neural Network for Domain-Specific applications on FPGA 28

Towards Efficient Convolutional Neural Network for Domain-Sp...

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28th international conference on field programmable logic and applications (FPL)

作者： Zhao, Ruizhe Ng, Ho-Cheung Luk, Wayne Niu, Xinyu Imperial Coll London Dept Comp London England Corerain Technol Ltd Shenzhen Peoples R China

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

FPGA becomes a popular technology for implementing Convolutional Neural Network (CNN) in recent years. Most CNN applications on FPGA are domain-specific, e.g., detecting objects from specific categories, in which commonly used CNN models pre-trained on general datasets may not be efficient enough. this paper presents TuRF, an end-to-end CNN acceleration framework to efficiently deploy domain-specific applications on FPGA by transfer learning that adapts pre-trained models to specific domains, replacing standard convolution layers with efficient convolution blocks, and applying layer fusion to enhance hardware design performance. We evaluate TuRF by deploying a pre-trained VGG-16 model for a domain-specific image recognition task onto a Stratix V FPGA. Results show that designs generated by TuRF achieve better performance than prior methods for the original VGG-16 and ResNet-50 models, while for the optimised VGG-16 model TuRF designs are more accurate and easier to process.

关键词： Convolution field programmable gate arrays Standards Hardware Acceleration Task analysis Kernel

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Providing Multi-tenant Services with FPGAs: Case Study on a Key-Value Store 28

Providing Multi-tenant Services with FPGAs: Case Study on a ...

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28th international conference on field programmable logic and applications (FPL)

作者： Istvan, Zsolt Alonso, Gustavo Singla, Ankit Swiss Fed Inst Technol Dept Comp Sci Syst Grp Zurich Switzerland

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

FPGAs can be used to speed up computation and data management tasks in various application domains. In cloud settings, however, high utilization is as important as high performance. In software it is common to co-locate different tenants' workloads on the same servers to increase utilization. Sharing an FPGA is more complex because applications take up physical space on the chip. Even though it is possible to physically partition the FPGA, tenants can have widely different requirements and their needs can also fluctuate over time. In this paper, we take a different approach and provide flexibility to the tenants who are interested in the same type of application but have different workloads and quality of service requirements. We demonstrate our approach of multi-tenant design using a key value store service but the ideas generalize to other network facing services as well. A key challenge of multi-tenancy is to efficiently share the underlying hardware while enforcing strict data and performance isolation between tenants. In this paper we demonstrate that, by following a single-pipeline design principle, it is possible to control each tenant's share of network bandwidth and computational resources even for complex, distributed operations. Furthermore, we show how state-machine based logic on the FPGA can be made tenant-aware without introducing significant context-switching overhead. Finally, our hardware design provides flexibility for changing per-tenant shares, allowing the same circuit to be used by one or multiple tenants without performance loss.

关键词： field programmable gate arrays Pipelines Bandwidth Cloud computing Data structures Switches Resource management

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A Demonstration of FPGA-based You Only Look Once version2 (YOLOv2) 28

A Demonstration of FPGA-based You Only Look Once version2 (Y...

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28th international conference on field programmable logic and applications (FPL)

作者： Nakahara, Hiroki Shimoda, Masayuki Sato, Shimpei Tokyo Inst Technol Tokyo Japan

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

We implement the YOLO (You only look once) object detector on an FPGA, which is faster and has higher accuracy. It is based on the convolutional deep neural network (CNN), and it is a dominant part of both the performance and the area. It is widely used in the embedded systems, such as robotics, autonomous driving, security, and drones, all of which require high-performance and low-power consumption. A frame object detection problem consists of two problems: one is a regression problem to spatially separated bounding boxes, the second is the associated classification of the objects within realtime frame rate. We used the binary (1 bit) precision CNN for feature extraction and the half-precision (16 bit) precision CNN for both classification and localization. We implement a pipelined based architecture for the mixed-precision YOLOv2 on the Xilinx Inc. zcul02 board, which has the Xilinx Inc. Zynq Ultrascale+ MPSoC. the implemented object detector archived 35.71 frames per second (FPS), which is faster than the standard video speed (29.9 FPS). Compared with a CPU and a GPU, an FPGA based accelerator was superior in power performance efficiency. Our method is suitable for the frame object detector for an embedded vision system.

关键词： field programmable gate arrays Computer architecture Graphics processing units Detectors Feature extraction Training Neural networks

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Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point Representation 28

Reconfigurable Acceleration of 3D-CNNs for Human Action Reco...

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28th international conference on field programmable logic and applications (FPL)

作者： Fan, Hongxiang Ng, Ho-Cheung Liu, Shuanglong Que, Zhiqiang Niu, Xinyu Luk, Wayne Imperial Coll London Dept Comp Sch Engn London England

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Human action recognition (HAR) has been widely employed in various applications such as autonomous cars and intelligent video surveillance. Among the algorithms proposed for HAR, the 3D-CNNs algorithm can achieve the best accuracy. However, its algorithmic complexity imposes a substantial overhead over the speed of these networks, which limits their deployment in real-life applications. this paper proposes a novel customizable architecture for 3D-CNNs based on block floating-point (BFP) arithmetic, where the utilization of BFP significantly reduces the bitwidth while eliminating the need to retrain the network. Optimizations such as locality exploration and block alignment with 3D blocking are performed to improve performance and accuracy. An analytical model and tool are developed to predict the optimized parameters for hardware customization based on user constraints such as FPGA resources or accuracy requirement. Experiments show that without retraining, a 15 bit mantissa design using single-precision accumulation on a Xilinx ZC706 device can be 8.2 times faster than an Intel i7-950 processor at 3.07 GHz with only 0.4% accuracy loss.

关键词： three-dimensional displays field programmable gate arrays Convolution Acceleration Two dimensional displays Optimization Hardware

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Demonstration of Object Detection for Event-driven Cameras on FPGAs and GPUs 28

Demonstration of Object Detection for Event-driven Cameras o...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Shimoda, Masayuki Sato, Shimpei Nakahara, Hiroki Tokyo Inst Technol Tokyo Japan

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

We demonstrate an object detection system using a sliding window method for an event-driven camera[3] which outputs a subtracted frame (usually a binary value) when changes are detected in captured images. Fig. 1 shows the overall architecture of the object detector using a sliding window. First, our system extracts the object region candidates by applying a sliding window to the picture output by an event-driven camera. Since the event-driven camera outputs are binary, the sliding window determines whether an object exists or not based on the proportion of white pixels inside the bounding box as shown in Fig. 2. It reduces the number of proposed regions from 1,485 to average 10. the extracted pictures are resized to 40 x 40 size and applied to the ABCNN (All Binarized Convolutional Neural Network[7]), which is a BCNN (Binarized Convolutional Neural Network[4]) in which the first convolutional layer is done in binary form as well. All binarization is found to improve both the area and computation time, while the classification accuracy decreases. If the ABCNN infers the detected object as human, then it draws a box on the proposed region. Since more than one bounding box is commonly drawn against a single detected object, non-maximum suppression is used to reduce the extras to a single box. the proposed system is implemented on an FPGA and a GPU to show the comparison of them.

关键词： Cameras field programmable gate arrays Microsoft Windows Graphics processing units Micromechanical devices Neural networks Object detection

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Design Flow of Accelerating Hybrid Extremely Low Bit-width Neural Network in Embedded FPGA 28

Design Flow of Accelerating Hybrid Extremely Low Bit-width N...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Wang, Junsong Lou, Qiuwen Zhang, Xiaofan Zhu, Chao Lin, Yonghua Chen, Deming IBM Res China Beijing Peoples R China Univ Notre Dame Notre Dame IN 46556 USA Univ Illinois Champaign IL USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Neural network accelerators with low latency and low energy consumption are desirable for edge computing. To create such accelerators, we propose a design flow for accelerating the extremely low bit-width neural network (ELB-NN) in embedded FPGAs with hybrid quantization schemes. this flow covers both network training and FPGA-based network deployment, which facilitates the design space exploration and simplifies the tradeoff between network accuracy and computation efficiency. Using this flow helps hardware designers to deliver a network accelerator in edge devices under strict resource and power constraints. We present the proposed flow by supporting hybrid ELB settings within a neural network. Results show that our design can deliver very high performance peaking at 103 TOPS and classify up to 325.3 image/s/watt while running large-scale neural networks for less than 5W using embedded FPGA. To the best of our knowledge, it is the most energy efficient solution in comparison to GPU or other FPGA implementations reported so far in the literature.

关键词： field programmable gate arrays Neural networks Quantization (signal) Training Hardware Tools Acceleration

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Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs 28

Embracing Diversity: Enhanced DSP Blocks for Low-Precision D...

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28th international conference on field programmable logic and applications (FPL)

作者： Boutros, Andrew Yazdanshenas, Sadegh Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada Vector Inst Toronto ON Canada

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Use of reduced precisions in Deep Learning (DL) inference tasks has recently been shown to significantly improve accelerator performance and greatly reduce both model memory footprint and the required external memory bandwidth. With appropriate network retuning, reduced precision networks can achieve accuracy close or equal to that of full-precision floating-point models. Given the wide spectrum of precisions used in DL inference, FPGAs' ability to create custom bit-width datapaths gives them an advantage over other acceleration platforms in this domain. However, the embedded DSP blocks in the latest Intel and Xilinx FPGAs do not natively support precisions below 18-bit and thus can not efficiently pack low-precision multiplications, leaving the DSP blocks under-utilized. In this work, we present an enhanced DSP block that can efficiently pack 2x as many 9-bit and 4x as many 4-bit multiplications compared to the baseline Arria-10-like DSP block at the cost of 12% block area overhead which leads to only 0.6% total FPGA core area increase. We quantify the performance gains of using this enhanced DSP block in two state-of-the-art convolutional neural network accelerators on three different models: AlexNet, VGG-16, and ResNet-50. On average, the new DSP block enhanced the computational performance of the 8-bit and 4-bit accelerators by 1.32x and 1.6 x and at the same time reduced the utilized chip area by 15% and 30% respectively.

关键词： field programmable gate arrays Compressors Memory management Degradation Computational modeling

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Encoder and Adaptive Decoder for a (15,6,2) DEC-TED BCH Code

Encoder and Adaptive Decoder for a (15,6,2) DEC-TED BCH Code

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IEEE India conference (INDICON)

作者： Pallavi Rao Pranjali Babshet Ramya Arun Babu M S Sunita PES University Bengaluru India

ISBN: (数字)9781728169163

ISBN: (纸本)9781728169170

In this paper, an encoder and decoder for a double-error-correcting and triple-error-detecting (DEC-TED) (15,6,2) Bose-Chaudhuri-Hocquenghem (BCH) code are implemented for error correction in emerging memories. the encoder converts 6-bit data into 15-bit codewords. Emerging memories have fast read/write access times, and are often used in low-power applications. Hence, an adaptive technique is implemented in the decoder, providing lower power consumption and decoding latency compared to the conventional decoder. It detects the number of errors in a codeword, applies a different error correction algorithm for each error type as necessary, and retrieves error-free data. Its dynamic power consumption is further reduced by stabilizing the glitches that propagate to the error correcting blocks. Implementation was performed using the 28 nm Xilinx FPGA part xc7a35tcpg2361. With only 1.11% increase in FPGA resource utilization, the adaptive decoder achieves 64.4% average power reduction, and 35.68% average latency reduction when compared to the conventional decoder.

关键词： Power demand logic gates Encoding Decoding Error correction codes Resource management field programmable gate arrays

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