检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,813 篇 会议
29 篇 期刊文献
5 册 图书

馆藏范围

1,847 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,202 篇 工学
- 1,019 篇 计算机科学与技术...
- 707 篇 软件工程
- 388 篇 电气工程
- 186 篇 电子科学与技术（可...
- 62 篇 信息与通信工程
- 60 篇 控制科学与工程
- 26 篇 机械工程
- 26 篇 仪器科学与技术
- 25 篇 动力工程及工程热...
- 24 篇 建筑学
- 16 篇 土木工程
- 14 篇 生物工程
- 11 篇 核科学与技术
- 10 篇 材料科学与工程（可...
- 9 篇 光学工程
- 8 篇 生物医学工程（可授...
- 8 篇 安全科学与工程
- 6 篇 化学工程与技术
- 6 篇 交通运输工程
146 篇 理学
- 97 篇 数学
- 33 篇 物理学
- 16 篇 生物学
- 14 篇 系统科学
- 10 篇 统计学（可授理学、...
- 6 篇 化学
52 篇 管理学
- 39 篇 管理科学与工程(可...
- 17 篇 工商管理
- 15 篇 图书情报与档案管...
14 篇 法学
- 12 篇 社会学
9 篇 经济学
- 9 篇 应用经济学
8 篇 医学
6 篇 农学
4 篇 军事学
2 篇 教育学

主题

816 篇 field programmab...
670 篇 field programmab...
271 篇 hardware
154 篇 computer archite...
119 篇 logic gates
111 篇 table lookup
94 篇 clocks
83 篇 throughput
78 篇 random access me...
72 篇 routing
71 篇 acceleration
71 篇 software
66 篇 optimization
63 篇 kernel
61 篇 delays
52 篇 registers
52 篇 logic
49 篇 switches
46 篇 algorithm design...
45 篇 computational mo...

机构

15 篇 univ toronto dep...
9 篇 department of co...
9 篇 imperial coll lo...
8 篇 ecole polytech f...
7 篇 univ british col...
7 篇 school of comput...
7 篇 brigham young un...
7 篇 imperial coll lo...
7 篇 tokyo inst techn...
6 篇 univ tsukuba tsu...
6 篇 university of ch...
6 篇 department of el...
6 篇 univ warwick sch...
6 篇 xilinx inc san j...
5 篇 univ manchester ...
5 篇 department of el...
5 篇 univ toronto dep...
5 篇 swiss fed inst t...
5 篇 xilinx inc 2100 ...
5 篇 altera corp san ...

作者

33 篇 luk wayne
21 篇 maruyama tsutomu
16 篇 wayne luk
16 篇 koch dirk
12 篇 wilton steven j....
12 篇 betz vaughn
12 篇 ienne paolo
11 篇 fahmy suhaib a.
11 篇 cheung peter y. ...
10 篇 vaughn betz
9 篇 constantinides g...
8 篇 suhaib a. fahmy
8 篇 prasanna viktor ...
8 篇 chow paul
8 篇 glesner manfred
8 篇 amano hideharu
8 篇 akash kumar
7 篇 kapre nachiket
7 篇 alonso gustavo
7 篇 hutchings brad

语言

1,838 篇 英文
9 篇 其他

检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1847 条记录，以下是331-340 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Fast and Accurate Trajectory Tracking for Unmanned Aerial Vehicles based on Deep Reinforcement Learning

Fast and Accurate Trajectory Tracking for Unmanned Aerial Ve...

引用

IEEE international conference on Embedded and Real-Time Computing Systems and applications (RTCSA)

作者： Yilan Li Hongjia Li Zhe Li Haowen Fang Amit K. Sanyal Yanzhi Wang Qinru Qiu Electrical Engineering & Computer Science Syracuse University Syracuse NY USA Electrical and Computer Engineering Northeastern University Boston MA USA Mechanical and Aerospace Engineering Syracuse University Syracuse NY USA

Continuous trajectory control of fixed-wing unmanned aerial vehicles (UAVs) is complicated when considering hidden dynamics. Due to UAV multi degrees of freedom, tracking methodologies based on conventional control theory, such as Proportional-Integral-Derivative (PID) has limitations in response time and adjustment robustness, while a model based approach that calculates the force and torques based on UAV's current status is complicated and rigid. We present an actor-critic reinforcement learning framework that controls UAV trajectory through a set of desired waypoints. A deep neural network is constructed to learn the optimal tracking policy and reinforcement learning is developed to optimize the resulting tracking scheme. the experimental results show that our proposed approach can achieve 58.14% less position error, 21.77% less system power consumption and 9.23% faster attainment than the baseline. the actor network consists of only linear operations, hence field programmable Gate Arrays (FPGA) based hardware acceleration can easily be designed for energy efficient real-time control.

关键词： field programmable gate arrays Reinforcement learning Neural networks Unmanned aerial vehicles Trajectory Acceleration

来源：评论

学校读者我要写书评

暂无评论

Towards in the field fast pathogens detection using FPGAs 28

Towards in the field fast pathogens detection using FPGAs

引用

28th international conference on field programmable logic and applications (FPL)

作者： Casale-Brunet, S. Schuepbach, T. Guex, N. Iseli, C. Bridge, A. Kuznetsov, D. Sigrist, C. Lemercier, P. Xenarios, I. Bezati, E. Swiss Inst Bioinformat Lausanne Switzerland

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

the rapid detection and identification of infectious pathogens are a critical need for healthcare in both developed and developing countries. there is a need for portable diagnostics and epidemiological surveillance systems that can be deployed in remote field settings for infectious diseases testing, such as pandemic "hotspots" in Africa or southeast Asia. Together with the Vital-IT and Swiss-Prot groups, we developed a fast pathogen detection embedded hardware accelerator (no bigger than 75x50mm) capable of analyzing up to 250Mnt/s of DNA sequence. To deploy this solution, an embedded DNA Next Generation Sequencer (NGS) is used for retrieving the genetic material from patients sample at the point of care (e.g., the Oxford Nanopore Technologies MinION). Successively, the collected DNA sequences are analized in order to detect the presence of known pathogen patterns. Currently, up to 100 different pathogens can be analized at the same time using one single embedded accelerator. Due to the low-power consumption of this hardware accelerator, it is possible to give access to worldwide health organizations and local administrations to a complete real-time embedded and battery powered surveillance solution. Moreover, this solution can greatly scale to big computing clusters, where a larger pathogens number can be analized in parallel, outperforming current state of art computationally expensive solutions.

关键词： pathogens detection FPGA genomics

来源：评论

学校读者我要写书评

暂无评论

A scalable and efficient digital signal processing system for real time biological spike detection 25

A scalable and efficient digital signal processing system fo...

引用

25th IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： Noubir, Safouane Bornat, Yannick Le Gal, Bertrand Univ Bordeaux IMS Lab Bordeaux INP Bordeaux France

ISBN: (纸本)9781538695623

the design of computing systems able to process data from electrophysiology experiments in real-time is required by biological applications where feedback stimulation of cells could depend on their current activities. From algorithm to hardware implementations, these closed loop systems are specific to cell types, culture size and analog acquisition system properties. Consequently, developing digital processing systems for biological experimentation is time consuming and could become a limiting factor for research in neuroscience. Model based methodologies for hardware architecture generation is currently investigated in video and signal processing domains because they drastically reduce the development time of hardware prototypes and improve the design flexibility with low over cost in comparison with handmade designs. In this article, we evaluate the interests and the drawbacks of these model-based methodologies for electrophysiological applications and compare them with previous handmade design.

关键词： Hardware Computer architecture Real-time systems field programmable gate arrays Signal processing Neurons

来源：评论

学校读者我要写书评

暂无评论

Parity Based In-Place FFT Architecture for Continuous Flow applications 25

Parity Based In-Place FFT Architecture for Continuous Flow A...

引用

25th IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： Kitsakis, V. Papatheofanous, E. A. Reisis, D. Lentaris, G. Soudris, D. Univ Athens Dept Phys Elect Lab Panepistimiopolis Phys Bld 45 Athens 15784 Greece Natl Tech Univ Athens Microlab Sch Elect & Comp Engn Athens Greece

ISBN: (纸本)9781538695623

the current paper introduces a continuous flow radix-2 FFT architecture with a conflict free parallel access in place technique. the parity based technique stores the FFT input elements into two memory banks, and keeps each element at its input address through the entire FFT process. Moreover, it results in improved address generation and control circuits compared to hitherto published results. the FPGA implementation and the comparison with FPGA available cores show the advantages of the resulting architecture.

关键词： Indexes Computer architecture field programmable gate arrays Multiplexing Read only memory Shift registers Routing

来源：评论

学校读者我要写书评

暂无评论

Medusa: A Scalable Interconnect for Many-Port DNN Accelerators and Wide DRAM Controller Interfaces 28

Medusa: A Scalable Interconnect for Many-Port DNN Accelerato...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Shen, Yongming Ji, Tianchu Ferdman, Michael Milder, Peter SUNY Stony Brook Stony Brook NY 11794 USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

To cope with the increasing demand and computational intensity of deep neural networks (DNNs), industry and academia have turned to accelerator technologies. In particular, FPGAs have been shown to provide a good balance between performance and energy efficiency for accelerating DNNs. While significant research has focused on how to build efficient layer processors, the computational building blocks of DNN accelerators, relatively little attention has been paid to the on-chip interconnects that sit between the layer processors and the FPGA's DRAM controller. We observe a disparity between DNN accelerator interfaces, which tend to comprise many narrow ports, and FPGA DRAM controller interfaces, which tend to be wide buses. this mismatch causes traditional interconnects to consume significant FPGA resources. To address this problem, we designed Medusa: an optimized FPGA memory interconnect which transposes data in the interconnect fabric, tailoring the interconnect to the needs of DNN layer processors. Compared to a traditional FPGA interconnect, our design can reduce LUT and FF use by 4.7x and 6.0x, and improves frequency by 1.8x.

关键词： Random access memory Bandwidth Data transfer field programmable gate arrays Program processors Buffer storage Multiplexing

来源：评论

学校读者我要写书评

暂无评论

FINN-L: Library Extensions and Design Trade-off Analysis for Variable Precision LSTM Networks on FPGAs 28

FINN-L: Library Extensions and Design Trade-off Analysis for...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Rybalkin, Vladimir Ghaffar, Muhammad Mohsin Wehn, Norbert Pappalardo, Alessandro Gambardella, Giulio Blott, Michaela Univ Kaiserslautern Microelect Syst Design Res Grp Kaiserslautern Germany Xilinx Res Labs Dublin Ireland

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

It is well known that many types of artificial neural networks, including recurrent networks, can achieve a high classification accuracy even with low-precision weights and activations. the reduction in precision generally yields much more efficient hardware implementations in regards to hardware cost, memory requirements, energy, and achievable throughput. In this paper, we present the first systematic exploration of this design space as a function of precision for Bidirectional Long Short-Term Memory (BiLSTM) neural network. Specifically, we include an in-depth investigation of precision vs. accuracy using a fully hardware-aware training flow, where during training quantization of all aspects of the network including weights, input, output and in-memory cell activations are taken into consideration. In addition, hardware resource cost, power consumption and throughput scalability are explored as a function of precision for FPGA-based implementations of BiLSTM, and multiple approaches of parallelizing the hardware. We provide the first open source HLS library extension of FINN [1] for parameterizable hardware architectures of LSTM layers on FPGAs which offers full precision flexibility and allows for parameterizable performance scaling offering different levels of parallelism within the architecture. Based on this library, we present an FPGA-based accelerator for BiLSTM neural network designed for optical character recognition, along with numerous other experimental proof points for a Zynq UltraScale+ XCZU7EV MPSoC within the given design space.

关键词： Computer architecture Hardware Quantization (signal) Training field programmable gate arrays Microprocessors Libraries

来源：评论

学校读者我要写书评

暂无评论

Efficient Pattern Recognition Algorithm Including a Fast Retina Keypoint FPGA Implementation

Efficient Pattern Recognition Algorithm Including a Fast Ret...

引用

international conference on field programmable logic and applications

作者： Lester Kalms Maximilian Hajduk Diana Göhringer Technische Universität Dresden Dresden Germany

the field of computer vision is continuously increasing and becoming more complex and power demanding. Using feature detection and description allows a fast object detection without needing big databases. FPGAs are predestined for different requirements, like real-time and power constraints, which are important in many application areas. this work proposes a new pattern recognition algorithm, based on an improved Accelerated KAZE (AKAZE) detector and Fast Retina Keypoint (FREAK) descriptor. Our software implementation increased the repeatability in comparison to the original algorithm using optimized configurations. the percentage of correct matching features between two images (repeatability) increased from 85.7% to 91.4%, while the computation time decreases from 70.3ms to 24.9ms. Furthermore, we present an efficient FPGA implementation of the FREAK descriptor. the accelerator processes 2048 features at 73.4 frames per second; achieving a repeatability of 90.9%, while being optimized for resource utilization and memory bandwidth consumption. Additionally, we show an efficient Integral Image implementation that processes four image pixels per clock cycle at a high frequency (204 MHz on xc7z020clg484-1) consuming minimum resources.

关键词： field programmable gate arrays Retina Detectors Feature detection Pattern recognition Feature extraction Software algorithms

来源：评论

学校读者我要写书评

暂无评论

A Purely Digital Memristor Emulator based on a Flux-Charge Model 25

A Purely Digital Memristor Emulator based on a Flux-Charge M...

引用

25th IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： Camps, Oscar Al Chawa, Mohamad Moner de Benito, Carol Roca, Miquel Stavrinides, Stavros G. Picos, Rodrigo Chua, Leon O. Univ Balearic Isl Dept Phys Palma De Mallorca Spain Int Hellen Univ Sch Sci & Technol Thessaloniki Greece Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

ISBN: (纸本)9781538695623

In this work we present a memristor emulator that allows implementation in a purely digital environment. the emulator is based on a flux-charge description of the memristor, as proposed in the literature. It has been implemented in a commercial FPGA, and it has been shown that its behaviour mimics that of a circuit using memristors. Specifically, we show that it reproduces the fingerprints of a memristor, both in frequency and memory capability. In addition, we also reproduce an IMPLY gate, showing that the behaviour is correctly reproduced.

关键词： Memristors logic gates Resistance Mathematical model field programmable gate arrays High frequency Integrated circuit modeling

来源：评论

学校读者我要写书评

暂无评论

Mitigating DDoS Flooding Attacks against IoT using Custom Hardware Modules 6

Mitigating DDoS Flooding Attacks against IoT using Custom Ha...

引用

6th international conference on Internet of things - Systems, Management and Security (IOTSMS)

作者： Brasilino, Lucas R. B. Swany, Martin Indiana Univ Sch Informat Comp & Engn 700 N Woodlawn Ave Bloomington IN 47408 USA

ISBN: (纸本)9781728129495

the increasing number of deployed Internet of things (IoT) devices is supporting a plethora of new applications that enriches our daily lives. Smart Cities, for instance, leverage IoT to enable new ways of interactions among citizens, government, public services, healthcare, natural resources, waste and energy management. this synergy pushes the participation of individuals and organizations to new levels, strengthening democracy. However, the ubiquity of such devices and their unique characteristics of being numerous, constantly connected to the Internet and having constrained processing capabilities turned IoT into the new target of cyberattacks. Lately, we have witnessed an alarming increase in attack events towards IoT. the most common pattern is usually done in two phases. In the first phase, attackers exploit vulnerabilities in as many devices as possible, turning them into their bots. In the second phase, attackers order bots to dispatch as many request as possible towards a chosen target, flooding them with requests, attempting to exhaust device's computing resources: a Distributed Denial of Service (DDoS) is in place. the traditional targets of massive DDoS attacks are eminent organizations, like financial institutions, governments and online retailers. However, there is space still for small scale DDoS attacks towards IoT devices itself. the main objective would be bringing down IoT devices which firmwares are not easily exploitable, such as security/video surveillance devices. In this paper, we present a study on DDoS flooding attack mitigation where IoT devices are the targets. To that end, we propose a feasible architecture leveraging a CoAP Accelerator to effectively improve device's resilience. the CoAP Accelerator works in cooperation with the device's CPU, having a key role on CoAP message processing. the architecture was prototyped in a System-on-Chip (SoC) field programmable Gate Array (FPGA) and evaluations were carried out demonstrating how devi

关键词： Internet of things IoT FPGA programmable logic Embedded Systems CoAP Security Resilience

来源：评论

学校读者我要写书评

暂无评论

An Effective Architecture for Trace-Driven Emulation of Networks-on-Chip on FPGAs 28

An Effective Architecture for Trace-Driven Emulation of Netw...

引用

28th international conference on field programmable logic and applications (FPL)

作者： thiem Van Chu Kise, Kenji Tokyo Inst Technol Tokyo Japan

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Modern many-core systems use Networks-on-Chip (NoCs) to move data around their cores. As the number of cores increases, the overall performance becomes highly sensitive to the NoC performance. Research and development of NoCs thus play a key role in designing future systems with hundreds to thousands of cores. However, current methodologies for evaluating NoCs are not scalable with respect to the system complexity. Conventional software simulators are too slow for evaluating middle- and largescale NoCs. Recent FPGA-based emulators provide promising emulation speedups over software simulators. However, emulating large-scale NoCs with hundreds to thousands of nodes on FPGAs is a challenging problem because of the FPGA capacity constraints. Moreover, supporting trace-driven emulation is not trivial because trace data must be stored outside of the FPGA (usually in off-chip DRAM). Most of the existing FPGA-based NoC emulators rely on soft processors like Microblaze or hard processors on SoC FPGAs for loading trace data from the off chip memory, generating messages, injecting the messages to the target NoC, manipulating the emulation, and making sure that there is no timing error. this approach makes the implementation easy but drastically degrades the emulation speed. this paper proposes an effective architecture for trace-driven emulation of NoCs on FPGAs. We present methods to scale to large NoCs and effectively hide the off-chip memory access latency. Our evaluation results show that (1) the proposal achieves a speedup of 260 x compared to BookSim, one of the most widely used NoC simulators, when emulating an 8 x 8 NoC with trace data collected from full-system simulation of the PARSEC benchmark suite;and (2) the speedup is increased to three orders of magnitude when emulating a 64 x 64 NoC.

关键词： Emulation field programmable gate arrays Program processors Computer architecture Generators Time division multiplexing Random access memory

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共185页 << < 30 31 32 33 34 35 36 37 38 39 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：