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FPGA-Based Simulated Bifurcation Machine

FPGA-Based Simulated Bifurcation Machine

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international conference on field programmable logic and applications

作者： Kosuke Tatsumura Alexander R. Dixon Hayato Goto Toshiba Corporation

Since many combinatorial optimization problems can be mapped onto ground-state search problems of Ising models, special-purpose machines for Ising problems have attracted intense attention. Simulated bifurcation (SB) is a recently proposed algorithm to solve these Ising problems. One of the remarkable features of SB is the high-degree parallelism underlying in the algorithm, providing an opportunity to solve the Ising problems very fast by massively parallel processing. In this work, we implement the SB algorithm on FPGAs by designing massively parallel custom circuits. We then compare the FPGA-based SB machines with a state-of-the-art machine called a coherent Ising machine (CIM), a highly optimized implementation of simulated annealing (SA), and GPU-based SB machines. SB machines with spin size of 2,048/4,096 (2K/4K) on an Arria10 GX1150 FPGA have 8,192 processing elements for the matrix-vector multiplication (MM) modules (the most computationally intensive part) and achieve computation throughput of 1,873/2,027 GMAC/s for the MM modules, outperforming 2K/4K SB machines on an Nvidia Tesla V100 GPU (113/183 GMAC/s). the 2K FPGA-SB solves all-to-all connected 2000-node MAX-CUT problem 14X (/124X) faster than the CIM (/the highly-optimized SA), with much better energy efficiency (288X better than the CIM).

关键词： Oscillators Bifurcation Parallel processing field programmable gate arrays Optimization Graphics processing units Computational complexity

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FPGA Implementation of Low-Latency Robust Asynchronous Interfaces for GALS Systems 25

FPGA Implementation of Low-Latency Robust Asynchronous Inter...

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25th IEEE international conference on Electronics, Electrical Engineering and Computing (INTERCON)

作者： Curtinhas, Tiago Oliveira, Duarte L. Saotome, Osamu Brandolin, Joao B. ITA Elect Engn Div Sao Jose Dos Campos SP Brazil Fed Inst Educ Sci & Technol Dept Elect Sao Paulo Brazil

ISBN: (纸本)9781538654903

Complex digital systems must necessarily be based on the "System-on-Chip - SoC" concept. A natural implementation of SoC circuit uses global clock, but in DSM technology (Deep-Sub-Micron) global clock signal causes several problems. An interesting style for SoC design that reduces the problems of the global clock is the GALS (Globally Asynchronous, Locally Synchronous) paradigm. Currently, the major drawback in the design of a GALS system, shows to be the asynchronous interface. this paper proposes a novel asynchronous wrapper based on a unique port controller aiming to the point-to-point GALS style and easily generalized to multi-point GALS systems. the proposed asynchronous wrapper allows the communication between modules to be performed in the two-phase handshake protocol, which reduces the latency time when compared to the previous ones, and it is robust with respect to essential hazard. A comparison with seven wrappers found in literature shows that the proposed wrapper leads to an average reduction in latency time of 61.1% and average reduction in area of 58% in the FPGA (field programmable Gated array) platform.

关键词： Asynchronous logic wrapper GALS synthesis logic communication ports

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Hardware Implementation of A Chaotic Pseudo Random Number Generator Based on 3D Chaotic System without Equilibrium 25

Hardware Implementation of A Chaotic Pseudo Random Number Ge...

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25th IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： Jalilian, Maisam Ahmadi, Arash Ahmadi, Majid Eslam Abade E Gharb Branch Young Researchers & Elite Club Kermanshah Iran Univ Windsor ECE Dept Windsor ON Canada

ISBN: (纸本)9781538695623

Deterministic chaotic systems have been studied and developed in various fields of research. Dynamical systems with chaotic dynamics have different applications in communication, security and computation. Chaotic behaviors can be created by even simple nonlinear systems which can be implemented on low-cost hardware platforms. this paper presents a high-speed and low-cost hardware of three-dimensional chaotic flows without equilibrium. the proposed chaotic hardware is able to reproduce the main mechanism and dynamical behavior of the 3D chaotic flows observed in simulation, then a Chaotic Pseudo Random Number Generator is designed based on a 3D chaotic system. the proposed hardware is implemented with low computational overhead on an FPGA board, as a proof of concept. this low-cost chaotic hardware can be utilized in embedded and lightweight systems for a variety of chaotic based digital systems such as digital communication systems, and cryptography systems based on chaos theory for Security and IoT applications.

关键词： Chaotic communication Hardware three-dimensional displays Generators Mathematical model field programmable gate arrays Cryptography

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In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC 28

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FP...

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28th international conference on field programmable logic and applications (FPL)

作者： Nurvitadhi, Eriko Cook, Jeffrey J. Mishra, Asit Marr, Debbie Nealis, Kevin Colangelo, Philip Ling, Andrew Capalija, Davor Aydonat, Utku Dasu, Aravind Shumarayev, Sergey Intel Corp Santa Clara CA 95051 USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

FPGAs or ASICs? FPGAs are extremely flexible while ASICs offer top efficiency. We believe that FPGAs and ASICs are better together, to offer flexibility and efficiency. We propose single-package heterogeneous 2.5D integration of FPGAs and ASICs, using Intel's Embedded Multi-Die Interconnect Bridge (EMIB). Since the ASICs are separate chips from the FPGA, this approach (1) does not change FPGA fabric, allowing re-use of existing ecosystems (FPGA chips, packaging, boards, software), and (2) allows freedom in ASIC design (area/freq/process/etc unconstrained by FPGA fabric). Intel (R) Stratix (R) 10 FPGAs already have EMIBs, enabling single-package integration with other chips, or "tiles". We propose leveraging them to mix-and match any domain-specific ASICs with Stratixl0 FPGAs. In particular, this work focuses on deep learning (DL) domain, which demands efficient tensor (matrix/vector) operations. We propose TensorTile ASICs for Stratixl0 FPGAs to provide ASIC-level tensor performance, while relying on FPGA's flexibility for application-specific operations (e.g., Winograd). Our evaluation shows: (1) a small TensorTile offer much better tensor throughput than a large Stratixl02800 FPGA;(2) FPGAs and TensorTiles mix-and-match provide scalable solutions (e.g., similar to 69 peak INT8 TOPs with 1xTensorTile+sm all Stratixl0-400 FPGA, to 194 peak FP16 TOPs with 6xTensorTiles+large Stratixl0-2800);(3) AlexNet performance (performance/Watt) of Intel's DL FPGA design improved by 4x (3.3x) when enhanced with 2xTensorTiles.

关键词： field programmable gate arrays Tensile stress Fabrics Computer architecture Parallel processing Acceleration

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Study of Circuit Evolution to Repair Design Flaws in FPGA Edge Computing Chips

Study of Circuit Evolution to Repair Design Flaws in FPGA Ed...

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international Microsystems, Packaging, Assembly and Circuits Technology (IMPACT)

作者： Kuo-Chi Chang Kai-Chun Chu Yuh-Chung Lin Hsiao-Chuan Wang Tsui-Lien Hsu Fu-Hsiang Chang Fujian Provincial Key Laboratory of Big Data Mining and Applications Fujian University of Technology Fuzhou China School of Information Science and Engineering Fujian University of Technology Fuzhou China College of Mechanical & Electrical Engineering National Taipei University of Technology Taipei Taiwan North Borneo University College Sabah Malaysia No3 Xueyuan Road University Town Minhou Fuzhou Fujian Province China No. 1 Section 3 Zhongxiao East Road Taipei City Taiwan Lot 47 Block-F Alamesra Permai Plaza 2 Jln Sulaman Kota Kinabalu Sabah Malaysia Fujian University of Technology Fuzhou China Institute of Environmental Engineering National Taiwan University Taipei Taiwan No.1 Section 4 Roosevelt Road Taipei City Taiwan Institute of Construction Engineering and Management National Central University Taoyuan Taiwan No. 300 Zhongda Rd. Zhongli District Taoyuan City Taiwan Shih-Hsin University Taipei Taiwan No. 1 Ln. 17 Sec. 1 Muzha Rd. Wenshan Dist. Taipei City Taiwan

ISBN: (数字)9781728198514

ISBN: (纸本)9781728198521

field programmable logic Gate Array (FPGA) seems to be a semicustom circuit in the field of special application integrated circuits and use in edge computing. In this study, the chip-level reliability design of the system is carried out from the perspective of fault tolerance and fault self-repair. A real-time fault-tolerant self-repair system structure based on SRAM FPGA is proposed, and the design structure is verified on Xilinx Virtex-6 FPGA. It was found that the energy consumption of different modules in this study increased under the fault-tolerant self-repair design, and when the number of carry chains increased, the detection delay and reconstruction time also increased, which is in line with physical phenomena. However, it has been verified by the designer, it is found that the design time of the designer can be greatly reduced by about 50%, which is an important contribution.

关键词： Ions 5G mobile communication Urban areas Radio frequency Legged locomotion field programmable gate arrays three-dimensional displays

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Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs 38

Analytical Placement with 3D Poisson's Equation and ADMM Bas...

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38th IEEE/ACM international conference on Computer-Aided Design (ICCAD)

作者： Chen, Jianli Zhu, Wenxing Yu, Jun He, Lei Chang, Yao-Wen Fudan Univ State Key Lab ASIC & Syst Shanghai Peoples R China Fuzhou Univ Ctr Discrete Math & Theoret Comp Sci Fuzhou Peoples R China Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90024 USA Natl Taiwan Univ Grad Inst Elect Engn Taipei 10617 Taiwan Natl Taiwan Univ Dept Elect Engn Taipei 10617 Taiwan

ISBN: (纸本)9781728123509

As the design complexity keep increasing, the 2.5D FPGA with large logic capacity has become popular in modern circuit applications. A 2.5D FPGA consists of multiple dies connected through super long lines (SLLs) on an interposer, where each die contains heterogeneous logic blocks and ASIC-like clocking architectures to achieve better skew and timing. To address the crucial SLL issue and the special clocking architecture, this paper presents the first analytical placement algorithm for the 2.5D FPGA with the objective of minimizing the numbers of inter-die SLL signals and intra-die clocking violations simultaneously. Using a lifting dimension technique, we first formulate the 2.5D global placement problem as a three-dimensional continuous and differential minimization problem, where the SLL-aware block distribution is modeled by 3D Poisson's equation and directly solved to obtain an analytical solution. then, we further reformulate the minimization problem as a separable optimization problem with linear constraints. Based on the proximal alternating direction method of multipliers (ADMM) optimization method, we efficiently optimize the separable subproblems one by one in an alternating fashion. Finally, clock-aware legalization and detailed placement are applied to legalize and further improve our placement results. Compared with the state-of-the-art work, experimental results show that our algorithm can resolve all clocking constraints and reduce the number of SLL crossing signals by 36.9% with similar wirelength in comparable running time.

关键词： field programmable gate arrays (FPGA)

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Hardware Description Language Phase-Locked Loop (HDL-PLL) Open Architecture for FPGAs

Hardware Description Language Phase-Locked Loop (HDL-PLL) Op...

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IEEE Nuclear Science Symposium and Medical Imaging conference (NSS/MIC) / 25th international Symposium on Room-Temperature Semiconductor X-Ray and Gamma-Ray Detectors

作者： Lusardi, N. Garzetti, F. Gatti, L. Geraci, A. Politecn Milan Dept Elect Informat & Bioengn DEIB Via Golgi 40 I-20133 Milan MI Italy

ISBN: (纸本)9781538684948

this contribution aims to be a proof of the feasibility of a fully open architecture in Hardware Description Language of a Phase-Locked Loop (HDL-PLL) implemented in field programmable Gate Array (FPGA). Main parts of the system are the Phase-Frequency Detector (PFD) based on a Time-to-Digital Converter (TDC) and the Digital-Controlled Oscillator (DCO). Both of them are implemented by means of asynchronous architectures making possible to tune the DCO output period, by means of a feedback loop, with resolution of 78 ps and cycle-cycle jitter below 75.3 ps r.m.s. the dynamic range of the HDL-PLL is set by the user during the implementation and varies from several hundreds of MHz with no practical lower limit.

关键词： field programmable gate arrays Phase locked loops Hardware design languages Phase frequency detector Jitter logic gates Detectors

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Parallel Robust Absolute Orientation on FPGA for Vision and Robotics 25

Parallel Robust Absolute Orientation on FPGA for Vision and ...

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25th IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： Dimou, Nikolaos Lourakis, Manolis Lentaris, George Soudris, Dimitrios Reisis, Dionysios Fdn Res & Technol Hellas Inst Comp Sci GR-70013 Iraklion Greece Natl Tech Univ Athens Dept Elect & Comp Engn GR-15788 Athens Greece Nat Kapodistrian Univ Athens Dept Phys Elect Lab GR-15784 Athens Greece

ISBN: (纸本)9781538695623

the performance of absolute orientation, a computationally intensive process, plays a key role in a plethora of computer vision and robotics applications. this paper focuses on accelerating the execution of a robust algorithm based on Horn's quaternion solution and presents a HW architecture as well as its FPGA implementation. the proposed design approach relies on the specifics of the algorithm to develop each of its architectural parts by using either low-level Hardware Description Language (HDL) or High Level Synthesis (HLS) descriptions, significantly improving both the design and the time required for development. Combining HDL and HLS described parts leads to an architecture design that exploits parallelism, improves HW utilization and enhances the efficiency of calculations by customizing complicated arithmetic operations. Our implementations on Kintex 7 XC7K325T achieve 61x total speedup versus conventional SW on an embedded processor.

关键词： Computer architecture three-dimensional displays Hardware design languages field programmable gate arrays Symmetric matrices Partitioning algorithms Robots

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field programmable Gate Array Hardware Accelerator of Prime Implicants Generation for Single-Output Boolean Functions Minimization

Field Programmable Gate Array Hardware Accelerator of Prime ...

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international conference on Emerging eLearning Technologies and applications (ICETA)

作者： B. Madoš Z. Bilanová E. Chovancová N. Ádám Department of Computers and Informatics Faculty of Electrical Engineering and Informatics Technical University of Košice Košice Slovak

ISBN: (数字)9781728149677

ISBN: (纸本)9781728149684

the paper deals with the problematics of two-level single-output Boolean functions minimization which is important for many fields of science and technology including logic and control systems design, software engineering, artificial intelligence and others. In this work proposed solution, which is aimed to the production of prime implicants for particular Boolean functions, as the first step of Boolean functions minimization, is based on the use of designed hardware accelerator using field programmable Gate Array (FPGA) technology. As the part of this work, input and output binary vectors encoding is proposed along with the combinational logic module, described using VHDL. Module is implemented into Xilinx Kintex-7 FPGA KC705 Evaluation Kit evaluation board. Advantage of proposed hardware accelerator is in extremely small time complexity in comparison to the algorithms which are utilizing classical CPU based solutions. Another advantage is in constant time of prime implicants generation in case of the same number of input variables of Boolean function regardless of ON set cardinality. Disadvantage of the solution is that it is not possible to define don't care set and in space complexity which is rising quickly according to the number of input variables of Boolean function.

关键词： Boolean functions logic gates Hardware Minimization Input variables Encoding field programmable gate arrays

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FPL 2016 - 26th international conference on field-programmable logic and applications

FPL 2016 - 26th International Conference on Field-Programmab...

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26th international conference on field-programmable logic and applications, FPL 2016

ISBN: (纸本)9782839918442

the proceedings contain 98 papers. the topics discussed include: high-speed PCAP configuration scrubbing on Zynq-7000 all programmable SoCs;boosting convergence of timing closure using feature selection in a learning-driven approach;liquid: fast placement prototyping through steepest gradient descent movement;TeSHoP : a temperature sensing based hotspot-driven placement technique for FPGAs;search-based synthesis of approximate circuits implemented into FPGAs;fast hierarchical NPN classification;and hardware acceleration of feature detection and description algorithms on low-power embedded platforms.

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