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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1847 条记录，以下是361-370 订阅

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AutoRARE: An Automated Tool For Generating FPGA-Based Multi-Memory Hardware Accelerators For Compute-Intensive applications 37

AutoRARE: An Automated Tool For Generating FPGA-Based Multi-...

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37th IEEE international Performance Computing and Communications conference (IPCCC)

作者： Jadhav, Shrikant S. Gloster, Clay Doss, Christopher Kim, Youngsoo Naher, Jannatun North Carolina A&T State Univ Dept Elect & Comp Engn Greensboro NC 27401 USA North Carolina A&T State Univ Dept Comp Syst Technol Greensboro NC USA Bradley Univ Dept Elect & Comp Engn Peoria IL 61625 USA

ISBN: (纸本)9781538668085

In this paper, we present AutoRARE, a Java-based automated design tool for generating field programmable Gate Array (FPGA)-based hardware accelerators. AutoRARE automatically generates all VHDL models needed to build/synthesize a processor specifically tailored for each application. the user needs only provide the VHDL description of a special-purpose floating point Arithmetic logic Unit (ALU) or function core. the tool generates the VHDL description for the memory interface, memory controller, host processor interface, and the application specific processor. We also present details of the FPGA-based multi-memory hardware accelerator for accelerating computationally intensive applications, generated using AutoRARE. the multi-memory hardware accelerator is highly pipelined and able to simultaneously read and write multiple floating point values from multiple memories. the multi-memory architecture is the key to providing hardware accelerators that execute 10X-100X faster than typical multi-core processors. the Taylor Series expansion of the sine/cosine function is used as an application to demonstrate the merits of the multi-memory hardware accelerator. In our experiments, we executed the Taylor Series in software and compared execution times with an FPGA-based hardware implementation. Our experiments show that the FPGA-based multi-memory Taylor Series hardware accelerator is 481X faster than software executing the Taylor Series on a typical server.

关键词： Reconfigurable Computing field-programmable Gate Arrays field-programmable Custom Computing Machines High Performance Computing Multi-Memory Architecture Multiple Memory Banks

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Modular Signal Processing Unit for Motion Control applications Based on System-on-Chip with FPGA

Modular Signal Processing Unit for Motion Control Applicatio...

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international conference on Emerging Technologies and Factory Automation (ETFA)

作者： Vlastimil Šetka Ondřej Ježek Rihards Novickis NTIS – New Technologies for the Information Society Research Center University of West Bohemia Pilsen Czech Republic EDI – Institute of Electronics and Computer Science Riga Latvia

Motion control systems with distributed architecture where multiple input/output devices are connected to the upper layer controller by fast digital communication (fieldbus) became an industrial standard. this paper presents design of a modular input/output device which can process signals from multiple sensors, drive multiple actuators and act as a Slave or Master node in EtherCAT fieldbus network. User-defined algorithms can be easily implemented to preprocess input signals, combine multiple signals or close local control loops with extremely high sampling rates which makes the difference to standard off-the-shelf solutions. To meet these requirements and simplify hardware design, our device is based on System-on-Chip with both programmable logic (FPGA) and classic processor (CPU) ARM cores. Data processing including user algorithms can be done entirely in FPGA which provides very low latency and no jitter, and also on CPU for more complex computations with advantage of tight integration between FPGA and CPU. In this paper we provide description of hardware design, system architecture and typical applications.

关键词： field programmable gate arrays Universal Serial Bus Central Processing Unit Hardware Ethernet Random access memory

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System-on-Chip Linux-based Platform for High-Performance Time-to-Digital Conversion

System-on-Chip Linux-based Platform for High-Performance Tim...

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IEEE Nuclear Science Symposium and Medical Imaging conference (NSS/MIC) / 25th international Symposium on Room-Temperature Semiconductor X-Ray and Gamma-Ray Detectors

作者： Corna, N. Garzetti, F. Lusardi, N. Geraci, A. Politecn Milan Dept Elect Informat & Bioengn DEIB Via Golgi 40 I-20133 Milan MI Italy

ISBN: (纸本)9781538684948

this contribution presents a complete hardware, firmware and software platform for high-resolution time measurements. the implementation is into programmable logic and Processing System sections of a Xilinx System-on-Chip, hosted on a custom carrier board together with front-end circuits, communication interfaces (USB, Ethernet) and power resources. the platform is provided with a software for system configuration, management of output measures. the internal Block-Design IP-Core offers several parameters for customization purpose, also allowing a settable trade-off between saving of resources and performance, with time precision ranging from 12 ps r.m.s. to 50 ps r.m.s. and resolution from 1 ps to 100 ps, configurable number of channels (from 2 to 16) and a rate of measurements up to 45 MHz per channel. the area occupation per channel ranges from 256 SLICEs for a resource-saving configuration to 2048 SLICESs for optimizing performance. Additionally, the IP-Core has a very low Cross-Talk (< 3 ps r.m.s.) and temperature drift (286 fs/degrees C in the 0 degrees C - 70 degrees C operating range). the system is modular, permitting the integration of custom user-made software or firmware modules both in the form of spatial and temporal computing algorithms.

关键词： Software Time measurement Temperature measurement Hardware Microprogramming field programmable gate arrays Histograms

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Implementation of high-performance floating point divider using pipeline architecture on FPGA 1

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6th international conference on Frontiers of Intelligent Computing: theory and applications, FICTA-2017

作者： Hanuman, C.R.S. Kamala, J. Department of Electronics and Communication Engineering College of Engineering Guindy Anna University Chennai India

ISBN: (数字)9789811075667

ISBN: (纸本)9789811075650

Data intensive DSP algorithms mostly depend on double precision (DP) floating point arithmetic operations. With advanced FPGA devices, applications need more floating point arithmetic operations to accelerate reconfigurable logic. Important and complex applications heavily depend on the floating point divider (FPD) blocks. this paper illustrates implementation of low-latency dividers based on pipelining, which is operated at 30% faster than existing divider. DPFPD implemented using field programmable gate array (FPGA) outperforms other ULP dividers. Pipelining architecture of FPD increases the throughput and reduces the power considerably. the architecture is validated for standalone as well as integrated application levels. © Springer Nature Singapore Pte Ltd. 2018.

关键词： field programmable gate arrays (FPGA)

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Energy-efficient hardware caching decision using Fuzzy logic in Mobile Edge Computing 6

Energy-efficient hardware caching decision using Fuzzy Logic...

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6th IEEE Int Conf on Future Internet of things and Cloud (W-FiCloud) / 15th Int Conf on Mobile Web and Intelligent Information Systems (MobiWis) / 4th Int Conf on Big Data Innovations and applications (Innovate-Data)

作者： Mehamel, Sarra Slimani, Khaled Bouzefrane, Samia Daoui, Mehammed Univ Mouloud Mammeri LARI Lab Tizi Ouzou Algeria Conservatoire Natl Arts & Metiers CEDRIC Lab Paris France

ISBN: (纸本)9781538678107

To bring data contents and services in close proximity to the mobile user, mobile edge networks are good candidate because they provide cloud computing and caching capabilities at the edge of cellular networks, hence offering proximity that ensures low latency and high bandwidth through the concept of Mobile Edge Computing (MEC) [22]. To supply effective caching services in the highly resource-constrained and dynamically mobile environment, we propose an energy-efficient fuzzy caching technique for edge devices. this technique uses various parameters (such as mobility and requests frequency) to ensure the effectiveness of our proposed mechanism that highlights the challenge of the computational complexity in mobile edge computing. In this paper, our contribution is a novel solution based on a hardware implementation that uses field-programmable Gate Array (FPGA) as an alternative computational architecture that cuts overall energy requirements. Preliminary implementation and evaluation results demonstrate that the proposed solution reduces the energy consumption and the server load of the edge devices by using an FPGA implementation for fuzzy logic caching decision.

关键词： Edge caching mobile edge computing fuzzy logic energy FPGA

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Multiple hash matching units (MHMU): An algorithmic ternary content addressable memory design for field programmable gate arrays 19

Multiple hash matching units (MHMU): An algorithmic ternary ...

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19th IEEE international conference on High Performance Switching and Routing, HPSR 2018

作者： Reviriego, Pedro Pontarelli, Salvatore Ullah, Anees Zahir, Ali Bianchi, Giuseppe ARIES Research Center Universidad Antonio de Nebrija Spain Italy Department of Electrical and Computer Engineering Center of Advanced Studies in Engineering Pakistan Department of Electrical Engineering COMSATs Institute of Information Technology Pakistan University of Rome Tor Vergata Italy

ISBN: (纸本)9781538678015

As applications and user requirements are constantly evolving, there is a need to provide flexible networks that are able to process packets at high speed. One of the basic functions used for packet processing is matching a key formed by some fields of the incoming packet header against a set of stored rules. this is done for example to determine the next hop of a packet or to apply security checks on a firewall. In many cases, the stored rules have do not care bits as that enables a more flexible and compact representation of the rules. therefore, the matching can be done in hardware using Ternary Content Addressable Memories (TCAMs). However, TCAMs pose several problems in many implementations. For example, for ASICs they require much more circuit area and power than standard SRAMs. On the other hand, designs based on programmable logic such as field programmable Gate Arrays (FPGAs) can only use the blocks provided by the FPGA that do not typically include TCAMs. In this last case, a TCAM can be emulated using the FPGA logic resources but with a large cost. To reduce the cost of implementing TCAMs, a number of algorithmic solutions have been proposed and are known as Algorithmic TCAMs or A-TCAMs. Most of those schemes target either software or ASIC implementations. In this paper we present Multiple Hash Matching Units (MHMU) an A-TCAM solution targeted towards FPGA implementations. the proposed scheme exploits the massive parallelism of FPGAs to implement many hash based matching units that use the embedded block RAM memories of the FPGA. the proposed MHMU scheme has been mapped to a Xilinx series 7 FPGA to check its efficiency in terms of resource usage and its scalability. To validate the effectiveness of MHMU, a simple configuration has been tested with Classbench generated sets of rules. the results show that the MHMU is able to consistently accommodate sets with several tens of thousands of rules with large keys. © 2018 IEEE.

关键词： Static random access storage

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Ultra Low-Power Encryption/Decryption Core for Lightweight IoT applications

Ultra Low-Power Encryption/Decryption Core for Lightweight I...

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international Computer Engineering conference (ICENCO)

作者： Ahmed Zaky Eslam Elmitwalli Mostafa Hemeda Yehea Ismail Khaled Salah University of Science and Technology at Zewail City October Gardens Egypt Center of Nanoelectronics and Devices (CND) American University in Cairo Zewail City of Science and Technology Mentor a Siemens Business Egypt

ISBN: (数字)9781728151465

ISBN: (纸本)9781728151472

the fact that security is not the main functionality of an IoT device means that even lesser portion of its computing power is available for security. Security measures implemented in traditional computers such as cryptography, present a challenge from this context when applied in IoT devices. Different algorithms have been presented in the literature that meet IoT requirements and yet maintain the needed security level. Most of the studies have focused on popular algorithms, especially AES finalists. However, more IoT oriented algorithms have been presented to provide better performance in terms of power and capacity, those are known as lightweight cryptographic algorithms. PRESENT as one of the lightweight cryptographic algorithms is the main focus of this study. the algorithm has been implemented using MATLAB, ASIC and FPGA flows. Lowest achievable power consumption is 120.9 μW at throughput of 20.64 Mbps for the ASIC. For the FPGA, best achievable results was for 16 s-box design utilizing a power of 225.95 mW and 352 LUTs.

关键词： field programmable gate arrays Clocks Power demand Cryptography Matlab logic gates

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Implementation and Analysis of Methods for Error Detection and Correction on FPGA

Implementation and Analysis of Methods for Error Detection a...

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15th IFAC/IEEE conference on programmable Devices and Embedded Systems (PDeS)

作者： Dug, M. Krstic, M. Jokic, D. Int Burch Univ Dept Elect & Elect Engn Sarajevo Bosnia & Herceg IHP Technol Pk 25 D-15236 Frankfurt Oder Germany

In this paper, two methods are implemented and analyzed on a field Programable Gate Array (FPGA) board for the design of fault-tolerant pipelined sequential and combinational circuits. Evaluated methods are named Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC). the mentioned methods are based on Error Detection logic (EDC) in the combinational circuit part combined with fault tolerant master-slave flip-flops with fault tolerant memory elements. Additional to the analysis and implementation of the methods, the enhancement to a method is proposed. (C) 2018, IFAC (international Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： Soft errors combinational logic sequential logic TMR FPGA EDPEC FEDC

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Fully FPGA-based and all-reconfigurable TDC for 3D (X, Y, t) Cross Delay-Line detectors

Fully FPGA-based and all-reconfigurable TDC for 3D (X, Y, t)...

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IEEE Nuclear Science Symposium and Medical Imaging conference (NSS/MIC) / 25th international Symposium on Room-Temperature Semiconductor X-Ray and Gamma-Ray Detectors

作者： Garzetti, F. Lusardi, N. Geraci, A. Dobovicnik, E. Cautero, G. Dri, C. Sergo, R. Stebel, L. Politecn Milan Dept Elect Informat & Bioengn DEIB Via Golgi 40 I-20133 Milan MI Italy Univ Trieste DEEI Via Valerio 10 I-34100 Trieste Italy Elettra Sincrotrone Trieste SS 14 Km 1635 AREA Sci Pk I-34149 Trieste Italy

ISBN: (纸本)9781538684948

Time-resolved experiments often need detection devices able to provide information about position and arrival time of each detected event. Cross Delay-Lines detectors (CDL), which use arrival time information also for position detection, are the most suited instruments for this task and time resolution is a fundamental requirement, along with the high versatility and fast real-time computing. Typical acquisition architectures, based on Time-to-Digital Converters (TDC) followed by a field programmable Gate Array (FPGA), combine very fast parallel computing with a high time precision, allowing to perform state-of-the-art time-resolved experiments. In these devices, time precision as much as time accuracy are fundamental in order to guarantee a homogenous time-to-space conversion. Nevertheless, time resolution is still a limiting factor when time resolved experiments are associated to imaging. In 2017 at Nuclear Science Symposium, inside '' Development of fully FPGA-based 3D (X, Y, t) detection systems using multi-channel Tapped Delay-Line Time-to-Digital Converter with Cross Delay-Line detectors '' we presented a new approach, combining FPGA-based multi-channel TDC and an efficient multipurpose readout logic addressed to CDL detector. In this contribution, thanks to the modularity and reconfigurability offered by the FPGA, we redesigned the firmware that describes the TDC increasing the resolution from 10 ps to 1 ps, the channel precision from 15 ps r.m.s. to 9.7 ps r.m.s. and, reducing the accuracy from 200 ps to 40 ps. As result, we have greatly improved the overall performance and versatility of CDL detector systems allowing image acquisition with spatial precision better than 30 mu m. these make possible the application in a multidisciplinary research center like the Elettra and FERMI lightsources where electron analyzers and Time-of-Flight devices endowed with CDL detectors allow very high spatial and time resolved spectroscopy experiments.

关键词： Detectors field programmable gate arrays Image resolution Time measurement three-dimensional displays Instruments Computer architecture

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Simulation SPI+FLASH system based on FPGA

Simulation SPI+FLASH system based on FPGA

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international conference on Systems and Informatics (ICSAI)

作者： Xiuli Yu Bingqi Li Beijing University of Posts and Telecommunications BUPT Beijing China

ISBN: (数字)9781728152561

ISBN: (纸本)9781728152578

FLASH is called flash memory, also known as high-performance non-volatile memory. It combines the advantages of RAM and ROM which can transfer data quickly and maintain data for a long time in case of power failure. this is why many portable digital devices select flash memory as a storage medium. In recent years, the role of flash memory in the embedded field has become increasingly important. In view of the existing problems of FLASH, including slow erasing, difficult data tracking, complicated operation commands and timing, this paper proposes a method of realizing analog SPI + FLASH system based on FPGA which takes advantage of the parallelism, reconfiguration, high real-time and fast speed. In this paper, the DE10 development board of ALTERA company is used to simulate MX25L3206E chip (SPI+FLASH system) with Verilog Hardware Description Language and finite-state machine on QuartusII development platform. thus, an integrated system platform based on FPGA simulation SPI+FLASH and controller is established, which replaces the function of actual SPI+FLASH. the main work includes decoding operation commands and accurately controlling FLASH work, designing interface timing and control logic, and data transmission with dual-port RAM. then STM32 is used to simulate the host MCU to send data and instructions to the FLASH system simulated by the FPGA through the SPI interface. Finally, the real-time signal is captured and displayed by using the tool software of Signal TapII logic Analyzer to achieve the purpose of the system function test.

关键词： field programmable gate arrays Clocks Random access memory Data communication Flash memories Registers Memory management

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