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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1847 条记录，以下是381-390 订阅

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Application-Specific Soft-Core Vector Processor for Advanced Driver Assistance Systems 27

Application-Specific Soft-Core Vector Processor for Advanced...

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27th international conference on field programmable logic and applications (FPL)

作者： Nolting, Stephan Giesemann, Florian Hartig, Julian Schmider, Achim Paya-Vaya, Guillermo Leibniz Univ Hannover Inst Microelect Syst Appelstr 4 D-30167 Hannover Germany

ISBN: (纸本)9789090304281

Implementing convolutional neural networks for scene labelling is a current hot topic in the field of advanced driver assistance systems. the massive computational demands under hard real-time and energy constraints can only be tackled using specialized architectures. Also, cost-effectiveness is an important factor when targeting lower quantities. In this PhD thesis, a vector processor architecture optimized for FPGA devices is proposed. Amongst other hardware mechanisms, a novel complex operand addressing mode and an intelligent DMA are used to increase perfromance. Also, a C-compiler support for creating applications is introduced.

关键词： field programmable gate arrays Random access memory Computer architecture Vector processors Advanced driver assistance systems Biological neural networks Parallel processing

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In-Network Online Data Analytics with FPGAs 27

In-Network Online Data Analytics with FPGAs

引用

27th international conference on field programmable logic and applications (FPL)

作者： Cooke, Ryan Fahmy, Suhaib A. Univ Warwick Sch Engn Coventry W Midlands England

ISBN: (纸本)9789090304281

the growth of sensor technology, communication systems and computation have led to vast quantities of data being available for relevant parties to utilise. applications such as the monitoring and analysis of industrial equipment, smart surveillance, and fraud detection rely on the ‘real-time’ analysis of time sensitive data gathered from distributed sources. A variety of processing tasks, such as filtering, aggregation, machine learning algorithms, or other transformations to be carried out on this data in order to extract value from it. Centralised computation strategies are often deployed in these scenarios, with the majority of the data being forwarded though the network to a datacenter environment, typically due to the lack of required computational or storage resources at the leaves of the network, and data from other sources or historical data being required. this approach has also traditionally been viewed as more scalable, as resources can be augmented through the addition of extra compute hardware and cloud services.

关键词： field programmable gate arrays Hardware Computational modeling Drones Bandwidth Real-time systems

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Evaluating FPGA Clusters under Wide Ranges of Design Parameters 27

Evaluating FPGA Clusters under Wide Ranges of Design Paramet...

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27th international conference on field programmable logic and applications (FPL)

作者： Zgheib, Grace Ienne, Paolo Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland

ISBN: (纸本)9789090304281

the latest published studies with extensive explorations of look-up table and cluster sizes are now more than a decade old. However, CMOS technology as well as CAD and transistor modeling tools have improved so much since that it is reasonable to wonder whether the conclusions of such studies still hold. One of the major difficulties of conducting these studies, especially in academia, is producing credible delay and area models. In this paper, we take advantage of a recently developed architecture modeling tool to re-evaluate the effect of the various cluster parameters on the FPGA. We considerably extend the exploration space beyond that of the classic studies to include sparse crossbars and fracturable LUTs, and show some results that go against the current tenets of FPGA architecture.

关键词： Solid modeling Table lookup field programmable gate arrays Tools Routing Delays

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Dynamic Bitwidth Assignment for Efficient Dot Products 27

Dynamic Bitwidth Assignment for Efficient Dot Products

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27th international conference on field programmable logic and applications (FPL)

作者： Schmidt, Simon Joel Boland, David Monash Univ Dept Elect & Comp Syst Engn Clayton Vic Australia Univ Sydney Sch Elect & Informat Engn Sydney NSW Australia

ISBN: (纸本)9789090304281

the benefits of customising the precision throughout an FPGA design according to a design tolerance are well known. However, customising the precision of a design at run-time has the potential for an even greater performance impact. In this paper, we add the ability to dynamically choose the internal precision of a datapath. this enables a result that is at least as accurate as the worst-case under standard precisions, whilst internally operating at a lower precision. We demonstrate this technique on fused floating-point dot-product circuits. We show that for circuits with inputs that have a wide dynamic range, we can see substantial resource savings. We provide examples with savings of up to 75% of the DSPs and 16% of the ALMs over an optimised fused dot-product design.

关键词： Multiplexing Random access memory Algorithm design and analysis Adders Clocks field programmable gate arrays Hardware

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An Implementation method of Poisson Image Editing on FPGA 27

An Implementation method of Poisson Image Editing on FPGA

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27th international conference on field programmable logic and applications (FPL)

作者： Maeda, Ryouhei Maruyama, Tsutomu Univ Tsukuba Syst & Informat Engn 1-1-1 Tennodai Tsukuba Ibaraki Japan

ISBN: (纸本)9789090304281

In this paper, we describe an FPGA system for the real-time processing of Poisson image Editing. Poisson Image Editing is a powerful method to overlay an image on another image seamlessly. In this method, however, a simple equation is repeatedly applied to each pixel, and this repetition makes its computational complexity very high. In our system, a very deep pipeline is used to apply the equation. One repetition is executed on each stage of the pipeline, and all repetitions are applied to all pixels during one scan of the image. In our current implementation, to reduce the circuit size, a color image is scanned three times, for R-, G-, and B-plane, but its processing speed is still fast enough for real-time processing of HD images.

关键词： Mathematical model field programmable gate arrays Arrays Pipelines Real-time systems High definition video Image edge detection

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Parallel FPGA Routing: Survey and Challenges 27

Parallel FPGA Routing: Survey and Challenges

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27th international conference on field programmable logic and applications (FPL)

作者： Stojilovic, Mirjana Ecole Polytech Fed Lausanne Sch Comp & Commun Sci Lausanne Switzerland

ISBN: (纸本)9789090304281

As transistor scaling is slowing down [1], other opportunities for ensuring continuous performance increase have to be explored. field programmable gate arrays (FPGAs) are in the spotlight these days: not only due to their malleability and energy efficiency, but also because FPGAs have recently been integrated into the cloud [2]. the latter makes them available to everyone in need of the immense computing power and data throughput they can offer. However, one important issue needs to be resolved first-the time to compile an industrial-scale design for an FPGA must be drastically reduced. Researchers have been looking for ways to accelerate FPGA routing through parallelism, since routing is one of the most time-consuming compilation steps. However, the ideal solution has not been found yet. this paper provides a survey of parallel FPGA routers, with the aim to identify their strengths and weaknesses, thus suggesting directions to take in further efforts for acceleration.

关键词： Routing field programmable gate arrays Program processors Message systems Acceleration Parallel processing Wires

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A Generic High throughput Architecture for Stream Processing 27

A Generic High Throughput Architecture for Stream Processing

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27th international conference on field programmable logic and applications (FPL)

作者： Rousopoulos, Christos Karandeinos, Ektoras Chrysos, Grigorios Dollas, Apostolos Pnevmatikatos, Dionisios N. Tech Univ Crete Sch Elect & Comp Engn Khania 73100 Greece

ISBN: (纸本)9789090304281

Stream join is a fundamental and computationally expensive data mining operation for relating information from different data streams. this paper presents two FPGA-based architectures that accelerate stream join processing. the proposed hardware-based systems were implemented on a multi-FPGA hybrid system with high memory bandwidth. the experimental evaluation shows that our proposed systems can outperform a software-based solution that runs on a high-end, 48-core multiprocessor platform by at least one order of magnitude. In addition, the proposed solutions outperform any other previously proposed hardware-based or software-based solutions for stream join processing. Finally, our proposed hardware-based architectures can be used as generic templates to map stream processing algorithms on reconfigurable logic, taking into consideration real-world challenges and restrictions.

关键词： Computer architecture Hardware throughput Bandwidth field programmable gate arrays Parallel processing

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Making a Case for an ARM Cortex-A9 CPU Interlay Replacing the NEON SIMD Unit 27

Making a Case for an ARM Cortex-A9 CPU Interlay Replacing th...

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27th international conference on field programmable logic and applications (FPL)

作者： Ordaz, Jose Raul Garcia Koch, Dirk Univ Manchester Sch Comp Sci Manchester Lancs England

ISBN: (纸本)9789090304281

As an alternative of adding more and more instructions to CPU cores in order to address a wide range of applications, this paper examines to use a mixed grained CPU interlay fabric to provide reconfigurable instruction set extensions. In detail, we are examining to replace the hardened NEON SIMD unit of an ARM Cortex-A9 with an identical sized FPGA fabric. We show that by applying a set of optimizations, we are able to emulate original applications using NEON instructions at the same hardware cost and at very little performance drop by an interlay. Moreover we are demonstrating examples where special custom instructions running on a CPU-Interlay-hybrid are substantially outperforming the original hardened CPU-NEON-system, hence making a strong case to embed reconfigurability as a beneficial feature in future processors.

关键词： Neon Fabrics field programmable gate arrays Digital signal processing Hardware Computer architecture Program processors

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Line Rate programmable Packet Processing in 100Gb Networks 27

Line Rate Programmable Packet Processing in 100Gb Networks

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27th international conference on field programmable logic and applications (FPL)

作者： Benacek, Pavel Pus, Viktor Korenek, Jan Kekely, Michal CESNET Ale Zikova 4 Prague 16000 6 Czech Republic Netcope Technol Sochorova 3232-34 Brno 61600 Czech Republic

ISBN: (纸本)9789090304281

the P4 language provides a way to describe a custom network packet processing behavior that involves header parsing, matching and assembling modified packets. Such abstraction represents a significant step towards removing the limitation of fixed-function networking devices. Our live demonstration shows a straightforward usage of an algorithm and tool that maps a P4 program to a general architecture of FPGA-based networking device. Network traffic is received, parsed, filtered and modified by the generated circuit at the full line rate of 100 Gbps Ethernet. the results of our ongoing joint research project NFV200 show that the FPGA technology can be used to improve network flexibility without the usual burden of tedious and error-prone HDL coding.

关键词： field programmable gate arrays Protocols Pipeline processing Standards Software Tools Hardware design languages

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Broken-Karatsuba multiplication and its application to Montgomery modular multiplication 27

Broken-Karatsuba multiplication and its application to Montg...

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27th international conference on field programmable logic and applications (FPL)

作者： Ding, Jinnan Li, Shuguo Tsinghua Univ Natl Lab Informat Sci & Technol Inst Microelect Beijing Peoples R China

ISBN: (纸本)9789090304281

Large number multiplication has always been an essential operation in cryptographic algorithms. In this paper, we propose Broken-Karatsuba multiplication by applying the non-least-positive form to represent large numbers and dig the parallelism hidden in conventional Karatsuba multiplication. Further, we modify Montgomery modular multiplication algorithm with Broken-Karatsuba multiplication to make it suitable for pipeline implementation with fewer hardware resources. Based on this modified algorithm, a 256-bit two-stage modular multiplier is constructed. there is no stall in the pipeline when performing consecutive modular multiplications and the delay of a modular multiplication is reduced significantly. Implemented on Virtex-6 FPGA platforms, our design outperforms most previous works in terms of modular multiplication latency and area-time product, which makes it suitable for server-side applications.

关键词： Algorithm design and analysis Digital signal processing Pipelines Table lookup Hardware field programmable gate arrays Clocks

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