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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1846 条记录，以下是31-40 订阅

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An Efficient Clock Gated RSFQ Matrix Multiplier through FPGA Implementation 9

An Efficient Clock Gated RSFQ Matrix Multiplier through FPGA...

引用

9th international conference on Advanced Computing and Communication Systems, ICACCS 2023

作者： Kaarthik, K. Vivek, C. Sivaranjani, S. M. Kumarasamy College of Engineering Karur India Sri Eshwar College of Engineering Coimbatore India

ISBN: (纸本)9798350397376

Multiplier are one of the indispensible component in Arithmetic and logic Unit. Many applications for image and signal processing use matrix multiplication as their core operation. In order to speed up current solutions and adhere to real-time limitations. the proposed system depicts, the field programmable Gate Array features a clock-gated matrix multiplier. the clock-gating approach is used to impact a large number of bit-slicing multipliers in the suggested multiplier. the major goal of this clock-gating technology is to increase performance and decrease power consumption. this suggested multiplier's output bits be restricted to 16 bits. the fundamental gates like XOR,AND, D-flip flops and complete adders are used to create the multiplier that is being given. the multiplier design that is suggested is put into practise using the Altera Quartus II supporting *** CMOS uses two distinct technologies., such as 65nm and 90nm, are taken into consideration when developing the multiplier. Similar to this, the designing methodologies use two separate FPGA devices, Cyclone and Stratix. By testing the metrics such as delay, area and power, the proposed design is assessed. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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Optimization of Correlation Coefficient Calculation for Channel Matrix Characterization on FPGA 25

Optimization of Correlation Coefficient Calculation for Chan...

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25th IEEE international conferences on High Performance Computing and Communications, 9th international conference on Data Science and Systems, 21st IEEE international conference on Smart City and 9th IEEE international conference on Dependability in Sensor, Cloud and Big Data Systems and applications, HPCC/DSS/SmartCity/DependSys 2023

作者： Sibio, Simona Ben Smida, Souheil Ding, Yuan Goussetis, George Institute of Sensors Signals and Systems Heriot-Watt University Edinburgh United Kingdom

ISBN: (纸本)9798350330014

Current and future wireless communication networks need to support the demand for an ever-increasing data rate. Modern wireless communication air-interfaces use various modulation schemes with embedded pilot signals that are used to probe the channel state information (CSI). Since frequency resources are increasingly scarce, it becomes favorable to reduce the bandwidth occupied by the resources allocated to the pilot signals without compromising the system performance. In a MIMO scenario, the knowledge of the correlation coefficients between receiving antennas can help to optimize the transmission reducing the need of additional transmitted data. In this paper, a novel hardware implementation for calculating the correlation coefficient between two unknown signals is presented. the proposed approach aims to maintain a low mean-square error (MSE) with the minimum number of samples. Additionally, hardware optimizations are applied to the design resulting in a valuable reduction of the required digital resources and latency. the measurements, based on Xilinx XC7Z020 FPGA SoC, are compared with the results in a simulation environment to demonstrate its efficacy in the supported 5G NR frequency ranges. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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SMVAR: A Novel RNN Accelerator Based on Non-blocking Data Distribution Structure 25

SMVAR: A Novel RNN Accelerator Based on Non-blocking Data Di...

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作者： Xu, Jinwei Jiang, Jingfei Xu, Shiyao Gao, Lei National University of Defense Technology Science and Technology on Parallel and Distributed Laboratory Hunan Changsha China

ISBN: (纸本)9798350330014

Recurrent neural networks (RNNs) have become common models in the field of artificial intelligence to process temporal sequence task, such as speech recognition, text analysis, natural language processing, etc. To speedup RNNs inference, previous research proposed model sparse pruning techniques. However, the pruning rate of existing sparse pruning algorithms will be affected by pruning granularity and hardware friendliness. In order to approximate nonstructured pruning algorithm, this paper proposes Large Region Balanced Sparse (LRBS) pruning method, which does not limit sub-matrix shape and effectively improves pruning rate. Furthermore, we propose Sparse Matrix Vector Multiplication Accelerator for RNNs (SMVAR), which adopt non-blocking data distribution structure to solve the problem of efficient execution of large region irreg-ular matrix multiplication. To further improve the accelerator performance, SMVAR fine-grained adjusts the pipeline between macro-operations to reduce the idle of compute components. In addition, according to the coarse-grained block characteristics of LRBS algorithm, we develop the coarse-grained parallelism of accelerator with multiply compute units(CUs) structure. Experiments show that the pruning rate of our proposed LRBS is 1.25x-2.5x higher than that of the existing pruning algorithms. Compared with the existing work, the execution efficiency is improved by more than 2.02x-35.9x in the same application scenario. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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High-Performance SET Hardening Technique for Vision-Oriented applications 19

High-Performance SET Hardening Technique for Vision-Oriented...

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19th international conference on Synthesis, Modeling, Analysis and Simulation Methods, and applications to Circuit Design, SMACD 2023

作者： De Sio, Corrado Sterpone, Luca Politecnico di Torino Dipartimento di Automatica e Informatica Turin Italy

ISBN: (纸本)9798350332650

the decreasing feature size of VLSI circuits has led to a rise in Single Event Transients (SETs), making them the dominant cause of errors in modern VLSI devices, especially Flash-based FPGAs. the combinational logic in these devices is particularly vulnerable to SETs, making efficient SET hardening techniques essential. Given the demanding performance requirements for vision-oriented benchmarks, finding an efficient hardening technique that does not exceed area and performance limitations is challenging. this paper presents a SET hardening workflow based on an accurate SET analysis aimed at identifying vulnerable circuit nodes for selectively applying hardening techniques to Microchip RTG4 radiation-hardened Flash-based FPGAs. Results from experiments comparing plain, Global hardening, and proposed selective hardening techniques show the high efficiency of the proposed solution. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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A Testbench for Stereo-Processing Acceleration Based on PYNQ and the StereoPi 12

A Testbench for Stereo-Processing Acceleration Based on PYNQ...

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12th IEEE international conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and applications, IDAACS 2023

作者： Kalomiros, John Vourvoulakis, John Vologiannidis, Stavros International Hellenic University Dpt. of Computers Informatics and Telecommunications Serres62124 Greece

ISBN: (纸本)9798350358056

Stereo processing accelerators are often designed and implemented using field programmable logic. In this paper, a new setup for the implementation and practical testing of hardware stereo-processing solutions is presented. A PYNQ Z1 board featuring a Zynq SoC is combined with a low-cost StereoPi camera. It is shown that the system is versatile, since it can exploit the optimized OpenCV capabilities of the Raspberry Pi Compute Module for image pre-processing and the hardware acceleration capabilities of the programmable logic embedded in the Zynq chip. A series of experiments prove the feasibility of the concept. A state-of-the-art implementation of the SGM stereo algorithm in hardware description language is used in order to prove the feasibility of the design. the system can process depth maps with the nominal refresh rate of 60 fps, using stereo image resolution 640×480 and up to 96 levels of disparity. © 2023 IEEE.

关键词： FPGAs hardware design PYNQ Stereo processing StereoPi

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Hardware Implementation of the Precision Time Base Technique for Digital Sampling Oscilloscopes on FPGA

Hardware Implementation of the Precision Time Base Technique...

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Digital Signal Processing and its applications (DSPA), international conference on

作者： Bilal Moussa Kabalan Chaccour Rachid Bouyekhf Multilane Inc. Research and Development Department Houmal Technology Park Bdadoun Lebanon Dept. of Computer and Communications Engineering TICKET Lab. Antonine University Hadat-Baabda Lebanon Nanomedicine Imagery and Therapeutics (NIT) Lab. UTBM Belfort cedex France

In this paper we investigate implementing a Precision Time Base (PTB) technique to improve measurement jitter performance of digital sampling oscilloscopes (DSO) on a field programmable Gate Array (FPGA). To achieve better measurements, two reference signals are used to correct time-base errors and minimize jitter added by the DSO itself (minimize measurement jitter). We show experimentally that using the aforementioned technique, measurement jitter can be reduced from 1.3 pico-seconds (ps) to 280 femto-seconds (fs) (depending on the data rate and the pattern length) on a high-speed DSO.

关键词： Power demand Measurement uncertainty Oscilloscopes Jitter Parallel processing logic gates Length measurement

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Advancing Digital Design: Integration of 16-Bit Unsigned Divider Capability in Xilinx's Kintex and Virtex FPGA Chips for Enhanced Computational Efficiency 13

Advancing Digital Design: Integration of 16-Bit Unsigned Div...

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13th IEEE international conference on Communication Systems and Network Technologies, CSNT 2024

作者： Shishir, Shrivastava Kaur, Amanpreet Chitkara University Institute of Engineering and Technology Chitkara University Punjab India

ISBN: (纸本)9798350305463

the addition of a 16-bit unsigned divider to Xilinx's Kintex and Virtex FPGA devices improves digital design and computational performance. Developers may divide nonnegative 16-bit integers with the 16-bit unsigned divider for precision numerical operations. Due to their hardware versatility and efficiency, FPGAs may speed complicated algorithms in numerous application industries. Recognizable logic gates and programmable interconnects make FPGAs versatile for digital signal processing, telecommunications, and fast prototyping. Xilinx's Kintex and Virtex series, known for customized designs and outstanding performance, get a 16-bit unsigned divider capability. Engineers may execute complex algorithms faster and more precisely with this innovation, opening up new possibilities in embedded systems, telecommunications, and more. Using HDLs like Verilog and VHDL makes FPGA programming easy, like software. When efficiency and speed are crucial, FPGAs are essential in highperformance computing and real-time processing. Xilinx's Kintex and Virtex FPGA processors' 16-bit unsigned divider integration marks a major FPGA technical milestone. It simplifies calculation and widens digital designs, enabling designers to reach new possibilities. In this development, Xilinx's dedication to cutting-edge solutions shows how FPGAs are becoming essential tools for a wide range of applications. Xilinx, FPGA, 16-bit unsigned division, computational efficiency, digital design, hardware acceleration, and highperformance computing are keywords for this work. © 2024 IEEE.

关键词： field programmable gate arrays (FPGA)

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2023 17th international conference on Engineering of Modern Electric Systems, EMES 2023

2023 17th International Conference on Engineering of Modern ...

引用

17th international conference on Engineering of Modern Electric Systems, EMES 2023

ISBN: (纸本)9798350310634

the proceedings contain 107 papers. the topics discussed include: proposal for a vacuum thermal evaporation deposition monitoring system using fuzzy models and ai elements;image classification of roughness using feed forward artificial neural network;integrated intelligent services accelerator platform;comparative study on the drying of wood chips with different humidities and sizes in a microwave field;considerations in mitigating Kerberos vulnerabilities for active directory;versatile control of an automotive assembly line by using programmable logic controllers;control system of an autonomous object tracking robot;fitting empirical distributions for vessels behavioral analysis and maritime anomaly detection;hydrogen production and use: an overview of its importance in mitigating climate change and its nexus with renewable and power engineering;integrative therapeutic music-based application for Alzheimer’s disease;quantum fingerprint scrambling algorithm based on chaos theory;integral methods for calculating the magnetic field intensity for a cylindrical permanent magnet;and face-tracking mount display for medical and engineering applications.

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Bridging Deep Learning and logic Programming for Explainability through ILP 40

Bridging Deep Learning and Logic Programming for Explainabil...

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40th international conference on logic Programming (ICLP)

作者： Dreossi, Talissa Univ Udine Udine Italy

My research explores integrating deep learning and logic programming to set the basis for a new generation of AI systems. By combining neural networks with Inductive logic Programming (ILP), the goal is to construct systems that make accurate predictions and generate comprehensible rules to validate these predictions. Deep learning models process and analyze complex data, while ILP techniques derive logical rules to prove the network's conclusions. Explainable AI methods, like eXplainable Answer Set Programming (XASP), elucidate the reasoning behind these rules and decisions. the focus is on applying ILP frameworks, specifically ILASP and FastLAS, to enhance explainability in various domains. My test cases span weather prediction, the legal field, and image recognition. In weather forecasting, the system will predict events and provides explanations using FastLAS, with plans to integrate recurrent neural networks in the future. In the legal domain, the research focuses on interpreting vague decisions and assisting legal professionals by encoding Italian legal articles and learning reasoning patterns from Court of Cassation decisions using ILASP. For biological laboratories, we will collaborate with a research group to automate spermatozoa morphology classification for Bull Breeding Soundness Evaluation using YOLO networks and ILP to explain classification outcomes. this hybrid approach aims to bridge the gap between the high performance of deep learning models and the transparency of symbolic reasoning, advancing AI by providing interpretable and trustworthy applications.

关键词： Weather forecasting

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FPGA Implementation of a High Speed Efficient Single Precision Floating Point ALU 5

FPGA Implementation of a High Speed Efficient Single Precisi...

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5th international conference on Control, Communication and Computing, ICCC 2023

作者： Azhar Yaseen, N.J. Adersh, V.R. College of Engineering Department of Electronics and Communication Engineering Trivandrum India

ISBN: (纸本)9798350334128

Modern-day computing processors require efficient floating point processing units that operate with high speed and low power consumption. Floating point computation operations are used in a wide variety of applications across different fields such as Engineering, AI, ML and DSP due to their inconceivable dynamic range and enhanced accuracy. these operations need to be performed quickly, with low power consumption and minimal hardware usage. In this paper, we present an efficient single precision floating point arithmetic logic unit with optimized architectures for addition and subtraction using carry look-ahead adder, multiplication using a modified booth encoder and division using the Goldschmidt algorithm. Our proposed architecture is designed using Verilog HDL and implemented on the Spartan 7 FPGA. the implemented design is compared with an existing ALU architecture and we demonstrate that the proposed ALU is 36% faster and more efficient in terms of power and area. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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