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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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PolyPC: Polymorphic Parallel Computing Framework on Embedded Reconfigurable System 27

PolyPC: Polymorphic Parallel Computing Framework on Embedded...

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27th international conference on field programmable logic and applications (FPL)

作者： Ding, Hongyuan Huang, Miaoqing Univ Arkansas Dept Comp Sci & Comp Engn Fayetteville AR 72701 USA

ISBN: (纸本)9789090304281

With the help of parallelism provided by the fine-grained architecture, hardware accelerators on field programmable Gate Arrays (FPGAs) can significantly improve the performance of many applications. However, designers are typically required to have excellent hardware programming skills and unique optimization techniques to fully explore the potential of FPGA resources. In this work, we propose the PolyPC (Polymorphic Parallel Computing) framework that aims to improve productivity while achieving performance speedup. the PolyPC framework implements a custom hardware platform on which the PolyPC framework extends vendor-provided tools to convert OpenCL-like programs into executables by using high-level synthesis (HLS) tools. the PolyPC framework is evaluated regarding performance, area efficiency, and multitasking. the results show a maximum of 66 folds of speedup over a dual-core ARM processor, and 1,043 folds of speedup over a high-performance MicroBlaze soft processor, with 125 folds of area efficiency. In addition, it delivers a significant improvement in response time to high-priority PolyTasks with the priority-aware scheduling.

关键词： Hardware Kernel Computer architecture field programmable gate arrays Multitasking Parallel processing

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Reliable SEU Monitoring and Recovery using a programmable Configuration Controller 27

Reliable SEU Monitoring and Recovery using a Programmable Co...

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27th international conference on field programmable logic and applications (FPL)

作者： Gong, Lingkan Kroh, Alexander Agiakatsikas, Dimitris Nguyen, Nguyen T. H. Cetin, Ediz Diessel, Oliver UNSW Sydney Sch Comp Sci & Engn Sydney NSW Australia UNSW Sydney Sch Elect Engn & Telecommun Sydney NSW Australia Macquarie Univ Dept Engn N Ryde NSW Australia

ISBN: (纸本)9789090304281

FPGAs are promising candidates for computational tasks in space. However, they are susceptible to radiation-induced errors in their configuration memory. the recovery of configuration errors, either by device scrubbing or by module-based recovery, involves a series of reads and writes to the FPGA's configuration port, and is efficiently performed on-chip by a fast, flexible and reliable reconfiguration controller. In this work, we consider the reliability improvement of the recently proposed programmable Configuration Controller (PCC), a soft reconfiguration controller that has been shown to be both fast and flexible, but whose reliability, particularly in the face of radiation-induced configuration errors, has not until now been studied. To ensure that the PCC itself is reliable, we propose the use of traditional Triple Modular Redundant (TMR) combined with a novel software-based interrupt-driven fault recovery process that leverages hardware-accelerated configuration access. We report on our design space exploration to balance the utilization, error recovery performance, and reliability of the PCC. In extremely harsh radiation environments, the Mean Time to Failure of the PCC is as high as 25 years, compared with 3.5 hours for its non-protected counterpart, and that it takes as little as 27 ms to recover from a configuration memory error affecting the PCC.

关键词： field programmable gate arrays Tunneling magnetoresistance Synchronization Registers Reliability engineering Performance evaluation

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Reconfigurable Acceleration of Genetic Sequence Alignment: A Survey of Two Decades of Efforts 27

Reconfigurable Acceleration of Genetic Sequence Alignment: A...

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27th international conference on field programmable logic and applications (FPL)

作者： Ng, Ho-Cheung Liu, Shuanglong Luk, Wayne Imperial Coll London Dept Comp London England

ISBN: (纸本)9789090304281

Genetic sequence alignment has always been a computational challenge in bioinformatics. Depending on the problem size, software-based aligners can take multiple CPU-days to process the sequence data, creating a bottleneck point in bioinformatic analysis flow. Reconfigurable accelerator can achieve high performance for such computation by providing massive parallelism, but at the expense of programming flexibility and thus has not been commensurately used by practitioners. therefore, this paper aims to provide a thorough survey of the proposed accelerators by giving a qualitative categorization based on their algorithms and speedup. A comprehensive comparison between work is also presented so as to guide selection for biologist, and to provide insight on future research direction for FPGA scientists.

关键词： field programmable gate arrays Acceleration Genetics Databases Software Algorithm design and analysis Bioinformatics

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Rapid Implementation of a Partially Reconfigurable Video System with PYNQ 27

Rapid Implementation of a Partially Reconfigurable Video Sys...

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27th international conference on field programmable logic and applications (FPL)

作者： Hutchings, Brad Wirthlin, Mike Brigham Young Univ Dept Elect & Comp Engn Provo UT 84602 USA

ISBN: (纸本)9789090304281

Undergraduate students rapidly implement a partially-reconfigured, real-time video processor on the Xilinx PYNQ board. the video processor performs various real-time operations including Sobel edge detection, embossing, averaging, an interactive Pong game, etc., using a separate partially-reconfigurable bit-stream for each distinct function. Selection of image-processing functions is accomplished by a Python-based graphical user interface that is accessed via a Jupyter notebook. As users select image-processing functions the appropriate partial bit-stream is automatically downloaded to the FPGA. the resulting system is easily and quickly developed by several undergraduate students over a period of about 10 weeks with very little supervision. All files related to the project are available for download on Github. the productivity benefits provided by PYNQ, including Jupyter-based documentation, tutorials, and executable Python code greatly ease development effort making PYNQ an excellent FPGA platform for education.

关键词： Streaming media Hardware field programmable gate arrays Pipelines Tutorials Documentation Real-time systems

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An FPGA Hardware Implementation Approach for a Phylogenetic Tree Reconstruction Algorithm with Incremental Tree Optimization 27

An FPGA Hardware Implementation Approach for a Phylogenetic ...

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27th international conference on field programmable logic and applications (FPL)

作者： Block, Henry Maruyama, Tsutomu Univ Tsukuba Syst & Informat Engn 1-1-1 Ten Ou Ddai Tsukuba Ibaraki 3058573 Japan

ISBN: (纸本)9789090304281

In this paper, we present an FPGA hardware implementation approach for a phylogenetic tree reconstruction with maximum parsimony algorithm. the algorithm, based on stochastic local search, uses the Indirect Calculation of Tree Lengths and the Incremental Tree Optimization methods. We evaluate and compare our new approach against previous hardware approaches, and against TNT, the fastest available parsimony program. We make this comparison for eight real-world biological datasets. We obtain acceleration rates per tree between 2.60 and 4.68 against a previous approach that does not use incremental optimization;between 2.19 and 4.05 against a previous approach that uses an alternative second-pass optimization;and, between 2.66 and 31.94 against TNT. Our approach is not only faster, but it does not use additional memories during the incremental optimization, as it is the case for a software approach.

关键词： Hardware Phylogeny field programmable gate arrays Optimization methods Acceleration DNA

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FPGA Acceleration of Multilevel ORB Feature Extraction for Computer Vision 27

FPGA Acceleration of Multilevel ORB Feature Extraction for C...

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27th international conference on field programmable logic and applications (FPL)

作者： Weberruss, Josh Kleeman, Lindsay Boland, David Drummond, Tom Monash Univ Clayton Vic Australia Univ Sydney Sydney NSW Australia Australian Ctr Excellence Robot Vis Brisbane Qld Australia

ISBN: (纸本)9789090304281

In this paper, we present the first multilevel implementation of the Harris-Stephens corner detector and the ORB feature extractor running on FPGA hardware, for computer vision and robotics applications. ORB is a fundamental component of many robotics applications, and requires significant computation. the design has been validated both in behavioural simulation and in implementation on an Arria V FPGA connected to a desktop PC via PCI-Express. A Linux kernel-mode driver and userspace library allow integration of the acceleration hardware into C++ programs. the device has significantly higher throughput than a CPU implementation (150 MPixel/s vs 27 MPixel/s) and a GPU implementation (40 MPixel/s), with much lower power draw (5.3 W vs 145 W). this throughput is equivalent to 72 fps at 1920 x 1080 or 488 fps at 640 x 480.

关键词： Feature extraction Detectors field programmable gate arrays Hardware Graphics processing units Robots Image resolution

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On Accelerating Pair-HMM Computations in programmable Hardware 27

On Accelerating Pair-HMM Computations in Programmable Hardwa...

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27th international conference on field programmable logic and applications (FPL)

作者： Banerjee, Subho S. el-Hadedy, Mohamed Tan, Ching Y. Kalbarczyk, Zbigniew T. Lumetta, Steve Iyer, Ravishankar K. Univ Illinois Urbana IL 61801 USA

ISBN: (纸本)9789090304281

this paper explores hardware acceleration to significantly improve the runtime of computing the forward algorithm on Pair-HMM models, a crucial step in analyzing mutations in sequenced genomes. We describe 1) the design and evaluation of a novel accelerator architecture that can efficiently process real sequence data without performing wasteful work;and 2) aggressive memoization techniques that can significantly reduce the number of invocations of, and the amount of data transferred to the accelerator. We describe our demonstration of the design on a Xilinx Virtex 7 FPGA in an IBM Power8 system. Our design achieves a 14.85x higher throughput than an 8-core CPU baseline (that uses SIMD and multi-threading) and a 147.49x improvement in throughput per unit of energy expended on the NA12878 sample.

关键词： Coprocessors Reconfigurable architectures Bioinformatics Genomics

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A Programming Model and Runtime System for Approximation-Aware Heterogeneous Computing 27

A Programming Model and Runtime System for Approximation-Awa...

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27th international conference on field programmable logic and applications (FPL)

作者： Parnassos, Ioannis Bellas, Nikolaos Katsaros, Nikolaos Patsiatzis, Nikolaos Gkaras, Athanasios Kanellis, Konstantinos Antonopoulos, Christos D. Spyrou, Michalis Maroudas, Manolis Univ Thessaly Elect & Comp Engn Dept Volos Greece

ISBN: (纸本)9789090304281

Heterogeneous platforms that include diverse architectures such as multicore CPUs, FPGAs and GPUs are becoming very popular due to their superior performance and energy efficiency. Besides heterogeneity, a promising approach for minimizing energy consumption is through approximate computing which relaxes the requirement that all parts of a program are considered equally important to the output quality, thus, all should be executed at full accuracy. Our work extends a traditional OpenMP-like programming model and runtime system to support seamless execution on hybrid architectures with approximation semantics. Starting from a common application code, annotated with our programming model, the programmer can not only target heterogeneous architectures comprising CPU, FPGA and GPU components, but can also regulate the amount of approximation. We evaluate our framework on a number of large-scale applications and demonstrate that the combination of heterogeneous and approximate computing can provide a powerful dynamic interplay between performance and output quality.

关键词： field programmable gate arrays Kernel Runtime Graphics processing units Programming Histograms

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TAIGA: A NEW RISC-V SOFT-PROCESSOR FRAMEWORK ENABLING HIGH PERFORMANCE CPU ARCHITECTURAL FEATURES 27

TAIGA: A NEW RISC-V SOFT-PROCESSOR FRAMEWORK ENABLING HIGH P...

引用

27th international conference on field programmable logic and applications (FPL)

作者： Matthews, Eric Shannon, Lesley Simon Fraser Univ Sch Engn Sci Burnaby BC Canada

ISBN: (纸本)9789090304281

Recently, there has been an increased focus on integration of reconfigurable fabric with modern processors. However, existing soft-processors are optimized to leverage older FPGA fabrics, focus primarily on resource minimization and have fixed-pipeline designs that limit the scope for tightly integrated hardware accelerators. In this work, we present Taiga: a RISC-V, 32-bit, soft-processor architecture supporting the RISC-V Multiply/Divide and Atomic operations extensions (RV32IMA) designed to support Linux-based shared-memory systems. the processor design is highly configurable and features a standardized interface for functional units allowing for ease of integration of new functional units. Despite a more complex pipeline, our design uses approximately 33% fewer slices while clocking 39% faster than a LEON3 based system built on a Xilinx Zynq X7CZ020.

关键词： Program processors field programmable gate arrays Pipelines Rockets Table lookup Fabrics

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Voltage Drop-based Fault Attacks on FPGAs using Valid Bitstreams 27

Voltage Drop-based Fault Attacks on FPGAs using Valid Bitstr...

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27th international conference on field programmable logic and applications (FPL)

作者： Gnad, Dennis R. E. Oboril, Fabian Tahoori, Mehdi B. Karlsruhe Inst Technol Inst Comp Engn Karlsruhe Germany

ISBN: (纸本)9789090304281

Due to the widespread use of FPGAs in many critical application domains, their security is of high concern. In recent systems, such as FPGAs in the Cloud or in Systems-on-Chip (SoCs), users can gain access, even remotely, to the reconfigurable fabric to implement custom accelerators. this access can expose new security vulnerabilities in the entire system through malicious use of the FPGA fabric. In the past, attacks on the power supply level required local access to the hardware. In this paper, we reveal a security vulnerability in FPGAs that allows a valid configuration to generate severe voltage fluctuations, which crashes the FPGA within a few microseconds. Moreover, the extent of this crash is so severe, that manual power-cycling is required to be able to access and use the system again. this vulnerability has been systematically exploited in two different generations of FPGAs, and a SoC containing an FPGA. Because this vulnerability can lead to severe security attacks in systems using FPGA-based accelerators, we also analyze its underlying mechanism, and discuss possibilities for mitigation.

关键词： field programmable gate arrays Security Delays Clocks Latches Fabrics Computer crashes

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