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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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Quantifying and Mitigating the Costs of FPGA Virtualization 27

Quantifying and Mitigating the Costs of FPGA Virtualization

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27th international conference on field programmable logic and applications (FPL)

作者： Yazdanshenas, Sadegh Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9789090304281

FPGAs are being incorporated into contemporary datacenters in order to improve computational capacity, power consumption, and processing latency. Efficiently integrating FPGAs in datacenters is, however, quite challenging. Ideally, smaller tasks could share a device and the cloud management layer would be able to partially reconfigure the device to allocate its free resources to incoming tasks. Moreover, to facilitate FPGA hardware upgrades without undue porting effort for previously developed accelerator tasks, the complexities associated with board-specific system-level integration should be abstracted away from designers. By meeting these requirements, FPGAs in the cloud would become multi-user virtualized resources with increased availability and elasticity. the virtualization of FPGAs, however, comes with two major costs in current FPGAs: lower application operating frequency, and extravagant use of routing resources. In this paper, we quantify the costs of FPGA virtualization and demonstrate that for an FPGA that supports four independent tasks, virtualization reduces the task average frequency by 18% to 46% and increases wire usage to 2.6x. We also investigate the cause of these costs and show that the use of hard NoCs in future datacenter-optimized FPGAs would facilitate FPGA virtualization without sacrificing operating frequency or routing resources.

关键词： field programmable gate arrays Virtualization Routing Bandwidth Cloud computing Random access memory

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Customised Pearlmutter Propagation: A Hardware Architecture for Trust Region Policy Optimisation 27

Customised Pearlmutter Propagation: A Hardware Architecture ...

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27th international conference on field programmable logic and applications (FPL)

作者： Shao, Shengjia Luk, Wayne Imperial Coll London Dept Comp London England

ISBN: (纸本)9789090304281

Reinforcement Learning (RL) is an area of machine learning in which an agent interacts with the environment by making sequential decisions. the agent receives reward from the environment to find an optimal policy that maximises the reward. Trust Region Policy Optimisation (TRPO) is a recent policy optimisation algorithm that achieves superior results in various RL benchmarks, but is computationally expensive. this paper proposes Customised Pearlmutter Propagation (CPP), a novel hardware architecture that accelerates TRPO on FPGA. We use the Pearlmutter Algorithm to address the key computational bottleneck of TRPO in a hardware efficient manner, avoiding symbolic differentiation with change of variables. Experimental evaluation using robotic locomotion benchmarks demonstrates that the proposed CPP architecture implemented on Stratix-V FPGA can achieve up to 20 times speed-up against 6-threaded Keras deep learning library with theano backend running on a Core i7-5930K CPU.

关键词： Hardware field programmable gate arrays Optimization Machine learning Computer architecture Benchmark testing Acceleration

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PAAS: A System Level Simulator for Heterogeneous Computing Architectures 27

PAAS: A System Level Simulator for Heterogeneous Computing A...

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27th international conference on field programmable logic and applications (FPL)

作者： Liang, Tingyuan Feng, Liang Sinha, Sharad Zhang, Wei Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Hong Kong Peoples R China Nanyang Technol Univ Sch Comp Sci & Engn Singapore Singapore

ISBN: (纸本)9789090304281

Heterogeneous computing with hardware accelerators is a promising direction to overcome the power and performance walls in traditional computing systems. CPU-accelerator integrated architectures, such as CPU with ASIC or FPGA based accelerators, are able to provide customized processing according to application requirements and are thus particularly attractive to speed up computation-intensive applications. therefore, system level simulation showing the interaction among CPUs, hardware accelerators and memory system precisely is important for performing design space exploration leading to architecture and design optimization. In this work, we present PAAS (Processor Accelerator Architecture Simulator), a system level simulator to enable cycle-accurate full system simulation of CPU-accelerator heterogeneous systems. PAAS can easily support flexible architectural configurations, such as different on-chip interconnection topologies, memory hierarchy, etc. Using PAAS, this paper also presents the analysis of the impact of different architectural configurations on the performance of benchmark applications with different execution characteristics using FPGA based accelerators. Furthermore, as an example showing the research capability of PAAS, this paper proposes and investigates a cache-partitioning scheme for improving the performance of shared-cache based CPU-FPGA systems.

关键词： field programmable gate arrays Registers Hardware Hardware design languages Ports (Computers) Monitoring

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Accelerator-in-Switch: a framework for tightly coupled switching hub and an accelerator with FPGA 27

Accelerator-in-Switch: a framework for tightly coupled switc...

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27th international conference on field programmable logic and applications (FPL)

作者： Tsuruta, Chiharu Kaneda, Takahiro Nishikawa, Naoki Amano, Hideharu Keio Univ Dept Informat & Comp Sci Yokohama Kanagawa Japan

ISBN: (纸本)9789090304281

Accelerator-in-Switch (AiS) is a framework for building an accelerator logic tightly coupled with a switching hub in a single FPGA for high performance computation with heterogeneous environment with CPUs and GPUs. AiS is implemented on a partial reconfigurable region of an FPGA whose permanent region is used for a switching hub. A port of the switching hub is connected to the registers and local memory of AiS directly. AiS has a standard interface for a standard bus (Avalon MM bus, here) to exchange data between on-board DDR SDRAM and the local memory, and various types of accelerators can be implemented just by providing such an interface. the data input and output are performed with the DMA controller inside the switching hub with the shared memory model between host CPUs and GPUs. We implemented two example accelerators: a reduction calculator for a radiation transfer equations solver (RED) and LET generator for N-body simulation (LET) were implemented as the AiS on PEACH3, a switching hub for a PCIe direct interconnection network with Altera's Stratix V. the use of partial reconfiguration makes it possible to switch multiple accelerators without stopping the switching hub. As a result, we reduced the time for place&route of an accelerator by 47% compared to the case of the design combining the accelerator into the switching hub.

关键词： Switches field programmable gate arrays Ports (Computers) SDRAM Calculators IP networks Hardware

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Learning-based Interconnect-aware Dataflow Accelerator Optimization 27

Learning-based Interconnect-aware Dataflow Accelerator Optim...

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27th international conference on field programmable logic and applications (FPL)

作者： Liu, Shuangnan Schafer, Benjamin Carrion Hong Kong Polytech Univ Dept Elect & Informat Engn Kowloon Hong Kong Peoples R China Univ Texas Dallas Dept Elect & Comp Engn 800 W Campbell Rd Richardson TX 78050 USA

ISBN: (纸本)9789090304281

the interconnect is the Achilles heel of FPGAs. It currently dominates the delay and leads to high power consumption. It is thus, imperative to take it into account when designing complex FPGA systems. In this work, we propose a learning-based method for data-flow systems build out of multiple individual components directly connected and find a set of optimal configurations with unique area vs. throughput trade-offs by time-multiplexing their interconnects. these type of configurations are prevalent in FPGA designs where one block streams data to the next one, i.e., jpeg encoders. One uniqueness of this work is that it uses advanced features of state-of-the-art HLS tools that enable automatic pin multiplexing. this feature implies that logic IO ports are time multiplexed automatically, which affects not only the performance of the design, but also the area, and the interconnect complexity, leading to system configurations with unique area vs. performance trade-offs. Pin multiplexing is not feasible at the RT-level where each design has to be manually optimized. Experimental results show that the method is accurate and fast when compared to an exhaustive search as well as other state-of-the-art methods.

关键词： Pins throughput Delays Multiplexing field programmable gate arrays Ports (Computers) Integrated circuit interconnections

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Fast RNS Implementation of Elliptic Curve Point Multiplication in GF(p) with Selected Base Pairs 27

Fast RNS Implementation of Elliptic Curve Point Multiplicati...

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27th international conference on field programmable logic and applications (FPL)

作者： Mo, Yifeng Li, Shuguo Tsinghua Univ Inst Microelect Tsinghua Natl Lab Informat Sci & Technol Beijing Peoples R China

ISBN: (纸本)9789090304281

Implementing elliptic curve point multiplication (ECPM) based on residue number system (RNS) can efficiently use FPGA resources. In this paper, we propose a modular reduction method, where a kind of RNS pair is selected to achieve fast reduction. Our reduction method mainly needs several parallel additions while the reduction unit of previous designs require two multiplications which are computed serially. We also present a novel multiplier-and-accumulator (MAC) with modular reduction unit (MAAU), whose reduction unit employs our fast reduction method, and MAC is based on Karatsuba-Ofman method. Compared with the previous classic designs based on Cox-Rower architecture, our reduction method allows our MAAU to take much larger radix r = 6 6 without increasing the number of the pipeline stages of MAAU while clock frequency keeps relatively high and no more resources are consumed. Taking larger radix leads to reducing the number of modulo, thus reducing the number of the required cycles and accelerating ECPM. Experimental results obtained on FPGA Stratix II show that the point multiplication for any curves of the size 256, 384 and 521 can be accomplished in 0.42, 0.87 and 1.53 ms respectively, which outperform the previous designs.

关键词： Pipelines Computer architecture Clocks Delays Elliptic curves Adders field programmable gate arrays

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Comparison of Hardware and Software Implementations of Selected Lightweight Block Ciphers 27

Comparison of Hardware and Software Implementations of Selec...

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27th international conference on field programmable logic and applications (FPL)

作者： Diehl, William Farahmand, Farnoud Yalla, Panasayya Kaps, Jens-Peter Gaj, Kris George Mason Univ Dept Elect & Comp Engn Fairfax VA 22030 USA

ISBN: (纸本)9789090304281

Lightweight block ciphers are an important topic of research in the context of the Internet of things (IoT). Current cryptographic contests and standardization efforts seek to benchmark lightweight ciphers in both hardware and software. Although there have been several benchmarking studies of both hardware and software implementations of lightweight ciphers, direct comparison of hardware and software implementations is difficult due to differences in metrics, measures of effectiveness, and implementation platforms. In this research, we facilitate this comparison by use of a custom lightweight reconfigurable processor. We implement six ciphers, AES, SIMON, SPECK, PRESENT, LED and TWINE, in hardware using register transfer level (RTL) design, and in software using the custom reconfigurable processor. Both hardware and software implementations are instantiated in identical Xilinx Kintex-7 FPGAs, which enables direct comparison of throughput, area, throughput-to-area (TP/A) ratio, power, and energy. Results show that TWINE and AES have the highest TP/A ratios for hardware and software implementations, respectively, assuming an area target of 300 - 450 LUTs. In terms of direct comparison, software implementations on tailored reconfigurable processers generally use less power - especially where reconfigurable instruction set extensions are permitted. However, custom hardware implementations have higher throughput and energy-efficiency than software implementations on the same platform.

关键词： Cipher cryptography encryption field programmable gate array reconfigurable microcontroller

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OpenSoC System Architect: An Open Toolkit for Building Soft-Cores on FPGAs 27

OpenSoC System Architect: An Open Toolkit for Building Soft-...

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27th international conference on field programmable logic and applications (FPL)

作者： Fatollahi-Fard, Farzad Donofrio, David Shalf, John Leidel, John Wang, Xi Chen, Yong Lawrence Berkeley Natl Lab Berkeley CA 94720 USA Tact Comp Labs Dallas TX USA Texas Tech Univ Lubbock TX 79409 USA

ISBN: (纸本)9789090304281

Given the recent difficulty in continuing the classic CMOS manufacturing density and power scaling curves, also known as Moore's Law and Dennard Scaling, respectively, we find that modern complex system architectures are increasingly relying upon accelerators in order to optimize the placement of specific computational workloads. In addition, large-scale computing infrastructures utilized in HPC, data intensive computing, and cloud computing must rely almost exclusively upon commodity device architectures provided by third-party manufacturers. the end result being a final system architecture that lacks specificity for the target software workload. At the same time, there is a trend in the FPGA space of much larger FPGAs with a lot more resources and hardened IP blocks, making this type of architecture design space exploration much easier. the OpenSoC System Architect infrastructure combines several open source design tools and methodologies into a central infrastructure for designing, developing, and verifying the necessary hardware and software modules required to implement application-specific processors for use in FPGAs. the end result is an infrastructure that permits rapid development and deployment of application-specific accelerators and softcores, including a fully functional software development tool chain.

关键词： field programmable gate arrays Hardware Software Tools Computer architecture Standards Market research

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Area-optimized Montgomery multiplication on IGLOO 2 FPGAs 27

Area-optimized Montgomery multiplication on IGLOO 2 FPGAs

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27th international conference on field programmable logic and applications (FPL)

作者： Massolino, Pedro Maat C. Batina, Lejla Chaves, Ricardo Mentens, Nele Radboud Univ Nijmegen iCIS Digital Secur Grp Nijmegen Netherlands Univ Lisbon INESC ID IST Lisbon Portugal Katholieke Univ Leuven Imec COSIC Leuven Belgium

ISBN: (纸本)9789090304281

this paper presents the first area-optimized Montgomery modular multiplication module on low-power reconfigurable IGLOO((R)) 2 FPGAs, from Microsemi. In order to obtain a good response time with few resources, the FPGA pipelined Math blocks and the embedded memory blocks are fully leveraged. As a result, 256-bit modular multiplications can be done in 2.33 mu s, at a cost of 505 LUT4 cells, 257 Flip Flops, 1 Math block and 1 64x18 RAM block. If more area resources are considered, a modular multiplication can be performed in 1.25 mu s at a cost of 680 LUT4s, 341 Flip Flops, 2 Math blocks and 2 64x18 RAM blocks. this work is the first fundamental step towards area-efficient public-key cryptography on the Microsemi IGLOO((R)) 2 FPGAs.

关键词： field programmable gate arrays Random access memory Algorithm design and analysis Pipelines Table lookup Galois fields Digital signal processing

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Deflection-Routed Butterfly Fat Trees on FPGAs 27

Deflection-Routed Butterfly Fat Trees on FPGAs

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27th international conference on field programmable logic and applications (FPL)

作者： Kapre, Nachiket Univ Waterloo Waterloo ON Canada

ISBN: (纸本)9789090304281

Bufferless, deflection-routed, Butterfly Fat Trees (BFTs) can outperform state-of-the-art FPGAs overlay NoCs such as Hoplite by as much as 2-5 x on throughput and approximate to 5 x on worst-case latency at identical PE counts, and by approximate to 1.5 x on throughput at identical resource costs > 16K LUTs for statistical traffic patterns. In this paper, we show how to modify the tree connectivity and routing function to support deflection routing on the BFT topology. We introduce the idea of localized deflections that trap deflected packets within a single level of a multi-level BFT to avoid the long round-trip penalty traditionally associated with deflection routing. Across a range of statistical traffic patterns, we show a sustained throughput improvement of 2-5 x over for Hoplite for system sizes as large at 512 PEs at above 20% injection rates when using localized deflections. We also show how the configurable bisection bandwidth of the BFT, modeled with the Rent parameter 0the best performing NoC at a desired cost. For instance, our NoC generator can produce simple trees (P=0) for low-cost applications <2K LUTs, mesh-equivalent BFTs (P=0.5) for real-world applications with locality at <10K LUTs, and crossbars (P=1) when cost is not a constraint >64K LUTs. For workloads with locality, we recommend the BFT topology with p = 0.67.

关键词： Switches Routing Topology field programmable gate arrays Bandwidth Table lookup Fats

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