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IP Core of Coprocessor for Multiple-Precision-Arithmetic Computations

IP Core of Coprocessor for Multiple-Precision-Arithmetic Com...

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international conference on Mixed Design of Integrated Circuits and Systems (MIXDES)

作者： Kamil Rudnicki Tomasz P. Stefanski Department of Reconfigurable Systems Brightelligence Inc. Glasgow UK Faculty of Electronics Gdansk University of Technology Gdansk Poland

In this paper, we present an IP core of coprocessor supporting computations requiring integer multiple-precision arithmetic (MPA). Whilst standard 32/64-bit arithmetic is sufficient to solve many computing problems, there are still applications that require higher numerical precision. Hence, the purpose of the developed coprocessor is to support and offload central processing unit (CPU) in such computations. the developed digital circuit of the coprocessor works with integer numbers of precision approaching maximally 32 kbits. Our IP core is developed using the very high speed integrated circuit hardware description language (VHDL) and simulated assuming implementation in field-programmable gate arrays (FPGAs). It exchanges data using three 64-bit data buses whereas a code for execution on the coprocessor is fetched from a dedicated 8-bit bus (all buses in AMBA standard - AXI Stream). An instruction set of the coprocessor currently consists of 7 instructions including multiplication, addition and subtraction. the computations can maximally employ 16 registers of the length 32k bits. Simulation results assuming implementation on Zynq system on chip (SoC) show that computations of the factorial (n!) for n=1000 take 326.4 μsec. Such a design currently requires 7982 look-up tables (LUTs), 10400 flip-flops (FFs), 33 block RAMs (BRAMs) and 28 DSP modules. the processor is aimed to provide scalability allowing one to use the developed IP core not only in scientific computing, but also in embedded systems employing encryption based on MPA.

关键词： Coprocessors IP networks field programmable gate arrays Registers Computational modeling Standards Simulation

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Toward a Pixel-Parallel Architecture for Graph Cuts Inference on FPGA 27

Toward a Pixel-Parallel Architecture for Graph Cuts Inferenc...

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27th international conference on field programmable logic and applications (FPL)

作者： Gao, Tianqi Choi, Jungwook Tsai, Shang-nien Rutenbar, Rob A. Univ Illinois Dept Elect & Comp Engn Champaign IL 61820 USA IBM TJ Waston Res Ctr Yorktown Hts NY USA WorldQuant LLC Old Greenwich CT USA Univ Pittsburgh Dept Comp Sci Pittsburgh PA 15260 USA Univ Pittsburgh Dept Elect & Comp Engn Pittsburgh PA 15260 USA

ISBN: (纸本)9789090304281

the method of Graph Cuts converts a Maximum a Posteriori (MAP) inference problem on a Markov Random field (MRF) into a network flow, which can be solved efficiently. Many computer vision problems can be conveniently cast as an inference task to find most likely labels for pixels. the method is widely used, but computationally burdensome. Prior accelerator attempts have failed to exploit the problem's attractive, maximum available parallelism: push-relabel flow solvers can run in parallel across every pixel. this paper describes the design and implementation of the first pixel-parallel Graph Cuts inference engine. Our prototype implements a 256-pixel tile of an image, implemented as 256 locally-connected pixel processors. A checkerboard scheduling scheme allows for maximum parallelism while avoiding critical data dependencies. A 150MHz implementation on an FPGA can solve a segmentation task in 6 microseconds. We also discuss strategies for extending our prototype to larger "virtual" images that span more than the physical extent of the inference tile. Our model suggests 2-40x speedups compared with previous accelerator experiments. To the best of our knowledge, this is the first fully functional, pixel-parallel accelerator demonstration for Graph Cuts inference.

关键词： Program processors Parallel processing field programmable gate arrays Prototypes Convergence Arrays

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High-Performance Video Content Recognition with Long-term Recurrent Convolutional Network for FPGA 27

High-Performance Video Content Recognition with Long-term Re...

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27th international conference on field programmable logic and applications (FPL)

作者： Zhang, Xiaofan Liu, Xinheng Ramachandran, Anand Zhuge, Chuanhao Tang, Shibin Ouyang, Peng Cheng, Zuofu Rupnow, Kyle Chen, Deming Univ Illinois Dept Elect & Comp Engn 1406 W Green St Urbana IL 61801 USA Tsinghua Univ Inst Microelect Beijing Peoples R China Beihang Univ Sch Elect & Informat Engn Beijing Peoples R China Inspirit IoT Inc Champaign IL USA

ISBN: (纸本)9789090304281

FPGA is a promising candidate for the acceleration of Deep Neural Networks (DNN) with improved latency and energy consumption compared to CPU and GPU-based implementations. DNNs use sequences of layers of regular computation that are well suited for HLS-based design for FPGA. However, optimizing large neural networks under resource constraints is still a key challenge. HLS must manage on-chip computation, buffering resources, and off-chip memory accesses to minimize the total latency. In this paper, we present a design framework for DNNs that uses highly configurable IPs for neural network layers together with a new design space exploration engine for Resource Allocation Management (REALM). We also carry out efficient memory subsystem design and fixed-point weight re-training to further improve our FPGA solution. We demonstrate our design framework on the Longterm Recurrent Convolution Network for video inputs. Our implementation on a Xilinx VC709 board achieves 3.1X speedup compared to an NVIDIA K80 and 4.75X speedup compared to an Intel Xeon with 17.5X lower energy per image.

关键词： IP networks field programmable gate arrays Resource management Optimization Neural networks Mathematical model Quantization (signal)

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Evaluating Irregular Memory Access on OpenCL FPGA Platforms: a Case Study with XSBench 27

Evaluating Irregular Memory Access on OpenCL FPGA Platforms:...

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27th international conference on field programmable logic and applications (FPL)

作者： Luo, Yingyi Wen, Xianshan Yoshii, Kazutomo Ogrenci-Memik, Seda Memik, Gokhan Finkel, Hal Cappello, Franck Northwestern Univ Dept Elect Engn & Comp Sci Evanston IL 60208 USA Argonne Natl Lab Math & Comp Sci Div Argonne IL 60439 USA Argonne Natl Lab Leadership Comp Facil Argonne IL 60439 USA

ISBN: (纸本)9789090304281

FPGAs are becoming an attractive choice as a heterogeneous computing unit for scientific computing because FPGA vendors are adding floating-point-optimized architectures to their product lines. Additionally, high-level synthesis (HLS) tools such as Altera OpenCL SDK are emerging, which could potentially break the FPGA programming wall and provide a streamlined flow for domain experts in scientific computing. On the other hand, providing high performance in the presence of irregular memory access patterns to off-chip memory remains a challenge for the automated synthesis flows. In this paper, we study the performance/energy characteristics of OpenCL-generated FPGA designs on irregular memory access patterns, targeting XSBench, a memory-intensive Monte Carlo simulation code, as a case study. To complete our study, we implement XSBench in OpenCL and study optimization strategies for FPGAs. We observe that our OpenCL implantation of XSBench achieves 50% higher energy efficiency on an Intel Arria10-based FPGA platform than that on an Intel Xeon 8-core CPU while trading off 35% of performance.

关键词： field programmable gate arrays Kernel Optimization Tools Hardware Digital signal processing Memory management

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Flexible FPGA design for FDTD using OpenCL 27

Flexible FPGA design for FDTD using OpenCL

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27th international conference on field programmable logic and applications (FPL)

作者： Kenter, Tobias Foerstner, Jens Plessl, Christian Paderborn Univ Paderborn Ctr Parallel Comp Warburger Str 100 D-33098 Paderborn Germany Paderborn Univ Dept Comp Sci Warburger Str 100 D-33098 Paderborn Germany Paderborn Univ Dept Elect Engn Warburger Str 100 D-33098 Paderborn Germany

ISBN: (纸本)9789090304281

Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures.

关键词： field programmable gate arrays Kernel Time-domain analysis Pipeline processing Finite difference methods Tools Pipelines

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Asynchronous Interface FIFO Design on FPGA for High-throughput NRZ Synchronisation 27

Asynchronous Interface FIFO Design on FPGA for High-throughp...

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27th international conference on field programmable logic and applications (FPL)

作者： Liu, Gengting Garside, James Furber, Steve Plana, Luis A. Koch, Dirk Univ Manchester Sch Comp Sci Manchester M13 9PL Lancs England

ISBN: (纸本)9789090304281

Networks-on-chip (NoCs) have become a new chip design paradigm as the size of transistors continues to shrink. Globally-asynchronous locally-synchronous (GALS) on-chip networks are proposed for solving issues such as large clock tree distribution and signal delay variations. More interestingly, for the GALS networks using m-of-n delay-insensitive interconnect, the asynchronous interconnect not only can be used for on-chip interconnection, but also provides a simple, direct and power-saving solution for off-chip interconnection. this paper presents an asynchronous interface FIFO design to improve throughput over asynchronous inter-chip links using 2-of-7 Non-Return-to-Zero (NRZ) encoding in an existing many-core system. the proposed design is suitable for implementation on commodity FPGAs without using the limited global clock buffer resources, but involves using the FPGA to implement asynchronous circuits. the interface FIFO is constructed from the transition detectors themselves rather than by employing a separate buffer in the more conventional fashion. the proposed solution has been demonstrated in an existing system and is suitable for adaptation to other asynchronous m-of-n NRZ coding protocols for high-throughput communication.

关键词： Detectors Image edge detection field programmable gate arrays Synchronization Optical signal processing Encoding

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FPGA Modeling Techniques for Detecting and Demodulating Multiple Wireless Protocols 27

FPGA Modeling Techniques for Detecting and Demodulating Mult...

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27th international conference on field programmable logic and applications (FPL)

作者： Drozdenko, Benjamin Handagala, Suranga Chowdhury, Kaushik Leeser, Miriam Louisiana Tech Univ Ruston LA 71270 USA Northeastern Univ ECE Dept Boston MA 02115 USA

ISBN: (纸本)9789090304281

In an increasingly interconnected world, the rising number of wireless devices in the Internet of things has caused heavy congestion on particular bandwidths (BWs). Due to spectrum scarcity, the need has arisen for these devices to operate on the same BWs. However, existing wireless devices are inflexible and have no capabilities to coexist with devices using other protocols. In this work, we propose new FPGA-based design techniques to receive multiple protocols on the same computing platform. Our methods incorporate tunable parameters, such as FIR filter length and number of bits per fixed-point word, to explore design tradeoffs regarding clock cycle, resource utilization, power consumption, and detection accuracy. We separate the physical (PHY) layer receive chains into a set of building blocks, including rate transition, pattern detection, and OFDM demodulation. We investigate implementation of the LTE physical downlink shared channel (PDSCH) and 802.11a protocols to test our techniques. LTE is the standard for high-speed wireless communication for mobile phones and data terminals;Wi-Fi uses variants of IEEE 802.11a. To ease the system development process, we develop our models using MathWorks Simulink, which supports auto-generation of HDL code for the non-critical sections and incorporation of handtuned HDL code as part of its black box interface. Our building blocks can be used by the wireless system modeling community to meet the needs of modern evolving wireless standards. In the future, our framework will allow researchers to achieve highperformance transceiver implementations on FPGA fabric for multiple cutting edge protocols.

关键词： Protocols field programmable gate arrays Long Term Evolution Wireless communication OFDM Clocks Demodulation

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In-Switch Approximate Processing: Delayed Tasks Management for MapReduce applications 27

In-Switch Approximate Processing: Delayed Tasks Management f...

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27th international conference on field programmable logic and applications (FPL)

作者： Mitsuzuka, Koya Hayashi, Ami Koibuchi, Michihiro Amano, Hideharu Matsutani, Hiroki Keio Univ Dept ICS Kohoku Ku 3-14-1 Hiyoshi Yokohama Kanagawa Japan Natl Inst Informat Chiyoda Ku 2-1-2 Hitotsubashi Tokyo Japan

ISBN: (纸本)9789090304281

In MapReduce, the parallel processing performance is often limited by only a few compute nodes that delay to complete given tasks. Although various techniques have been invented to handle such stragglers, these techniques mostly impose a burden on master node to monitor the progress of all the compute nodes, resulting in a new bottleneck as the number of compute nodes increases. As an alternative approach, in this paper, we propose to move such straggler management burden from master node to network switch that connects the master and compute nodes, because all the information goes through the switch. More specifically, the proposed network switch monitors output packets from Map tasks to detect stragglers. When detected, the proposed switch generates a response instead of the straggler based on the outputs of the other normal Map tasks, so that Reduce tasks can be started without delay. We introduce some approximate techniques for the proxy computation and response at the switch;thus our switch is called "ApproxSW." We implement ApproxSW on NetFPGA-SUME board that has four 10Gbit Ethernet (10GbE) interfaces and a Virtex-7 FPGA. An experiment shows that the ApproxSW functions do not degrade the original 10GbE switch performance. We also analyze the accuracy of the proxy computation and response for stragglers and show that the proposed approximation based on task similarity achieves the best accuracy.

关键词： Switches Monitoring Delays Pipeline processing Electronic mail

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An Automatic RTL Compiler for High-throughput FPGA Implementation of Diverse Deep Convolutional Neural Networks 27

An Automatic RTL Compiler for High-Throughput FPGA Implement...

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27th international conference on field programmable logic and applications (FPL)

作者： Ma, Yufei Cao, Yu Vrudhula, Sarma Seo, Jae-sun Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85287 USA Arizona State Univ Sch Comp Informat Decis Syst Engn Tempe AZ USA

ISBN: (纸本)9789090304281

Convolutional neural networks (CNNs) are rapidly evolving and being applied to a broad range of applications. Given a specific application, an increasing challenge is to search the appropriate CNN algorithm and efficiently map it to the target hardware. the FPGA-based accelerator has the advantage of reconfigurability and flexibility, and has achieved highperformance and low-power. Without a general compiler to automate the implementation, however, significant efforts and expertise are still required to customize the design for each CNN model. In this work, we present an RTL-level CNN compiler that automatically generates customized FPGA hardware for the inference tasks of various CNNs, in order to enable high-level fast prototyping of CNNs from software to FPGA and still keep the benefits of low-level hardware optimization. First, a generalpurpose library of RTL modules is developed to model different operations at each layer. the implementation of each module is optimized at the RTL level. Given a CNN algorithm, its structure is abstracted to a directed acyclic graph (DAG) and then complied with RTL modules in the library. the integration and dataflow of physical modules are predefined in the top-level system template and reconfigured during compilation. the runtime control of layer-by-layer sequential computation is managed by the proposed execution schedule so that even highly irregular and complex network topology, e.g. ResNet, can be compiled. the proposed methodology is demonstrated with end-to-end FPGA implementations of various CNN algorithms (e.g. NiN, VGG-16, ResNet-50, and ResNet-152) on two standalone Intel FPGAs, Stratix V and Arria 10. the performance and overhead of the automated compilation are evaluated. the compiled FPGA accelerators exhibit superior performance compared to state-ofthe- art automation-based works by >2x for various CNNs.

关键词： field programmable gate arrays (FPGA)

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Kiwi scientific acceleration at large: Incremental compilation and multi-FPGA HLS demo 27

Kiwi scientific acceleration at large: Incremental compilati...

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27th international conference on field programmable logic and applications, FPL 2017

作者： Greaves, David J. University of Cambridge Computer Laboratory United Kingdom

ISBN: (纸本)9789090304281

the Kiwi project revolves around a compiler that converts C#.NET bytecode into Verilog RTL and/or SystemC. An alpha version of the Kiwi toolchain is now open source and a user community is growing. We will demonstrate an incremental approach to large system assembly of HLS and blackbox components, based on an extended IP-XACT intermediate representation. We show how to address multi-FPGA designs with object passing between components, automatic configuration of shared memory maps and automatic assembly of debugging infrastructure. We will also demonstrate the use of the unsafe subset of the C# language for type casting between byte arrays and structures which is a common coding style for network protocol implementations. Unsafe programming is also needed for user-coded memory managers that need to essentially perform address arithmetic, but such procedures can commonly defeat the memory pool disambiguation algorithms in static analysis. © 2017 Ghent University.

关键词： field programmable gate arrays (FPGA)

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