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Local validity for circular proofs in linear logic with fixed points 27

Local validity for circular proofs in linear logic with fixe...

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27th Annual EACSL conference Computer Science logic, CSL 2018

作者： Nollet, Rémi Saurin, Alexis Tasson, Christine IRIF Université Paris Diderot CNRS Paris France IRIF CNRS Université Paris Diderot INRIA Paris France

ISBN: (纸本)9783959770880

Circular (ie. Non-wellfounded but regular) proofs have received increasing interest in recent years with the simultaneous development of their applications and meta-theory: infinitary proof theory is now well-established in several proof-theoretical frameworks such as Martin Löf's inductive predicates, linear logic with fixed points, etc. In the setting of non-wellfounded proofs, a validity criterion is necessary to distinguish, among all infinite derivation trees (aka. Pre-proofs), those which are logically valid proofs. A standard approach is to consider a pre-proof to be valid if every infinite branch is supported by an infinitely progressing thread. the paper focuses on circular proofs for MALL with fixed points. Among all representations of valid circular proofs, a new fragment is described, based on a stronger validity criterion. this new criterion is based on a labelling of formulas and proofs, whose validity is purely local. this allows this fragment to be easily handled, while being expressive enough to still contain all circular embeddings of Baelde's μMALL finite proofs with (co)inductive invariants: in particular deciding validity and computing a certifying labelling can be done efficiently. Moreover the Brotherston-Simpson conjecture holds for this fragment: every labelled representation of a circular proof in the fragment is translated into a standard finitary proof. Finally we explore how to extend these results to a bigger fragment, by relaxing the labelling discipline while retaining (i) the ability to locally certify the validity and (ii) to some extent, the ability to finitize circular proofs. © Rémi Nollet, Alexis Saurin, and Christine Tasson;licensed under Creative Commons License CC-BY.

关键词： Calculations

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Deep Learning Challenges and Solutions with Xilinx FPGAs 17

Deep Learning Challenges and Solutions with Xilinx FPGAs

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IEEE/ACM 36th international conference on Computer-Aided Design (ICCAD)

作者： Delaye, Elliott Sirasao, Ashish Dudha, Chaithanya Das, Sabya Xilinx Inc San Jose CA 95124 USA

ISBN: (纸本)9781538630938

In this paper, we will describe the architectural, software, performance, and implementation challenges and solutions and current research on the use of programmable logic to enable deep learning applications. First a discussion of characteristics of building a deep learning system will described. Next architectural choices will be explained for how a FPGA fabric can efficiently solve deep learning tasks. Finally specific techniques for how DSPs, memories and are used in high performance applications will be described.

关键词： Machine learning field programmable gate arrays Quantization (signal) Arrays Acceleration Training

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SOCAO: Source-to-source OpenCL compiler for intel-altera FPGAS 4

SOCAO: Source-to-source OpenCL compiler for intel-altera FPG...

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international Workshop on FPGAs for Software Programmers, FSP 2017, co-located with international conference on field programmable logic and applications, FPL 2017

作者： Rohde, Johanna Martinez-Peiró, Marcos Gadea-Gironés, Rafael Computer Systems Group Technische Universität Darmstadt Germany Department of Electronic Engineering Universitat Politècnica de València Spain

ISBN: (纸本)9783800744435

this paper describes the SOCAO source-to-source compiler that allows transforming C/C++ code into an OpenCL accelerated program targeting Intel FPGA SDK for OpenCL. this drastically drops the requirements regarding the knowledge of the designers on parallel computing and hardware design, only C/C++ and the user-guide of the SOCAO compiler are now needed. Results show a 54% to 278% increase of speed for two well-known algorithms for cryptographic applications. the detailed description of the compiler, the user-guide and some outcomes of the project are also explained in this work. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： field programmable gate arrays (FPGA)

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AutoRARE: An Automated Tool For Generating FPGA-Based Multi-Memory Hardware Accelerators For Compute-Intensive applications

AutoRARE: An Automated Tool For Generating FPGA-Based Multi-...

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IEEE international Performance Computing and Communications conference

作者： Shrikant S. Jadhav Clay Gloster Christopher Doss Youngsoo Kim Jannatun Naher Dept. of Electrical and Computer Engineering North Carolina A&T State University Greensboro NC Dept. of Computer Systems Technology North Carolina A&T State University Greensboro NC Dept. of Electrical and Computer Engineering Bradley University Peoria IL

ISBN: (纸本)9781538668092;9781538668085

In this paper, we present AutoRARE, a Java-based automated design tool for generating field programmable Gate Array (FPGA)-based hardware accelerators. AutoRARE automatically generates all VHDL models needed to build/synthesize a processor specifically tailored for each application. the user needs only provide the VHDL description of a special-purpose floating point Arithmetic logic Unit (ALU) or function core. the tool generates the VHDL description for the memory interface, memory controller, host processor interface, and the application specific processor. We also present details of the FPGA-based multi-memory hardware accelerator for accelerating computationally intensive applications, generated using AutoRARE. the multi-memory hardware accelerator is highly pipelined and able to simultaneously read and write multiple floating point values from multiple memories. the multi-memory architecture is the key to providing hardware accelerators that execute 10X-100X faster than typical multi-core processors. the Taylor Series expansion of the sine/cosine function is used as an application to demonstrate the merits of the multi-memory hardware accelerator. In our experiments, we executed the Taylor Series in software and compared execution times with an FPGA-based hardware implementation. Our experiments show that the FPGA-based multi-memory Taylor Series hardware accelerator is 481X faster than software executing the Taylor Series on a typical server.

关键词： Reconfigurable computing field-programmable gate arrays field-programmable custom computing machines High performance computing Multi-Memory architecture Multiple memory banks

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DESIGN AND IMPLEMENTATION OF programmable READ ONLY MEMORY USING REVERSIBLE DECODER ON FPGA 4

DESIGN AND IMPLEMENTATION OF PROGRAMMABLE READ ONLY MEMORY U...

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4th international conference on Signal Processing, Communication and Networking (ICSCN)

作者： Naguboina, Gopi Chand Anusudha, K. Pondicherry Univ Dept Elect Engn Pondicherry India

ISBN: (纸本)9781509047406

Reversible logic is the emerging field for research in present era. the aim of this paper is to design and synthesize a programmable Read Only Memory (PROM) using a reversible decoder which is designed using reversible logic with minimum quantum cost. the PROM is a programmable logic device which consists of fixed AND Gates and programmable OR gates array. Fixed AND gates can be termed as a decoder. PROM finds its applications in cell phones, RFID tags, video game consoles, medical devices, computers and other electronic devices. An n input and k output Boolean function f (a1, a2, a3,.., an) (referred as (n, k)) is said to be logically reversible if and only if, the number of inputs are equal to the number of outputs i.e., 'n' equals 'k' and the input pattern uniquely maps the output pattern. the reversible logic must run both forward and backward as well such that the inputs can also be retrieved from outputs. there are many reversible logic gates in literature like NOT gate, Feynman Gate (CNOT gate), Double Feynman Gate, Peres Gate, TR gate, Seynman Gate and many more. Fan-out and Feed-back are not allowed in logical Reversibility. To overcome the Fan out limitation, the signals from required output lines are duplicated to desired lines using additional reversible combinational circuits. Reversible logic owns its applications in various fields which include Quantum Computing, Optical Computing, Nano-technology, Computer Graphics, low power VLSI etc., Reversible logic is gaining its own importance in recent years largely due to its property of low power consumption and low heat dissipation. In this paper, the programmable Read Only Memory (PROM) using reversible decoder which has less heat dissipation and low power consumption is proposed. the designed circuit is analyzed in terms of quantum cost, garbage outputs and number of gates. the Circuit has been designed and simulated using Xilinx software and implemented on FPGA SPARTAN - 3E.

关键词： PROM PLDS Quantum Cost Reversible Gates Garbage Outputs Number of gates

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A Rapid Data Communication Exploration Tool for Hybrid CPU-FPGA Architectures 25

A Rapid Data Communication Exploration Tool for Hybrid CPU-F...

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25th Euromicro international conference on Parallel, Distributed and Network-Based Processing (PDP)

作者： Makni, Mariem Niar, Smail Baklouti, Mouna Zhong, Guanwen Mitra, Tulika Abid, Mohamed Univ Valenciennes LAMIH Valenciennes France Natl Engn Sch Sfax Sfax Tunisia Natl Univ Singapore Singapore Singapore

ISBN: (纸本)9781509060580

Modern System-on-Chip (SoC) designs face many challenges. Choosing the best communication protocol among the different processing nodes is one of the most important design decisions. On-chip communication architectures can have a significant impact on the performance of SoC designs. However, in most of the existing design tools, only the computation cost is accurately estimated. To address this challenge, we present a high-level analytical tool to estimate the data communication cost for hybrid CPU-FPGA architectures. the proposed model allows to estimate, rapidly and accurately, both computation and communication cost of applications containing multiple nested loops. this paper also explores the benefits of applying various optimization pragmas including dataflow and loop pipelining, at the compilation phase. Experimental results show that the proposed model provides accurate data communication estimation for hybrid CPUFPGA architectures.

关键词： Kernel Data communication Estimation Computational modeling Pipeline processing Analytical models field programmable gate arrays

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DESIGN AND IMPLEMENTATION OF PAL AND PLA USING REVERSIBLE logic ON FPGA SPARTAN 3E 4

DESIGN AND IMPLEMENTATION OF PAL AND PLA USING REVERSIBLE LO...

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4th international conference on Signal Processing, Communication and Networking (ICSCN)

作者： Naguboina, Gopi Chand Anusudha, K. Pondicherry Univ Dept Elect Engn Pondicherry India

ISBN: (纸本)9781509047406

Reversible logic is the emerging field for research in present era. the aim of this paper is to design and synthesize a programmable array logic (PAL) and programmable logic array (PLA) using reversible logic with minimum quantum cost. the PAL is a programmable logic device which consists of programmable AND Gates and fixed OR gates array. the PLA is the PLD which contains programmable AND array and programmable OR array. the PLDs are the combinational circuits mainly used to realize Boolean functions on our interest. An n input and k output Boolean function f (a1, a2, a3,.., an) (referred as (n, k)) is said to be logically reversible if and only if, the number of inputs are equal to the number of outputs i.e., 'n' equals 'k' and the input pattern maps uniquely maps the output pattern. the reversible logic must run both forward and backward in such a way that the inputs can also be retrieved from outputs. there are many reversible logic gates in literature like NOT gate, Feynman Gate (CNOT gate), Double Feynman Gate, Peres Gate, TR gate, Seynman Gate and many more. Fan-out and Feed-back are not allowed in logical Reversibility. To overcome the Fan out limitation, the signals from required output lines are duplicated to desired lines using additional reversible combinational circuits. Reversible logic owns its applications in various fields which include Quantum Computing, Optical Computing, Nanotechnology, Computer Graphics, low power VLSI etc., Reversible logic is gaining its own importance in recent years largely due to its property of low power consumption and low heat dissipation. In this paper, the design of PAL and PLA which has less heat dissipation and low power consumption is proposed. the designed circuits are analyzed in terms of quantum cost, garbage outputs and number of gates. the Circuit has been designed and simulated using Xilinx software and implemented on FPGA SPARTAN - 3E.

关键词： PAL PLA PLDS Quantum Cost Reversible Gates Garbage Outputs Number of gates

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Rapid Design of Real-Time Image Fusion on FPGA using HLS and Other Techniques

Rapid Design of Real-Time Image Fusion on FPGA using HLS and...

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ACS/IEEE international conference on Computer Systems and applications

作者： Furkan Aydin H. Fatih Ugurdag Vecdi Emre Levent Aydin Emre Guzel N. Fajar R. Annafianto M. Akif Ozkan Toygar Akgun Cengiz Erbas Dept. of EE and CS Ozyegin University Istanbul Turkey Ozyegin Universitesi Istanbul TR Dept. of CS Friedrich-Alexander University Erlangen-Niirnberg Nuremberg Germany Aselsan Ankara Turkey

During the process of implementing a parameterized hardware IP generator for an image fusion algorithm, we had a chance to test various tools and techniques such as HLS, pipelining, and PCIe logic/software porting, which we developed in a previous design project. Image fusion combines two or more images through a color transformation process. Depending on the application, different fps and/or resolution may be needed. Yet the specifics of the image-processing algorithm may frequently change causing redesign. If the target platform is FPGA, usually rapid yet optimized hardware implementation is required. All these requirements cannot be met only by HLS. Clever approaches in terms of architectural techniques such as unorthodox ways of pipelining, RTL coding, and creative ways of porting interface logic/software allowed us to meet the requirements outlined above. With all these in our arsenal, we were able to get 3 versions of the algorithm (with different fps and/or resolution) running on Cyclone IV and Arria 10 FPGAs in a fairly short amount of time. this paper explains the image fusion algorithm, our hardware architecture as well as our specific flow for rapid implementation of it.

关键词： Image fusion field programmable gate arrays Hardware Pipeline processing Tools Standards Task analysis

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Functional & timing in-hardware verification of FPGA-based designs using unit testing frameworks 27

Functional & timing in-hardware verification of FPGA-based d...

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27th international conference on field programmable logic and applications, FPL 2017

作者： Caba, Julian Rincoon, Fernando Dondo, Julio Daniel Department of Technology and Information Systems University of Castilla-La Mancha Spain

ISBN: (纸本)9789090304281

In this PhD dissertation, we propose a new testing approach for effectively managing hardware development risks, producing hardware designs with enough quality and reliability. Our proposal is based on the combination of high-level modelling and a unit testing framework in order to generate real hardware implementations for validating the designer intent, in order to keep a high cycle-accuracy and a low design effort. Such real hardware implementations are based on FPGAs, whose reconfigurability are key to provide a flexible verification environment, whereas unit testing frameworks have been extended to consider new testing requirements beyond pure functionality, such as timing analysis. Moreover, we provide a hardware library with two different types of components: 1) monitors to check internal variables at run time, keeping the errors to later trace them, and 2) double functions to reduce third-party dependencies. © 2017 Ghent University.

关键词： field programmable gate arrays (FPGA)

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Tectogrammatical Trees and Fuzzy Natural logic in Linguistic Characterization of Dynamic Processes 17

Tectogrammatical Trees and Fuzzy Natural Logic in Linguistic...

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Joint 17th World Congress of international-Fuzzy-Systems-Association / 9th international conference on Soft Computing and Intelligent Systems (IFSA-SCIS)

作者： Novak, Vilem Univ Ostrava Inst Res & Applicat Fuzzy Modeling NSC IT4Innovat 30Dubna 22 Ostrava 70103 1 Czech Republic

ISBN: (纸本)9781509049172

this paper is a contribution to the applications of fuzzy logic in modeling of linguistic semantics. the topic of interest is description of the past course of a dynamical process that is given by data in the form of time series. We suggest to use the well developed technique of linguistic theory, the so called tectogrammatical trees using which linguists represent semantics of sentences. the core of the suggested procedure is construction of the tectogrammatical tree that is then assigned a formula of fuzzy natural logic. As the latter construes semantics of the given sentence, we can construct a model on the basis of the given data. If successful, the initial sentence can be taken as a linguistic characterization of them. In this paper we demonstrate how sentences characterizing the course of the trend of time series can be assigned the formulas of fuzzy natural logic expressing their semantics via tectogrammatical trees.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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