检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,813 篇 会议
29 篇 期刊文献
5 册 图书

馆藏范围

1,847 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,202 篇 工学
- 1,019 篇 计算机科学与技术...
- 707 篇 软件工程
- 388 篇 电气工程
- 186 篇 电子科学与技术（可...
- 62 篇 信息与通信工程
- 60 篇 控制科学与工程
- 26 篇 机械工程
- 26 篇 仪器科学与技术
- 25 篇 动力工程及工程热...
- 24 篇 建筑学
- 16 篇 土木工程
- 14 篇 生物工程
- 11 篇 核科学与技术
- 10 篇 材料科学与工程（可...
- 9 篇 光学工程
- 8 篇 生物医学工程（可授...
- 8 篇 安全科学与工程
- 6 篇 化学工程与技术
- 6 篇 交通运输工程
146 篇 理学
- 97 篇 数学
- 33 篇 物理学
- 16 篇 生物学
- 14 篇 系统科学
- 10 篇 统计学（可授理学、...
- 6 篇 化学
52 篇 管理学
- 39 篇 管理科学与工程(可...
- 17 篇 工商管理
- 15 篇 图书情报与档案管...
14 篇 法学
- 12 篇 社会学
9 篇 经济学
- 9 篇 应用经济学
8 篇 医学
6 篇 农学
4 篇 军事学
2 篇 教育学

主题

816 篇 field programmab...
670 篇 field programmab...
271 篇 hardware
154 篇 computer archite...
119 篇 logic gates
111 篇 table lookup
94 篇 clocks
83 篇 throughput
78 篇 random access me...
72 篇 routing
71 篇 acceleration
71 篇 software
66 篇 optimization
63 篇 kernel
61 篇 delays
52 篇 registers
52 篇 logic
49 篇 switches
46 篇 algorithm design...
45 篇 computational mo...

机构

15 篇 univ toronto dep...
9 篇 department of co...
9 篇 imperial coll lo...
8 篇 ecole polytech f...
7 篇 univ british col...
7 篇 school of comput...
7 篇 brigham young un...
7 篇 imperial coll lo...
7 篇 tokyo inst techn...
6 篇 univ tsukuba tsu...
6 篇 university of ch...
6 篇 department of el...
6 篇 univ warwick sch...
6 篇 xilinx inc san j...
5 篇 univ manchester ...
5 篇 department of el...
5 篇 univ toronto dep...
5 篇 swiss fed inst t...
5 篇 xilinx inc 2100 ...
5 篇 altera corp san ...

作者

33 篇 luk wayne
21 篇 maruyama tsutomu
16 篇 wayne luk
16 篇 koch dirk
12 篇 wilton steven j....
12 篇 betz vaughn
12 篇 ienne paolo
11 篇 fahmy suhaib a.
11 篇 cheung peter y. ...
10 篇 vaughn betz
9 篇 constantinides g...
8 篇 suhaib a. fahmy
8 篇 prasanna viktor ...
8 篇 chow paul
8 篇 glesner manfred
8 篇 amano hideharu
8 篇 akash kumar
7 篇 kapre nachiket
7 篇 alonso gustavo
7 篇 hutchings brad

语言

1,838 篇 英文
9 篇 其他

检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1847 条记录，以下是471-480 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Spatial memory trace prediction 4

Spatial memory trace prediction

引用

international Workshop on FPGAs for Software Programmers, FSP 2017, co-located with international conference on field programmable logic and applications, FPL 2017

作者： Gebara, Nadeen Yassir Ienne, Paolo Fleming, Kermin Intel Corporation HudsonMA United States EPFL Lausanne Switzerland

ISBN: (纸本)9783800744435

Heterogeneous FPGA systems among other spatial architectures are gaining popularity as candidates for accelerating Data Center and HPC applications. As the number of FLOPs supported on FPGAs increases, the rate at which data can be provided to computational units becomes the major bottleneck determining overall system performance. this heightens the importance of having a quick way to observe and understand the memory access patterns of applications on FPGAs prior to investing long periods of time and effort in writing RTL, especially for applications that will not observe any performance improvements due to bandwidth limitations. Furthermore, since the memory subsystem within FPGAs is programmable, a clear visibility of the spatial memory access patterns of applications prior to design implementation can guide FPGA programmers on the best way to configure and use the memory subsystem in an application specific manner while providing an estimate of bandwidth requirements. In this paper, we present a novel approach for obtaining memory traces of workloads targeting FPGA systems to provide insight on the memory access patterns of applications and guide FPGA programmers. Our algorithm displays an average prediction accuracy of 97.45% for read memory accesses when RTL optimization opportunities are fully exploited, and an accuracy of 90.71% for memory write accesses across the investigated benchmarks. By providing a fast and efficient way to obtain spatial memory reference traces of applications, our work not only guides FPGA programmers by providing more insight into the memory profiles of workload regions amenable to FPGA implementations, but also helps leverage the shortage of memory traces available for performing architectural studies and enhancing FPGA memory systems. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Implementation and Optimization of throughput in High Speed Memory Interface Using AXI Protocol

Implementation and Optimization of Throughput in High Speed ...

引用

international conference on Computing and Networking Technology (ICCNT)

作者： C Sarojini Jaisingh thangaraj Dept of Electronics engineering IIT(ISM) Dhanbad India

the current challenge is to meet out the compatibility of data rates between the data processing systems and the memory bandwidth requirements. For a stream oriented data, Double Data Rate Type three (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) memory interface boosts the buffering capability for processing applications. In this paper, We mainly focus on optimizing the throughput of a high speed DDR3 memory interface using the Advanced eXtensible Interface (AXI) protocol containing independent read/write channels. We have designed the user defined logic in the AXI master to command the AXI slave viz., DDR3 memory. the final design is implemented in the Microsemi RTG4 series FPGA and operated at the frequency of 320 MHz. the design is articulated to achieve maximum throughput by designing AXI master without write response states.

关键词： throughput Clocks Protocols field programmable gate arrays Bandwidth IP networks Random access memory

来源：评论

学校读者我要写书评

暂无评论

Accelerating linux bash commands on FPGAS using partial reconfiguration 4

Accelerating linux bash commands on FPGAS using partial reco...

引用

international Workshop on FPGAs for Software Programmers, FSP 2017, co-located with international conference on field programmable logic and applications, FPL 2017

作者： Horta, Edson Shen, Xinzi Pham, Khoa Koch, Dirk School of Computer Science University of Manchester United Kingdom

ISBN: (纸本)9783800744435

the Linux Operating System is used by a wide range of companies, mainly due to its security and stability. the latest FPGA devices, with embedded processors, allow the development of SoCs running this OS. One of the key features of FPGAs is their ability to change the hardware architecture while the system is running. It is possible to reconfigure one or more regions of the FPGA while the remainder continues to work. these partially reconfigurable regions inside the FPGA can be used to implement software functions, accelerating the execution time for the system. this work presents an FPGA system that provides the required interfaces to deploy Linux bash commands mapped directly into partially reconfigurable blocks of the FPGA. these commands can be executed in any order, thanks to a hardware interface, equivalent to the software pipe interface in Linux, implemented on the static region of the FPGA. the methodology presented in this paper allows the hardware implementations of commands that can be directly interfaced to the std_in and std_out inside the FPGA. this integration is executed in a very flexible manner according to the currently called bash command. this approach can be used to improve the performance of Linux applications through the use of hardware accelerated bash commands. Moreover, this approach is providing a template that will make hardware and software integration very easy. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

An IP Core Integration Tool-Flow for Prototyping Software-Defined Radios using Static Dataflow with Access Patterns 16

An IP Core Integration Tool-Flow for Prototyping Software-De...

引用

16th IEEE international conference on field-programmable Technology (ICFPT)

作者： Tsoeunyane, Lekhobola J. Winberg, Simon Inggs, Michael Univ Cape Town Software Defined Radio Grp Dept Elect Engn Cape Town South Africa

ISBN: (纸本)9781538626566

the current design practices for prototyping Software Defined Radio (SDR) applications using reconfigurable FPGA platforms often rely on the reuse of Intellectual Property (IP) processing cores. this design practice usually involves stitching together these IP blocks to formulate a working system. High-level Synthesis (HLS) tools that support IP core integration often do not fully allow for capturing critical application timing constraints nor provide mechanisms to automatically adjust integrating logic to maintain these constraints. Consequently, reusing IP cores tends to involve many manual and time-consuming design tasks, often at a low level of abstraction. Moreover, these tasks may need to be repeated during the development process. To address these problems, we present a new open tool-flow, built upon the Delite compiler infrastructure. Central to our tool-flow is an automated mechanism for interconnecting a selection of IP cores that maintain particular application timing constraints. A crucial part of our approach and the focus of this paper is the way this tool-flow uses a static dataflow with access patterns (SDF-AP) model to efficiently capture precise timing for aspects of the processing chain. We demonstrate the capability of our tool-flow by generating six typical SDR applications in VHDL. We show how slight modifications to a design, which would have previously needed many manual adjustments, can be carried out quickly using this tool-flow. To evaluate our tool-flow, we compare performance and area results of our tool-generated SDR designs with equivalent hand-coded designs. We found that the generated solutions closely match the results obtained from our hand-coded designs, showing merit for our approach. Our plans for future work include refining the tool-flow, further optimizing the generated code, and performance testing of a wider range of SDR applications.

关键词： field programmable gate arrays Tools Timing DSL Clocks Ports (Computers) Analytical models

来源：评论

学校读者我要写书评

暂无评论

Security by Design in System on a Chip applications 12

Security by Design in System on a Chip Applications

引用

12th international conference on Cyber Warfare and Security (ICCWS)

作者： Reber, Patrick Graham, Scott Air Force Inst Technol Wright Patterson AFB OH 45433 USA

ISBN: (纸本)9781911218265

System on a Chip (SoC) devices pairing a field programmable Gate Array (FPGA) and a processor on a single chip have grown in popularity and capability since their introduction in 2011, while decreasing in power-consumption and cost. Offering considerable benefits, including shorter development time to market and increased flexibility, these devices continue to capture market share, including medical, military, automotive, and control system applications. Security is essential due to the safety critical nature of these applications. In addition to physical security of these devices, designers must be able to secure the software they run. External interfaces provide malicious actors an attack surface to alter the software executed on the processor or semi-permanently alter the FPGA functionality via remote reprogramming. We contend that the security against both of these threats is permanently influenced by initial design decisions, including configuration modes and data storage choices. Alternatively, configuration mode choices may allow for integrity checking of all boot stages as well as application memory of running programs, reducing security threats. the flexibility offered by SoCs increases this trade space between security, flexibility, integrity, cost, and simplicity. Designers incorporating SoCs into their systems must be informed of these trade-offs to ensure future security of their applications. Previous publications on design guidance focus on capabilities and implementation details without addressing system-level security decisions. these documents aid engineers in how to implement features, but lack advice on meeting security goals. this paper helps to evaluate the security requirements and recommends varied levels of protections.

关键词： FPGA system on a chip attestation programmable logic control security

来源：评论

学校读者我要写书评

暂无评论

SPynq: Acceleration of Machine Learning applications over Spark on Pynq 17

SPynq: Acceleration of Machine Learning Applications over Sp...

引用

17th Annual international conference on Embedded Computer Systems - Architectures, Modeling, and Simulation (SAMOS)

作者： Kachris, Christoforos Koromilas, Elias Stamelos, Ioannis Soudris, Dimitrios NTUA Inst Commun & Comp Syst ICCS Athens Greece Natl Tech Univ Athens Dept Elect & Comp Engn Athens Greece

ISBN: (纸本)9781538634370

Spark is one of the most widely used frameworks for data analytics that offers fast development of applications like machine learning and graph computations in distributed systems. In this paper, we present SPynq: A framework for the efficient utilization of hardware accelerators over the Spark framework on heterogeneous MPSoC FPGAs, such as Zynq. Spark has been mapped to the Pynq platform and the proposed framework allows the seamlessly utilization of the programmable logic for the hardware acceleration of computational intensive Spark kernels. We have also developed the required libraries in Spark that hides the accelerator's details to minimize the design effort to utilize the accelerators. A cluster of 4 nodes (workers) based on the all-programmable MPSoCs has been implemented and the proposed platform is evaluated in a typical machine learning application based on logistic regression. the logistic regression kernel has been developed as an accelerator and incorporated to the Spark. the developed system is compared to a high-performance Xeon cluster that is typically used in cloud computing. the performance evaluation shows that the heterogeneous accelerator-based MpSoC can achieve up to 2.3x system speedup compared with a Xeon system (with 90% accuracy) and 20x better energy-efficiency. For embedded application, the proposed system can achieve up to 40x speedup compared to the software only implementation on low-power embedded processors and 30x lower energy consumption.

关键词： Sparks Hardware Program processors Libraries Machine learning field programmable gate arrays Cloud computing field programmable gate arrays Program processors sparks Cloud Computing Computer hardware Artificial Intelligence Machine Learning Libraries Accelerators design effort Performance Evaluation hardware accelerator

来源：评论

学校读者我要写书评

暂无评论

Implementation and Optimization of the Accelerator Based on FPGA Hardware for LSTM Network 15

Implementation and Optimization of the Accelerator Based on ...

引用

15th IEEE international Symposium on Parallel and Distributed Processing with applications (ISPA) / 16th IEEE international conference on Ubiquitous Computing and Communications (IUCC)

作者： Zhang, Yiwei Wang, Chao Gong, Lei Lu, Yuntao Sun, Fan Xu, Chongchong Li, Xi Zhou, Xuehai USTC Dept Comp Sci & Technol Hefei 230027 Anhui Peoples R China USTC Suzhou Inst Adv Study Suzhou Peoples R China

ISBN: (纸本)9781538637906

Today, artificial neural networks (ANNs) are important machine learning methods which are widely used in a variety of applications. As the emerging field of ANNs, recurrent neural networks (RNNs) are often used for sequence-related applications. And Long Short-Term Memory (LSTM) is an improved RNN which contains complex computational logic. To achieve high accuracy, researchers always build large-scale LSTM networks which are time-consuming and power-consuming. thus the acceleration of LSTM networks, low power & energy consumption become the hot issues in today's research. In this paper, we present a hardware accelerator for the LSTM neural network layer based on FPGA Zedboard and use pipeline methods to parallelize the forward computing process. To optimize our implementation, we also use multiple methods including tiled matrix-vector multiplication, binary adder tree, and overlap of computation and data access. through the acceleration and optimization methods, our accelerator is power-efficient and has a better performance than ARM Cortex A9 processor and Intel Core i5 processor.

关键词： field programmable gate arrays Adders Pipelines Vegetation Hardware Acceleration Computer architecture

来源：评论

学校读者我要写书评

暂无评论

A 550-μW, 2.4-GHz ZigBee/BLE Receiver Front End for IoT applications in 180-nm CMOS

A 550-μW, 2.4-GHz ZigBee/BLE Receiver Front End for IoT app...

引用

Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： Sesha Sairam Regulagadda S. Nagaveni Ashudeb Dutta Indian Institute of Technology Hyderabad India

An ultra-low-power, 2.4 GHz ZigBee and Bluetooth-low-energy (BLE) direct-conversion-receiver front-end for internet of things (IoT) applications is designed and presented. A common-source (CS) Low-noise-amplifier (LNA) and direct back-gate-coupled quadrature-voltage-controlled-oscillator (QVCO) are reusing the current to reduce the power consumption. A symmetrical AND-type passive mixer which converts 50% local oscillator (LO) signal duty cycle to 25% and trans-impedance-amplifier (TIA), converting single-ended RF into differential base-band without I/Q cross talk. Finally, a programmable low-pass-filter (LPF) makes the receiver to operate in both the standards. the proposed full on chip receiver front end is designed with the UMC 180 nm CMOS technology and post layout simulation result show 42dB of conversion-gain (CG), 14 dB of noise-figure (NF),-15dB of S 11 and-16dBm of input referred third order inter modulation intercept point (IIP3). the front end consuming 550 μ W of power with 0.8 V supply and occupied an area of 1 mm 2 .

关键词： Receivers Mixers logic gates Layout ZigBee Simulation Standards

来源：评论

学校读者我要写书评

暂无评论

A 60 GHz Wideband Variable Gain Amplifier in 130nm SiGe BiCMOS for Dielectric Spectroscopy 15

A 60 GHz Wideband Variable Gain Amplifier in 130nm SiGe BiCM...

引用

15th IEEE international New Circuits and Systems conference (NEWCAS)

作者： Yadav, Rahul Kumar Jamal, Farabi Ibne Eissa, Mohamed Wessel, Jan Kissinger, Dietmar IHP Technol Pk 25 D-15236 Frankfurt Oder Germany Tech Univ Berlin Einsteinufer 17 D-10587 Berlin Germany

ISBN: (纸本)9781509049912

this paper presents the design, implementation, layout and measured results of a single stage 60 GHz Variable Gain Amplifier (VGA). the VGA has been implemented in 0.13 mu m SiGe BiCMOS technology with f(t)/f(max) = 250/340 GHz. It provides a tunable gain of -15 to 7 dB. the circuit consumes 32.25 mW of power from 2.5 V supply. It occupies an area of 0.6 mm(2) and it is intended to be deployed in miniaturized dielectric sensing applications.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

A Dynamic Software Product Line Approach for Adaptation Planning in Autonomic Computing Systems 14

A Dynamic Software Product Line Approach for Adaptation Plan...

引用

14th IEEE international conference on Autonomic Computing (ICAC)

作者： Pfannemueller, Martin Krupitzer, Christian Weckesser, Markus Becker, Christian Univ Mannheim Chair Informat Syst 2 D-68131 Mannheim Germany Tech Univ Darmstadt Real Time Syst Lab Merckstr 25 D-64283 Darmstadt Germany

ISBN: (纸本)9781538617625

Modeling the reasoning component of self-adapting systems including its context is a challenging task. Context feature models used in dynamic software product lines help to capture the capabilities of a software as well as the monitored context values. this enables the possibility to add constraints between the context and system features. In this paper, we present an adaptation logic architecture for specifying the knowledge for reasoning in a model-based manner by means of dynamic software product lines. the whole knowledge for reasoning is encapsulated inside a component which enables the reuse of the adaptation logic for various application scenarios. thus, the system designer only has to specify the adaptation logic's knowledge and implement the according interfaces in the managed resource. We evaluate the adaptation logic using our architecture in a distributed computing scenario.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共185页 << < 44 45 46 47 48 49 50 51 52 53 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：