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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1847 条记录，以下是481-490 订阅

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Metasurface: Multi-Element Optical System Design 17

Metasurface: Multi-Element Optical System Design

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17th international conference on Numerical Simulation of Optoelectronic Devices NUSOD

作者： Yilmaz, Nazmi Bagci, Fehim Taha Sumer, Can Demircioglu, Ibrahim Hakki Yilmaz, Burak Kurt, Hamza ASELSAN Inc Ankara Turkey TOBB Univ Econ & Technol Dept Elect & Elect Engn Ankara Turkey

ISBN: (纸本)9781509053230

Metasurfaces that control the amplitude, phase and polarization of light are two-dimensional ultra-thin optical components consisting of nanoscatterers. In this paper, we demonstrate a triplet zoom system by using three different planar lenses (metalenses) working at 600 nm. the movement of metalenses provide three f# values: 1, 1.25, 1.5 and three focal length values: 20, 25, 30 mu m, while total thickness does not change. Our design of triplet zoom system shows that zoom systems could be realized with metasurface applications.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Design and FPGA Implementation of a Fuzzy-PI Controller for Omnidirectional Robot System 4th

Design and FPGA Implementation of a Fuzzy-PI Controller for ...

引用

4th international conference on Robot Intelligence Technology and applications (RiTA)

作者： Masmoudi, Mohamed Slim Krichen, Najla Koesdwiady, Arief B. Karray, Fakhri Masmoudi, Mohamed Natl Sch Elect & Commun Sfax METS Res Grp TechnopkBP 1163CP 3018 Sfax Tunisia Natl Engineers Sch Sfax CEM Lab BP 3000 Sfax Tunisia Univ Waterloo Ctr Pattern Anal & Machine Intelligence Waterloo ON Canada Natl Engineers Sch Sfax METS Res Grp Tunisia Route SoukraKm 3-5BP 1173 Sfax 3038 Tunisia

ISBN: (纸本)9783319312934;9783319312910

Fuzzy logic systems have been implemented successfully for the design of a wide variety of control systems. they provide a powerful way for designing nonlinear controllers using human expert knowledge. In this article, we present an approach to design and implement a fuzzy logic proportional integral controller (Fuzzy-PI) for omnidirectional robot navigation system, using a field-programmable gate array (FPGA). First, we define the kinematic model of the robot system and then we design, simulate, and optimize the controller navigation system using MATLAB and Robot-ino Sim platforms. the main goal of this work is the design of the Fuzzy-PI controller and the hardware implementation using FPGA resources. the controller can be implemented on an FPGA using software or hardware approach. For the latter approach, the Fuzzy-PI algorithm is implemented in VHDL language, synthesized, optimized, placed and routed, and downloaded on an FPGA board.

关键词： Fuzzy logic

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A novel Κ convention logic (NCL) gates architecture based on basic gates 24

A novel Κ convention logic (NCL) gates architecture based o...

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24th IEEE international Congress on Electronics, Electrical Engineering and Computing, INTERCON 2017

作者： Oliveira, Duarte L. Verducci, Orlando Faria, Lester A. Curtinhas, Tiago Electronic Engineering Division Technological Institute of Aeronautics - ITA - IEEA Brazil

ISBN: (纸本)9781509063628

Digital circuit design may demand critical requirements, such as power consumption, robustness, performance, etc., while being implemented in VLSI (Very Large Scale Integration). the asynchronous paradigm presents interesting features that serve as an alternative to these critical requirements. An important class of the asynchronous paradigm is the one called QDI (Quasi Delay Insensitive) circuits that can also be used for critical requirements design. QDI circuits are interesting for these applications because they are robust to certain kinds of faults, to noise and to temperature and supply voltage variations, having also low electromagnetic emissions. An interesting style of QDI circuits is the NCL (Κ Convention logic) circuits because they accept conventional Boolean functions and can achieve great optimization. this paper presents an architecture based on basic QDI gates for the synthesis of NCL gates focusing on VLSI that uses only standard libraries and FPGA (field programmable Gate Array). © 2017 IEEE.

关键词： VLSI circuits

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Sobel filter operation in image processing via stochastic arithmetic-logic unit design

Sobel filter operation in image processing via stochastic ar...

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IEEE Signal Processing and Communications applications (SIU)

作者： Sercan Aygün Mustafa Altun Ece Olcay Güneş Elektronik ve Haberleşme Mühendisliği Bölümü İstanbul Teknik Üniversitesi İstanbul Türkiye Bilgisayar Mühendisliği Bölümü Yıldız Teknik Üniversitesi İstanbul Türkiye

ISBN: (纸本)9781509064953

With the increase of technological developments, the speed limit of the processors that have emerged has accelerated the reduction of nanotechnological solutions of transistors into atomic dimensions from nanometers. Physical systems in which stochastic computation is critical instead of deterministic computation by taking action from atomic behavior are discussed. For this reason, as an interdisciplinary study, this paper will discuss the application of the arithmetic-logic unit in stochastic behavior for the design issues and image processing applications. the logic level design made by considering the design constraints will be used during known image filtering operations. Probabilistic pixel values in binary that sent to the input of the arithmetic logic unit will be used in the Sobel image processing operator. the images are processed with both conventional filter and stochastic filter, then the results obtained will be given visually.

关键词： field programmable gate arrays Image edge detection Transistors Nanoelectronics PSNR Computers

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Automata-to-Routing: An Open-Source Toolchain for Design-Space Exploration of Spatial Automata Processing Architectures

Automata-to-Routing: An Open-Source Toolchain for Design-Spa...

引用

Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Jack Wadden Samira Khan Kevin Skadron University of Virginia Charlottesville Virginia

Newly-available spatial architectures to accelerate finite-automata processing have spurred research and development on novel automata-based applications. However, spatial automata processing architecture research is lacking, because of a lack of automata optimization and place-and-route tools. To solve this issue, we propose a new, open-source toolchain-Automata-to-Routing (ATR)-that enables design-space exploration of spatial automata architectures. ATR leverages existing open-source tools for both automata processing and FPGA architecture research. To demonstrate the usefulness of this new toolchain, we use it to analyze design choices of spatial automata processing architectures. We first show that ATR is capable of modeling the logic tiles of a commercially-available spatial automata processing architecture. We then use ATR to compare and contrast two different routing architecture methodologies-hierarchical and 2D-mesh-over a set of diverse automata benchmarks. We show that shallower 2D-mesh-style routing fabrics can route complex automata with equal channel width, while using up to 4.2x fewer logic tile resources.

关键词： Automata Computer architecture Routing Benchmark testing Open source software Tools field programmable gate arrays

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Hardware Acceleration of Bayesian Neural Networks using RAM based Linear Feedback Gaussian Random Number Generators 35

Hardware Acceleration of Bayesian Neural Networks using RAM ...

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35th IEEE international conference on Computer Design (ICCD)

作者： Cai, Ruizhe Ren, Ao Wang, Luhao Pedram, Massoud Wang, Yanzhi Syracuse Univ Dept Elect Engn & Comp Sci Syracuse NY 13244 USA Univ Southern Calif Dept Elect Engn Los Angeles CA 90089 USA

ISBN: (纸本)9781538622544

Bayesian neural networks (BNNs) have been proposed to address the problem of model uncertainty in training. By introducing weights associated with conditioned probability distributions, BNN is capable to resolve overfitting issues commonly seen in conventional neural networks. Frequent usage of Gaussian random variables requires a properly optimized Gaussian Random Number Generator (GRNG). the high hardware cost of conventional GRNG makes the hardware realization of BNN challenging. In this paper, a new hardware acceleration architecture for variational inference in BNNs is proposed to facilitate the applicability of BNN in larger-scale applications. In addition, the proposed implementation introduced the RAM based Linear Feedback based GRNG (RLF-GRNG) for effective weight sampling in BNNs. the RAM based Linear Feedback method can effectively utilize RAM resources for parallel Gaussian random number generation while requiring limited and sharable control logic. Implementation on an Altera Cyclone V FPGA suggests that the RLF-GRNG utilizes much less RAM resources compared to other GRNG methods. Experiments results show that the proposed hardware implementation of a BNN can still attain similar accuracy compared to software implementation.

关键词： Hardware Neural networks Bayes methods Random access memory field programmable gate arrays Training Software

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"All programmable FPGA, providing hardware efficiency to software programmers"

"All programmable FPGA, providing hardware efficiency to sof...

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international conference on field programmable logic and applications

作者： Ivo Bolsens Xilinx

Smart Systems create new challenges for semiconductor components that need to provide, at one hand, the ease of software programmability and, on the other hand, the capability of hardware efficiency. this dichotomy is driven by, on the one hand, the need for a software stack that supports flexibility, scalability, fast development cycles and, on the other hand, the need for hardware optimization to support performance, efficiency and cost. In this talk, we will discuss the technical trends in major market segments such as datacenters, 5G wireless infrastructure and software defined networking and the resulting requirements for semiconductor platforms, both from hardware and software perspective. To provide an answer to these challenges, it will be demonstrated on how FPGA technology is evolving from a programmable hardware solution catering to ASIC refugees towards an All programmable architecture empowering system and software engineers.

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3-Dimensional Compressive Sensing and High-Quality Recovery for Phased Array Weather Radar 12

3-Dimensional Compressive Sensing and High-Quality Recovery ...

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12th international conference on Sampling theory and applications (SAMPTA)

作者： Kawami, Ryosuke Hirabayashi, Akira Ijiri, Takashi Shimamura, Shigeharu Kikuchi, Hiroshi Ushio, Tomoo Ritsumeikan Univ Sch Info Sci & Eng Kyoto Japan Osaka Univ Grad Sch Eng Suita Osaka Japan

ISBN: (纸本)9781538615652

this paper proposes an effective three-dimensional compressive sensing method for the phased array weather radar (PAWR), which is capable of three-dimensional observation with spatially and temporally high resolution. Because of the large amount of observation data, which is approximately 1 gigabyte per minute, data compression is an essential technology to conduct a network observation by multiple PAWRs. Even though many conventional studies applied compressive sensing (CS) to weather radar measurements, their reconstruction quality should be further improved. To this end, we define a cost function for a three-dimensional recovery exploiting not only local similarity but also global redundancy of weather radar measurements. Since the cost function is convex, we can derive an efficient algorithm based on the standard convex optimization techniques. Simulation results show that the proposed method achieves normalized errors less than 10% for 25% compression ratio with outperforming conventional two-dimensional methods.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Parallel FPGA routing: Survey and challenges

Parallel FPGA routing: Survey and challenges

引用

international conference on field programmable logic and applications

作者： Mirjana Stojilović School of Computer and Communication Sciences Ecole Polytechnique Fédérale de Lausanne (EPFL) Switzerland

As transistor scaling is slowing down [1], other opportunities for ensuring continuous performance increase have to be explored. field programmable gate arrays (FPGAs) are in the spotlight these days: not only due to their malleability and energy efficiency, but also because FPGAs have recently been integrated into the cloud [2]. the latter makes them available to everyone in need of the immense computing power and data throughput they can offer. However, one important issue needs to be resolved first - the time to compile an industrial-scale design for an FPGA must be drastically reduced. Researchers have been looking for ways to accelerate FPGA routing through parallelism, since routing is one of the most time-consuming compilation steps. However, the ideal solution has not been found yet. this paper provides a survey of parallel FPGA routers, with the aim to identify their strengths and weaknesses, thus suggesting directions to take in further efforts for acceleration.

关键词： Routing field programmable gate arrays Program processors Message systems Acceleration Parallel processing Wires

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One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs

One size does not fit all: Implementation trade-offs for ite...

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international conference on field programmable logic and applications

作者： Gaël Deest Tomofumi Yuki Sanjay Rajopadhye Steven Derrien Univ. Rennes 1 / IRISA INRIA / IRISA Colorado State University

Iterative stencils are kernels in various application domains such as numerical simulations and medical imaging, that merit FPGA acceleration. the best architecture depends on many factors such as the target platform, off-chip memory bandwidth, problem size, and performance requirements. We generate a family of FPGA stencil accelerators targeting emerging System on Chip platforms, (e.g., Xilinx Zynq or Intel SoC). Our designs come with design knobs to explore trade-offs. We also propose performance models to hone in on the most interesting design points, and show how they accurately lead to optimal designs. the optimal choice depends on problem sizes and performance goals.

关键词： field programmable gate arrays System-on-chip Pipeline processing Memory management Acceleration Bandwidth Hardware

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