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Designing a Virtual Runtime for FPGA Accelerators in the Cloud 26

Designing a Virtual Runtime for FPGA Accelerators in the Clo...

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26th international conference on field-programmable logic and applications (FPL)

作者： Asiatici, Mikhail George, Nithin Vipin, Kizheppau Fahmy, Suhaib A. Ienne, Paolo Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland Mahindra Ecole Cent Hyderabad Telangana India Univ Warwick Sch Engn Coventry CV4 7AL W Midlands England

ISBN: (纸本)9782839918442

FPGAs can provide high performance and energy efficiency to many applications;therefore, they are attractive computing platforms in a cloud environment. However, FPGA application development requires extensive hardware design knowledge which significantly limits the potential user base. Moreover, in a cloud setting, allocating a whole FPGA to a user is often wasteful and not cost effective due to low device utilization. To make FPGA application development easier, firstly, we propose a methodology that provides clean abstractions with high-level APIs and a simple execution model that supports both software and hardware execution. Secondly, to improve device utilization and share the FPGA among multiple users, we developed a lightweight runtime system that provides hardware-assisted memory virtualization and memory protection, enabling multiple applications to simultaneously execute on the device.

关键词： field programmable gate arrays (FPGA)

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Memory Efficient and High Performance Key-value Store on FPGA Using Cuckoo Hashing 26

Memory Efficient and High Performance Key-value Store on FPG...

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26th international conference on field-programmable logic and applications (FPL)

作者： Liang, Wei Yin, Wenbo Kang, Ping Wang, Lingli Fudan Univ State Key Lab ASIC & Syst Shanghai Peoples R China

ISBN: (纸本)9782839918442

Key-value stores (KVS) become critical in many applications because of the data explosion recently. there is a strong demand to improve the throughput and reduce the latency for KVS. FPGA-based parallel architecture can bring excellent performance and power efficiency. Cuckoo hashing has proven to be an efficient approach to implement KVS with good memory utilization and constant worst case access time. In this paper, an FPGA-based KVS implementation is proposed based on Cuckoo hashing, with a decoupled storage to achieve 81.7% memory utilization, and a pipeline scheme to achieve high performance. the latency of insert, search and delete operations is only 40 ns. And the throughput for search and delete can be 200 million requests per second (MRPS) which is 5x faster than [1]. Even when the load factor becomes 0.9, the throughput for insert can still achieve 147 MRPS.

关键词： field programmable gate arrays (FPGA)

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Configurable and Scalable Belief Propagation Accelerator for Computer Vision 26

Configurable and Scalable Belief Propagation Accelerator for...

引用

26th international conference on field-programmable logic and applications (FPL)

作者： Choi, Jungwook Rutenbar, Rob A. IBM TJ Watson Res Ctr Yorktown Hts NY 10598 USA Univ Illinois Dept Comp Sci 1304 W Springfield Ave Urbana IL 61801 USA

ISBN: (纸本)9782839918442

We demonstrate a novel FPGA-based accelerator architecture that can tackle a range of standard computer vision (CV) problems, with scalable performance and attractive speedups. the architecture relies on multiple pipelined processing elements (PEs) that can be configured to support various belief propagation (BP) settings for different CV tasks. Inside each PE, innovative implementation of Jump Flooding for efficient computation of BP solves the core configurability challenge. A novel block-parallel memory interface supports parallelization by distributing BP inference workloads across the PEs. Experimental results demonstrate that our accelerator achieves scalable performance with 11-41x speedup over standard sequential CPU implementations across a subset of well-known Middlebury and OpenGM benchmarks, with no compromise in quality of inference results. To the best of our knowledge, this is the first FPGA hardware implementation of BP capable of running a range of standard CV benchmarks with significant speedups.

关键词： Belief propagation computer vision Markov random field field programmable gate arrays

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Measure Twice and Cut Once: Robust Dynamic Voltage Scaling for FPGAs 26

Measure Twice and Cut Once: Robust Dynamic Voltage Scaling f...

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26th international conference on field-programmable logic and applications (FPL)

作者： Ahmed, Ibrahim Zhao, Shuze Trescases, Olivier Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9782839918442

Although dynamic voltage scaling (DVS) is a popular power reduction solution that has been widely used by processors and ASICs, it is still not commercially adopted by FPGAs. A unique feature of FPGAs that leads to challenges in adopting DVS is that the critical path and hence the minimum safe V-dd depends on the configured application. We present a robust DVS technique that solves these challenges. For each application, we generate a calibration table (CT) that stores the actual failing points of that application on a specific FPGA, under various operating conditions. this CT is used to scale V-dd while the application is running to guarantee safe operation with minimal power consumption. We develop an automated tool (FRoC) that ensures a Fast-Robust-Calibration of the FPGA to any application using it. FRoC ensures that the calibration process is invisible to FPGA users and does not add any extra manual steps to the design process. We show that our proposed DVS technique achieves a 33% total power reduction on two large applications.

关键词： field programmable gate arrays (FPGA)

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Bayesian Inference implemented on FPGA with Stochastic Bitstreams for an Autonomous Robot 26

Bayesian Inference implemented on FPGA with Stochastic Bitst...

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26th international conference on field-programmable logic and applications (FPL)

作者： Fernandes, Hugo Awais Aslam, M. Lobo, Jorge Ferreira, Joao Filipe Dias, Jorge Univ Coimbra ISR P-3000 Coimbra Portugal Univ Coimbra ISR DEEC P-3000 Coimbra Portugal Khalifa Univ Abu Dhabi U Arab Emirates

ISBN: (纸本)9782839918442

this paper presents an FPGA implementation of a machine performing exact Bayesian inference using stochastic bitstreams. We revisited stochastic computing, not to perform better computations with unreliable hardware, but to perform approximate computations with less hardware. the underlying trade-off is between precision and computation time. An automatic design of probabilistic machines that compute soft inferences with an arithmetic based on stochastic bitstreams is presented. the computation tree provided by a Bayesian inference software is used to define the stochastic circuit. Tests were performed and results presented concerning accuracy and resource usage of the stochastic computing implementation of Bayesian machines performing exact inference. An application example is given of a Bayesian sensorimotor system that performs obstacle avoidance for an autonomous robot, fully implemented on an FPGA. Some conclusions were drawn on the followed approach, providing insights for future implementations.

关键词： field programmable gate arrays (FPGA)

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An Implementation method of the Box Filter on FPGA 26

An Implementation method of the Box Filter on FPGA

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26th international conference on field-programmable logic and applications (FPL)

作者： Wang, Sichao Maruyama, Tsutomu Univ Tsukuba Syst & Informat Engn 1-1-1 Tennodai Tsukuba Ibaraki Japan

ISBN: (纸本)9782839918442

the box filter is widely used in image processing. Its computational complexity is low, and many other filters can be realized by using different size box filters. the implementation method of the box filter that is widely used in the software programs requires an array to store data, the size of which is filter size x image width. this array often limits the feasibility of the box filter on FPGA, because its size is proportional to the image width. In this paper, we show an implementation method of the box filter that requires less memory. Two types of wide-width but shallow memory are required in this method, but these memory can be efficiently realized on FPGA using distributed RAMs and block RAMs. In this method, the image is scanned in zigzag. the performance is decreased because of the necessity to overlap the zigzag scan, but it is fast enough for practical use. this zigzag scan enable to reduce the memory size to store data, but extra line buffers are required. Our approach is specially effective for applications that calculate cross-correlations for finding the best matching, because the overhead caused by the extra line buffers becomes relatively small in these applications. We show the effectiveness of our method using a stereo vision program based on the cost aggregation with guided filter.

关键词： field programmable gate arrays (FPGA)

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Connect On the Fly: Enhancing and Prototyping of Cycle-Reconfigurable Modules 26

Connect On the Fly: Enhancing and Prototyping of Cycle-Recon...

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26th international conference on field-programmable logic and applications (FPL)

作者： Zhou, Hao Niu, Xinyu Yuan, Junqi Wang, Lingli Luk, Wayne Imperial Coll London Sch Engn Dept Comp London England Fudan Univ Sch Microelect Shanghai Peoples R China

ISBN: (纸本)9782839918442

this paper introduces cycle-reconfigurable modules that enhance FPGA architectures with efficient support for dynamic data accesses: data accesses with accessed data size and location known only at runtime. the proposed module adopts new reconfiguration strategies based on dynamic FIFOs, dynamic caches, and dynamic shared memories to significantly reduce configuration generation and routing complexity. We develop a prototype FPGA chip with the proposed cycle-reconfigurable module in the SMIC 130-nm technology. the integrated module takes less than the chip area of 39 CLBs, and reconfigures thousands of runtime connections in 1.2 ns. applications for large-scale sorting, sparse matrix-vector multiplication, and Memcached are developed. the proposed modules enable 1.4 and 11 times reduction in area-delay product compared with those applications mapped to previous architectures and conventional FPGAs.

关键词： field programmable gate arrays (FPGA)

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Optimising Sparse Matrix Vector Multiplication for Large Scale FEM problems on FPGA 26

Optimising Sparse Matrix Vector Multiplication for Large Sca...

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26th international conference on field-programmable logic and applications (FPL)

作者： Grigoras, Paul Burovskiy, Pavel Luk, Wayne Sherwin, Spencer Imperial Coll London Dept Comp London England Imperial Coll London Dept Aeronaut London England

ISBN: (纸本)9782839918442

Sparse Matrix Vector multiplication (SpMV) is an important kernel in many scientific applications. In this work we propose an architecture and an automated customisation method to detect and optimise the architecture for block diagonal sparse matrices. We evaluate the proposed approach in the context of the spectral/hp Finite Element Method, using the local matrix assembly approach. this problem leads to a large sparse system of linear equations with block diagonal matrix which is typically solved using an iterative method such as the Preconditioned Conjugate Gradient. the efficiency of the proposed architecture combined with the effectiveness of the proposed customisation method reduces BRAM resource utilisation by as much as 10 times, while achieving identical throughput with existing state of the art designs and requiring minimal development effort from the end user. In the context of the Finite Element Method, our approach enables the solution of larger problems than previously possible, enabling the applicability of FPGAs to more interesting HPC problems.

关键词： field programmable gate arrays (FPGA)

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SoCLog: A Real-Time, Automatically Generated Logging and Profiling Mechanism for FPGA-based Systems On Chip 26

SoCLog: A Real-Time, Automatically Generated Logging and Pro...

引用

26th international conference on field-programmable logic and applications (FPL)

作者： Parnassos, Ioannis Skrimponis, Panagiotis Zindros, Georgios Bellas, Nikolaos CERTH Thessaloniki Greece Univ Thessaly Volos Greece

ISBN: (纸本)9782839918442

Recent advances in FPGA technology and the proliferation of High Level Synthesis (HLS) tools makes it possible to implement complex System on Chip (SoC) designs that realize complete applications in a single FPGA device. To be able to exploit the large performance vs. area search space of such modern FPGA-based SoCs, system architects must have the appropriate performance analysis tools to evaluate-preferably at runtime-the computational requirements and the data flow of such a system to determine potential performance bottlenecks when running realistic workloads. In this paper we introduce SoCLog, a framework that automatically enhances the platform architecture with additional hardware components used to generate activity logs when the base SoC architecture executes an application. this real-time information can be analyzed by the system designer to expose performance bottlenecks not only on aggregate, but also at clock cycle granularity thus revealing potential design inefficiencies when there is burst of activity in the system. We evaluate our framework with a number of SoC designs to show that such a logging information can be valuable for the design of a complex SoC in a modern FPGA with minimal area overhead.

关键词： field programmable gate arrays (FPGA)

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Optimal Random Sampling Based Path Planning on FPGAs 26

Optimal Random Sampling Based Path Planning on FPGAs

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26th international conference on field-programmable logic and applications (FPL)

作者： Xiao, Size Postula, Adam Bergmann, Neil Univ Queensland Sch Informat Technol & Elect Engn Brisbane Qld 4072 Australia

ISBN: (纸本)9782839918442

Random sampling based path planning algorithms have shown their high efficiency in robotics, navigation and related fields. the Rapidly-Exploring Random Trees (RRT) is the typical method and works well in a variety of applications. Due to the sub-optimal issue of original RRT, the recent algorithm, known as RRT*, significantly improves the optimality of solution by adding the "cost review" procedure. However, the original RRT experiences the bottle neck of complicated iterations and it becomes worse in RRT*. this paper presents the developed hardware architecture for RRT*, which fully exploits the parallel potential of algorithm. Unlike the sequential execution in software, the "exploration" and "review" are identified as independent processes and executed in parallel. For the complicated operation of inserting vertexes, one pipelined Kd-tree constructor is designed to fast rebuild the tree when new vertex generated. Furthermore, to speed up the near neighbors and nearest neighbor searching, the vertexes are stored in separate Kd-trees so that the search processes can be carried out concurrently in each data tree. this work explores the possible and power-efficient RRT* hardware architecture on FPGAs compared to PC implementation.

关键词： field programmable gate arrays (FPGA)

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