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Efficient and Reliable High-Level Synthesis Design Space Explorer for FPGAs 26

Efficient and Reliable High-Level Synthesis Design Space Exp...

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26th international conference on field-programmable logic and applications (FPL)

作者： Liu, Dong Schafer, Benjamin Carrion Hong Kong Polytech Univ Dept Elect & Informat Engn Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9782839918442

this paper presents a dedicated High-Level Synthesis (HLS) Design Space Explorer (DSE) for FPGAs. C-based VLSI design has the advantage over conventional RTL design that it allows the generation of micro-architectures with unique area vs. performance trade-offs without having to modify the original behavioral description (in this work area vs. latency). this is typically done by modifying the Functional Unit (FU) constraint file or setting different synthesis directives e.g. unroll loops or synthesize arrays as RAM or registers. the result of the design space exploration is a set of Pareto-optimal designs. In this work, we first investigate the quality of the exploration results when using the results reported after HLS (in particular the area) to guide the explorer in finding Pareto-optimal designs. We found that due to the nature of how HLS tools pre-characterize, the area and delay of basic logic primitives and the FPGAs internal structure the area results are not accurate and hence making it necessary to perform a logic synthesis after each newly generated design. this in turn leads to unacceptable long running time. this work therefore presents a dedicated DSE for FPGAs based on a pruning with adaptive windowing method to extract the design candidates to be further (logic) synthesized after HLS. the adaptive windowing is based on a learning method inspired from Rival Penalized Competitive Learning (RPCL) model in order to classify which designs need to be synthesized to find the true Pareto-optimal designs. Results show that our method leads to similar results compared to an explorer which performs a logic synthesis for each newly generated design, while being much faster.

关键词： field programmable gate arrays (FPGA)

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Automated Extra Pipeline Analysis of applications mapped to Xilinx UltraScale plus FPGAs 26

Automated Extra Pipeline Analysis of Applications mapped to ...

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26th international conference on field-programmable logic and applications (FPL)

作者： Ganusov, Ilya Fraisse, Henri Ng, Aaron Possignolo, Rafael Trapani Das, Sabya Xilinx Inc 2100 Log Dr San Jose CA 95124 USA Univ Calif Santa Cruz Dept Comp Engn Santa Cruz CA 95064 USA

ISBN: (纸本)9782839918442

this paper describes the methodology and algorithms behind extra pipeline analysis tools released in the Xilinx Vivado Design Suite version 2015.3. Extra pipelining is one of the most effective ways to improve performance of FPGA applications. Manual pipelining, however, often requires significant efforts from FPGA designers who need to explore various changes in the RTL and re-run the flow iteratively. the automatic pipelining approach described in this paper, in contrast, allows FPGA users to explore latency vs. performance trade-offs of their designs before investing time and effort into modifying RTL. We describe algorithms behind these tools which use simple cut heuristics to maximize performance improvement while minimizing additional latency and register overhead. To demonstrate the effectiveness of the proposed approach, we analyse a set of 93 commercial FPGA applications and IP blocks mapped to Xilinx UltraScale+ and UltraScale generations of FPGAs. the results show that extra pipelining can provide from 18% to 29% potential Fmax improvement on average. It also shows that the distribution of improvements is bimodal, with almost half of benchmark suite designs showing no improvement due to the presence of large loops. Finally, we demonstrate that highly-pipelined designs map well to UltraScale+ and UltraScale FPGA architectures. Our approach demonstrates 19% and 20% Fmax improvement potential for the UltraScale+ and UltraScale architectures respectively, with the majority of applications reaching their loop limit through pipelining.

关键词： field programmable gate arrays (FPGA)

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FPGA-Based Accelerator Design from a Domain-Specific Language 26

FPGA-Based Accelerator Design from a Domain-Specific Languag...

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26th international conference on field-programmable logic and applications (FPL)

作者： Oezkan, M. Akif Reiche, Oliver Hannig, Frank Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Nurnberg Germany

ISBN: (纸本)9782839918442

A large portion of image processing applications often come with stringent requirements regarding performance, energy efficiency, and power. FPGAs have proven to be among the most suitable architectures for algorithms that can be processed in a streaming pipeline. Yet, designing imaging systems for FPGAs remains a very time consuming task. High-Level Synthesis, which has significantly improved due to recent advancements, promises to overcome this obstacle. In particular, Altera OpenCL is a handy solution for employing an FPGA in a heterogeneous system as it covers all device communication. However, to obtain efficient hardware implementations, extreme code modifications, contradicting OpenCL's data-parallel programming paradigm, are necessary. In this work, we explore the programming methodology that yields significantly better hardware implementations for the Altera Offline Compiler. We furthermore designed a compiler back end for a domain-specific source-to-source compiler to leverage the algorithm description to a higher level and generate highly optimized OpenCL code. Moreover, we advanced the compiler to support arbitrary bit width operations, which are fundamental to hardware designs. We evaluate our approach by discussing the resulting implementations throughout an extensive application set and comparing them with example designs, provided by Altera. In addition, as we can derive multiple implementations for completely different target platforms from the same domain-specific language source code, we present a comparison of the achieved implementations in contrast to GPU implementations.

关键词： field programmable gate arrays (FPGA)

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Approximate Frequent Itemset Mining for Streaming Data on FPGA 26

Approximate Frequent Itemset Mining for Streaming Data on FP...

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26th international conference on field-programmable logic and applications (FPL)

作者： Li, Yubin Sun, Yuliang Dai, Guohao Xu, Qiang Wang, Yu Yang, Huazhong Tsinghua Univ Dept EE Beijing Peoples R China Chinese Univ Hong Kong Dept CS Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9782839918442

Frequent Itemset Mining (FIM) is designed to find frequently occurring itemsets among a series of transactions. It is extremely memory and time expensive. Frequent Itemset Mining from a Data Stream (FIM-DS) is even more challenging since storing the infinite data to memory is infeasible. In recent years, researchers have proposed various approximation algorithms for FIM-DS. However, the computation complexity is still high, and these methods are difficult to be accelerated using hardware accelerators. In this paper, we propose a Space-Saving based approximate algorithm for FIM-DS. It avoids exponential candidates generation and comparisons. We realize a hardware accelerator design and implement it on an FPGA platform. Experimental results show that our algorithm in software implementation achieves up to 8.4x speedup for transactions with small item database, and our hardware accelerator achieves up to 50,000x speedup for transactions with small number of items, and 5.3x speedup for transactions with extremely large number of items.

关键词： field programmable gate arrays (FPGA)

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Liquid: Fast Placement Prototyping through Steepest Gradient Descent Movement 26

Liquid: Fast Placement Prototyping Through Steepest Gradient...

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26th international conference on field-programmable logic and applications (FPL)

作者： Vansteenkiste, Elias Lenders, Seppe Stroobandt, Dirk Univ Ghent Dept Elect & Informat Syst Comp Syst Lab Hardware & Embedded Syst Grp B-9000 Ghent Belgium

ISBN: (纸本)9782839918442

FPGA design compilation takes too much time to allow efficient design turnaround times. the largest runtime consuming steps of the compilation are placement and routing. To speed up the FPGA placement process, analytical placement techniques have become more popular in the last decade. Analytical techniques produce a placement in two steps, a placement prototyping step and a refinement step. In this work we focus on fast FPGA placement prototyping. Placement prototypes are also used to obtain fast accurate timing estimations and speed up the design cycle. In conventional analytical placement prototyping techniques the placement problem is formulated as a linear system which is solved several times to find a good legal placement. the most time consuming step of that process is solving the linear system. We show that it is not necessary to exactly solve this system, but that it is sufficient to optimize the placement following the steepest gradient descent in between legalization phases. this technique is implemented in our new placement tool called LIQUID. In LIQUID each block's position is updated several times following an accelerated gradient simulation. We compare this new technique with conventional analytical placement. the Titan23 designs and the Stratix IV FPGA are used for benchmarking. the net effect is that the runtime can be reduced by 2x on average compared to conventional analytical placement without losing any quality.

关键词： field programmable gate arrays (FPGA)

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An Evaluation on the Accuracy of the Minimum Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures 26

An Evaluation on the Accuracy of the Minimum Width Transisto...

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26th international conference on field-programmable logic and applications (FPL)

作者： Khan, Farheen Fatima Ye, Andy Ryerson Univ Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9782839918442

this work provides an evaluation on the accuracy of the minimum width transistor area models in ranking the actual layout area of FPGA architectures. Both the original VPR area model and the new COFFE area model are compared against the actual layouts with up to 3 metal layers for the various FPGA building blocks. We found that both models have significant variations with respect to the accuracy of their predictions across the building blocks. In particular, the original VPR model overestimates the layout area of larger buffers and full adders by as much as 34% while underestimate the layout area of smaller buffers and multiplexers by as much as 59% for an overall prediction error variation of 93%. the newer COFFE model also significantly overestimates the layout area of full adders by 13% and underestimates the layout area of multiplexers by a maximum of 58% for a prediction error variation of 71%. Such variations are particularly significant considering sensitivity analyses are not routinely performed in FPGA architectural studies. Our results suggest that such analyses are extremely important in studies that employing the minimum width area models so the tolerance of the architectural conclusions against the prediction error variations can be quantified. Furthermore, an open source version of the layouts of the actual FPGA building blocks should be created, so their actual layout area can be used to achieve a highly accurate ranking of the implementation area of FPGA architectures built upon these layouts.

关键词： field-programmable Gate Array (FPGA) layout area estimation area modeling Silicon-On-Chip (SOC) reconfigurable fabrics

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Survey of Domain-Specific Languages for FPGA Computing 26

Survey of Domain-Specific Languages for FPGA Computing

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26th international conference on field-programmable logic and applications (FPL)

作者： Kapre, Nachiket Bayliss, Samuel Nanyang Technol Univ Sch Comp Sci & Engn Singapore 639798 Singapore Imperial Coll London Dept Elect & Elect Engn London SW7 2BT England

ISBN: (纸本)9782839918442

High-performance FPGA programming has typically been the exclusive domain of a small band of specialized hardware developers. they are capable of reasoning about implementation concerns at the register-transfer level (RTL) which is analogous to assembly-level programming in software. Sometimes these developers are required to push further down to manage even lower levels of abstraction closer to physical aspects of the design such as detailed layout to meet critical design constraints. In contrast, software programmers have long since moved away from textual assembly-level programming towards relying on graphical integrated development environments (IDEs), high-level compilers, smart static analysis tools and runtime systems that optimize, manage and assist the program development tasks. Domain-specific languages (DSLs) can bridge this productivity gap by providing higher levels of abstraction in environments close to the domain of application expert. DSLs carefully limit the set of programming constructs to minimize programmer mistakes while also enabling a rich set of domain-specific optimizations and program transformations. With a large number of DSLs to choose from, an inexperienced FPGA user may be confused about how to select an appropriate one for the intended domain. In this paper, we review a combination of legacy and state-of-the-art DSLs available for FPGA development and provide a taxonomy and classification to guide selection and correct use of the framework.

关键词： field programmable gate arrays (FPGA)

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A Survey of AIS-20/31 Compliant TRNG Cores Suitable for FPGA Devices 26

A Survey of AIS-20/31 Compliant TRNG Cores Suitable for FPGA...

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26th international conference on field-programmable logic and applications (FPL)

作者： Petura, Oto Mureddu, Ugo Bochard, Nathalie Fischer, Viktor Bossuet, Lilian Jean Monnet Univ St Etienne Hubert Curien Lab UMR CNRS 5516 18 Rue Pr Lauras F-42000 St Etienne France

ISBN: (纸本)9782839918442

FPGAs are widely used to integrate cryptographic primitives, algorithms, and protocols in cryptographic systemson-chip (CrySoC). As a building block of CrySoCs, True Random Number Generators (TRNGs) exploit analog noise sources in electronic devices to generate confidential keys, initialization vectors, challenges, nonces, and random masks in cryptographic protocols. TRNGs aimed at cryptographic applications must fulfill the security requirements defined in the German Federal Bureau for Information Security's (BSI) recommendations AIS20/31, which has become a de facto standard in Europe. Many TRNG cores have already been published, only a few of which are suitable for FPGAs and even fewer comply with AIS-20/31. Here we present the results of the implementation of AIS-20/31 compliant TRNG cores in three FPGA families: Xilinx Spartan 6, Altera Cyclone V and Microsemi SmartFusion 2. In addition to common design parameters like area, bit rate and power/energy consumption, we compare and discuss the feasibility of generator cores in different FPGAs and the statistical quality of their output. these results will help designers select the best generator and the device family to match the requirements of the data security application. To ensure reproducibility of the results, the open source VHDL code of all generators adapted to individual families can be downloaded from the dedicated web page.

关键词： field programmable gate arrays (FPGA)

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Relational Query Processing on OpenCL-based FPGAs 26

Relational Query Processing on OpenCL-based FPGAs

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26th international conference on field-programmable logic and applications (FPL)

作者： Wang, Zeke Paul, Johns Ntu, Hui Yan Cheah He, Bingsheng Zhang, Wei Nanyang Technol Univ Singapore Singapore NUS Singapore Singapore HKUST Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9782839918442

the release of OpenCL support for FPGAs represents a significant improvement in extending database applications to the reconfigurable domain. Taking advantage of the programmability offered by the OpenCL HLS tool, an OpenCL database can be easily ported and re-designed for FPGAs. A single SQL query in these database systems usually consists of multiple operators, and each one of these operators in turn consists of multiple OpenCL kernels. Due to the specific properties of FPGAs, each OpenCL kernel can have different FPGA-specific optimization combinations, in terms of CU (compute unit) and SIMD (kernel vectorization), which are critical to the overall performance of query processing. Due to the resource limitation of an FPGA image, our query plan also considers the possibility of using multiple FPGA images. In this paper, we propose an FPGA-specific cost model to determine the optimal query plan in less than one minute. In particular, the FPGA synthesis time is significantly reduced by avoiding the need to evaluate all the feasible query plans on real FPGAs. Our cost model has two components: unit cost and optimal query plan generation. the first component generates multiple (unit cost, resource utilization) pairs for each kernel. the second component employs a dynamic programming approach to generate the optimal query plan which considers the possibility of using multiple FPGA images. the experiments show that 1) our cost model can accurately predict the performance of each feasible query plan for the input query, and can guide the optimal query plan generation, 2) our optimized query plan achieves a performance speedup 1.5x-4x over the state-of-the-art query processing on OpenCL-based FPGAs.

关键词： field programmable gate arrays (FPGA)

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A novel template-based multimedia processor array and its toolset

A novel template-based multimedia processor array and its to...

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international conference on Electrical and Electronics Engineering, ELECO

作者： Mehmet Tükel Arda Yurdakul Berna Örs Department of Electronics and Communication Engineering Istanbul Technical University Department of Computer Engineering Boğaziçi University

In this paper, we propose a template-based multimedia processor array and its design framework. the configurable processor array is designed for low-cost, low-power image/ video processing applications. Each processor in the array is template-based and implemented by considering the nature and specifications of image/video processing domain. the framework can set the size of the network and the parameters of the building blocks of each processor. Hence, the generated architecture occupies only the necessary amount of logic. To show the scalability and the performance of the design, different instances of the architecture implementing four test applications are generated. We have obtained better or comparable results in terms of energy consumption, throughput and area occupation compared to that of the similar architectures in literature.

关键词： Computer architecture Registers Parallel processing Hardware Image processing field programmable gate arrays Software

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