检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,813 篇 会议
29 篇 期刊文献
5 册 图书

馆藏范围

1,847 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,202 篇 工学
- 1,019 篇 计算机科学与技术...
- 707 篇 软件工程
- 388 篇 电气工程
- 186 篇 电子科学与技术（可...
- 62 篇 信息与通信工程
- 60 篇 控制科学与工程
- 26 篇 机械工程
- 26 篇 仪器科学与技术
- 25 篇 动力工程及工程热...
- 24 篇 建筑学
- 16 篇 土木工程
- 14 篇 生物工程
- 11 篇 核科学与技术
- 10 篇 材料科学与工程（可...
- 9 篇 光学工程
- 8 篇 生物医学工程（可授...
- 8 篇 安全科学与工程
- 6 篇 化学工程与技术
- 6 篇 交通运输工程
146 篇 理学
- 97 篇 数学
- 33 篇 物理学
- 16 篇 生物学
- 14 篇 系统科学
- 10 篇 统计学（可授理学、...
- 6 篇 化学
52 篇 管理学
- 39 篇 管理科学与工程(可...
- 17 篇 工商管理
- 15 篇 图书情报与档案管...
14 篇 法学
- 12 篇 社会学
9 篇 经济学
- 9 篇 应用经济学
8 篇 医学
6 篇 农学
4 篇 军事学
2 篇 教育学

主题

816 篇 field programmab...
670 篇 field programmab...
271 篇 hardware
154 篇 computer archite...
119 篇 logic gates
111 篇 table lookup
94 篇 clocks
83 篇 throughput
78 篇 random access me...
72 篇 routing
71 篇 acceleration
71 篇 software
66 篇 optimization
63 篇 kernel
61 篇 delays
52 篇 registers
52 篇 logic
49 篇 switches
46 篇 algorithm design...
45 篇 computational mo...

机构

15 篇 univ toronto dep...
9 篇 department of co...
9 篇 imperial coll lo...
8 篇 ecole polytech f...
7 篇 univ british col...
7 篇 school of comput...
7 篇 brigham young un...
7 篇 imperial coll lo...
7 篇 tokyo inst techn...
6 篇 univ tsukuba tsu...
6 篇 university of ch...
6 篇 department of el...
6 篇 univ warwick sch...
6 篇 xilinx inc san j...
5 篇 univ manchester ...
5 篇 department of el...
5 篇 univ toronto dep...
5 篇 swiss fed inst t...
5 篇 xilinx inc 2100 ...
5 篇 altera corp san ...

作者

33 篇 luk wayne
21 篇 maruyama tsutomu
16 篇 wayne luk
16 篇 koch dirk
12 篇 wilton steven j....
12 篇 betz vaughn
12 篇 ienne paolo
11 篇 fahmy suhaib a.
11 篇 cheung peter y. ...
10 篇 vaughn betz
9 篇 constantinides g...
8 篇 suhaib a. fahmy
8 篇 prasanna viktor ...
8 篇 chow paul
8 篇 glesner manfred
8 篇 amano hideharu
8 篇 akash kumar
7 篇 kapre nachiket
7 篇 alonso gustavo
7 篇 hutchings brad

语言

1,838 篇 英文
9 篇 其他

检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1847 条记录，以下是561-570 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Accelerating particle identification for high-speed data-filtering using OpenCL on FPGAs and other architectures OpenCL for FPGA in High Energy Physics 26

Accelerating particle identification for high-speed data-fil...

引用

26th international conference on field-programmable logic and applications (FPL)

作者： Sridharan, Srikanth Durante, Paolo Faerber, Christian Neufeld, Niko CERN LHCb Geneva Switzerland

ISBN: (纸本)9782839918442

the upgrade of the LHCb experiment at CERN envisions a Data Acquisition and Event Filtering system that captures 100% of the data generated by the various subdetectors, which measure with great precision the 40 million collisions per second of protons in CERN's Large Hadron Collider. the sensor readings result in about 40 Tbit/s of data, which need to be processed on a large computer farm. Since the computation on CPUs, as it is currently done, does not scale well, it is necessary to accelerate a good portion of the code to meet the computational demands of the proposed system. We are therefore looking for means to accelerate the most time-consuming parts of the event-filtering code. the Ring Imaging Cherenkov (RICH) detectors are one of the component detectors of the overall LHCb experiment. the Cherenkov photon that hits the detector are processed to determine the track of the original particle that caused these photons. the particle velocity and mass, derived from the Cherenkov angle, is used to identify the particle. the entire RICH photon reconstruction algorithm accounts for 50% of the second High Level Trigger (HLT) process and Cherenkov angle reconstruction comprises about 20% of the RICH and is a good candidate for acceleration. An OpenCL implementation of Cherenkov angle reconstruction algorithm that calculates the trajectory of Photons in the RICH detector was developed. the paper looks at the results of the OpenCL implementation of the algorithm on the Nallatech 385 card with Altera Strati x V FPGA, Nvidia GeForce GTX 690 GPU card and the Intel Xeon processor for comparison. While the two GPUs are 3.6X faster than a single FPGA, the FPGA is 3.4X better than two GPUs and 6.6X better than two multicore CPUs when energy efficiency is factored. Although significant speedup of computation was achieved on all the above architectures by using OpenCL, a good portion of the gain was lost due to the overhead of data transfer and parallelism. Different strategies a

关键词： FPGA field prgrammable gate arrays OpenCL GPU GPGPU High throughput computing HTC LHCb HEP High Energy Physics CEKN

来源：评论

学校读者我要写书评

暂无评论

A low bit-width parameter representation method for hardware-oriented convolution neural networks

A low bit-width parameter representation method for hardware...

引用

international conference on ASIC

作者： Qiang Chen Chen Xin Chenglong Zou Xinan Wang Bo Wang School of ECE The Key Laboratory of Integrated Microsystem Shenzhen China

Convolution neural networks (CNNs) have become the state-of-the-art technique for Artificial Intelligence (AI) applications. But they consume resources heavily both in computation and energy. Compressing the parameters to fewer bits is an effective way to reduce data quantity, making it possible to deploy CNNs on mobile, IoT and other resource-limited devices. the existing means need to re-train the entire networks and tune the parameters. this paper presents a convenient method to compress the parameters of trained CNN models without re-training and fine-tuning. Our method reduces the number of bits from 32 to 5-9 under the same networks and on the same dataset, with the loss of accuracy less than 1%. the logic power of a trained LeNet reduces by 70.58% on FPGA evaluation.

关键词： Quantization (signal) field programmable gate arrays Hardware Adders C++ languages Convolution Neural networks

来源：评论

学校读者我要写书评

暂无评论

Debugging Framework for FPGA-based Soft Processors 15

Debugging Framework for FPGA-based Soft Processors

引用

15th international conference on field-programmable Technology (FPT)

作者： Sidler, David Eguro, Ken Swiss Fed Inst Technol Dept Comp Sci Zurich Switzerland Microsoft Res Redmond WA USA

ISBN: (纸本)9781509056026

Soft processors are one way to raise the computational abstraction of FPGAs while keeping the advantages of reconfigurable hardware, such as adaptability, deterministic performance and high performance/watt. Software developers can quickly build, test and deploy applications using familiar tools while still leveraging important optimizations such as application-specific custom instructions. However, they also present unique debugging problems. For example, the higher-level programming abstraction runs contradictory to classical low-level debugging tools like logic analyzers. In this work we present a debugging framework for FPGA-based soft processors that enables step-by-step debugging at the level of all soft processor instructions, timetravel debugging, post-mortem memory dumps, and performance metrics. By using knowledge about the soft processor's internals, our framework can capture execution traces up to 60x more space-efficient than traditional embedded logic analyzers.

关键词： Program processors Debugging Hardware Instruments field programmable gate arrays Tools Radiation detectors

来源：评论

学校读者我要写书评

暂无评论

Time-borrowing platform in the Xilinx UltraScale+ family of FPGAs and MPSoCs 26

Time-borrowing platform in the Xilinx UltraScale+ family of ...

引用

26th international conference on field-programmable logic and applications, FPL 2016

作者： Ganusov, Ilya Devlin, Benjamin Xilinx Inc. 2100 Logic Drive San JoseCA95124-3400 United States

ISBN: (纸本)9782839918442

this paper presents enhancements to the Xilinx UltraScale+ clocking architecture to support fine-grain time-borrowing. Time borrowing improves performance by redistributing timing slack between fast and slow paths. the Ultra-Scale+ architecture introduces programmable hardware delays and pulse generators embedded in the clocking tree to support time-borrowing based both on clock skew scheduling and pulsed latches. this programmable hardware allows borrowing from a few picoseconds to multiple nanoseconds between sequential pipeline stages without any changes to RTL, placement or routing. Vivado algorithms automatically determine when to skew flip-flop clock or convert them to pulsed latches to achieve the highest possible performance. Using the default Vivado flow, this programmable time-borrowing platform delivers 5.5% Fmax increase on average over a suite of 89 industrial designs. It is especially effective on high-speed applications, delivering up to 13.7% Fmax increase on individual designs. We also demonstrate that using non-default features, such as delays cascades or increasing hold margin, can increase average performance gains to 7.4% and 8.5%, respectively. this platform incurs minimum area (less than 0.1% of total chip area) while staying robust in the presence of tight hold constraints and increasing process variation. © 2016 EPFL.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

A directly triggered asynchronous SAR logic with variable delay unit 13

A directly triggered asynchronous SAR Logic with variable de...

引用

2016 13th IEEE international conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Rong-Tao Liao Rui Guan Ting-Ting Mo Center for Analog/RF Integrated Circuit （CARFIC）School of Microelectronics Shanghai Jiaotong University

ISBN: (纸本)9781467397209

this paper presents a directly triggered asynchronous successive approximation register（SAR） logic with variable delay unit. With the help of the designed logic,the CDAC can be settled directly by the comparator result that avoids long propagation delay as conventional SAR logic does. Moreover, a variable delay unit is designed which provides more settling time to the last several bits to get more reliable result. Simulation result in TSMC 0.18 um process shows the delay is only 170 ps which is much better than the conventional architecture.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

Utilizing 3D ICs in Architectures for Neural Networks 13

Utilizing 3D ICs in Architectures for Neural Networks

引用

2016 13th IEEE international conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Qiaosha Zou Yuan Xie Department of Computer Technologies Zhejiang University of Science and Technology Department of Electrical and Computer Engineering University of California

ISBN: (纸本)9781467397209

the emerging applications is the dominant factor that drives the evolvement of computer technologies and architectures. Among the emerging applications these days, neural networks are the most attention-grabbing one To unleash the benefits of neural network, the architecture optimization is a necessity. In this paper, the architecture requirements of neural network is first reviewed. then based on these requirements, how to utilize 3D IC techniques to design emerging architectures is given with the introduction of state-of-art studies.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

Model Checking Reconfigurable Petri Nets with Maude 9th

引用

9th international conference on Graph Transformation in Memory of Hartmut Ehrig (ICGT) held as part of conference on Software Technologies - applications and Foundations (STAF)

作者： Padberg, Julia Schulz, Alexander Hamburg Univ Appl Sci Hamburg Germany

ISBN: (纸本)9783319405308;9783319405292

Model checking is a widely used technique to prove properties such as liveness, deadlock or safety for a given model. Here we introduce model checking of reconfigurable Petri nets. these are Petri nets with a set of rules for changing the net dynamically. We obtain model checking by converting reconfigurable Petri nets to specific Maude modules and using then the LTLR model checker of Maude. the main result of this paper is the correctness of this conversion. We show that the corresponding labelled transitions systems are bisimular. In an ongoing example reconfigurable Petri nets are used to model and to verify partial dynamic reconfiguration of field programmable gate arrays.

关键词： Reconfigurable Petri nets Rewrite logic Maude Model checking field programmable gate array Dynamic partial reconfiguration

来源：评论

学校读者我要写书评

暂无评论

Design and Application of Resistive Switching Devices for Novel Computing/Memory Architectures 13

Design and Application of Resistive Switching Devices for No...

引用

2016 13th IEEE international conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Jinfeng Kang Peng Huang Haitong Li Bin Gao Yudi Zhao Runze Han Zheng Zhou Zhe Chen Chen Liu Lifeng Liu Xiaoyan Liu Institute of Microelectronics Peking University Institute of Microelectronics Tsinghua University

ISBN: (纸本)9781467397209

Oxide-based resistive random access memory（RRAM） has been widely studied as the promising candidate for the applications of next generations of data storage and computing technologies. In this paper, we will discuss the physical mechanism and optimization design of oxide-based RRAM devices, the novel RRAM-based computing/memory unifying architectures and the applications for data storage and computing technologies.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

Optimization of InSb QWFET layer structure for high-speed and low power nano electronics applications

Optimization of InSb QWFET layer structure for high-speed an...

引用

international conference on Advances in Electrical Engineering (ICAEE)

作者： S.S. Mahtab M.J. Alam A.M. Khan Z. Uddm A.A. Mamun M.M. Uddin Department of Electrical and Electronic Engineering Feni University Feni Bangladesh Department of Physics Chittagong University of Engineering and Technology Chittagong Bangladesh

the parameters of InSb quantum well field effect transistor (QWFET) layer structure such as spacer layer, barrier layer, quantum well (QW) thickness and doping density in the barrier layer have been revealed using self-consistence quantum corrected Schrödinger Poisson (QCSP) solution. the optimized value of the spacer and barrier layer of the InSb QWFET are found to be 25 and 45 nm, respectively. the quantum well thickness and doping density in the barrier layer of the InSb QWFET have also been optimized 20 nm and 1 × 10 12 cm -2 respectively. the results are employed in the proposed structure and an optimized InSb QWFET has then been calculated at room temperature with a very high electron mobility 3.27 m 2 V -1 s -1 and density 2.36 × 10 15 m -2 at gate voltage, Vg = 0V. the two dimensional electron gas (2DEG) in the 20 nm QW is completely depleted by a very small V g = -0.47 V (pinch-off voltage V p ). the optimized InSb layer structure has significant implications for realizing InSb-based high-speed and low power depletion-mode QWFET for nanoelectronics applications.

关键词： Electron mobility Doping Transistors Optimization Silicon logic gates Mathematical model

来源：评论

学校读者我要写书评

暂无评论

DESIGN AND SIMULATION TOOLS FOR EMBEDDED NOCS ON FPGAS 25

DESIGN AND SIMULATION TOOLS FOR EMBEDDED NOCS ON FPGAS

引用

25th international conference on field programmable logic and applications

作者： Abdelfattah, Mohamed S. Bitar, Andrew Yaghi, Ange Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

We propose embedding hard NoCs on FPGAs to improve system-level communication as detailed in our previous studies [1-6]. this demo paper outlines the three main design and simulation tools that we have been using to e... 详细信息

ISBN: (纸本)9781467381239

关键词： simulation tool field programmable gate arrays embedding

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共185页 << < 53 54 55 56 57 58 59 60 61 62 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：