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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1846 条记录，以下是51-60 订阅

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FORC: A High-throughput Streaming FPGA Accelerator for Optimized Row Columnar File Decoders in Big Data Engines

FORC: A High-Throughput Streaming FPGA Accelerator for Optim...

引用

international conference on field programmable logic and applications

作者： Abdul Wadood Alec Lu Ken Zhang Zhenman Fang Simon Fraser University Burnaby BC Canada Huawei Canada Markham ON Canada

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

To improve the file storage efficiency of large datasets, big data analytics usually use some common file formats, such as Apache ORC (optimized row columnar) format, to encode and compress the data. However, this shifts the IO bottleneck (especially with high-bandwidth SSDs) to the computation bottleneck on CPUs to decompress and decode the data. this paper presents FORC, a high-throughput streaming-based FPGA accelerator overlay that supports different ORC file format decoders, and its dataflow integration with Apache ORC. Experimental results show that FORC achieves up to $12.9 \mathrm{~GB} / \mathrm{s}$ decoding throughput on AMD/Xilinx Alveo U280 FPGA, with a geomean speedup of 65x (up to 335x) over the CPU. FORC will be released soon at https://***/SFU-HiAccel/FORC.

关键词： Big Data throughput Decoding logic field programmable gate arrays Engines

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Design and Optimization of an MCU-based controller implementing field-Oriented-Control of a BLDC motor

Design and Optimization of an MCU-based controller implement...

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thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems EuroSimE

作者： Nicola Romano Mauro Canigliula Giuseppe D’Angelo STMicroelectronics Viale Remo De Feo 1 Arzano (NA) Italy

Brushless DC (BLDC) motors are widely used in many applications including automotive ones and the field Oriented Control (FOC) is the control algorithm used for these motors and, in general, it is implemented by a programmable Micro Controller Unit (MCU). the control parameters must be well tuned and the model-based design, using simulation platforms, gives the possibility to study the behavior of a system under several conditions, observing the outputs, and tuning the system’s parameters without interacting with the real one. this, combined with the automatic code generation capabilities of some simulation platforms, makes it possible to automatically convert the model or part of it into integrable standard C code. this paper presents a simulation-based optimization by the MATLAB/Simulink platform of the PIDs’ parameters of an existing FOC Software Library for a brushless motor, the automatic code generation, and the integration of the generated code in the existing library. the simulation and experimental results show that the speed ripple is reduced from ± 8% of the target speed to ± 4% and demonstrate the effectiveness of the proposed simulation-based optimization approach.

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Techniques for Exploring Fine-Grained LUT and Routing Aging on a 28nm FPGA

Techniques for Exploring Fine-Grained LUT and Routing Aging ...

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international conference on field programmable logic and applications

作者： Hayden Cook Jeffrey Goeders Department of Electrical and Computer Engineering Brigham Young University Provo Utah USA

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Understanding how FPGAs age and how to control that aging is crucial for ensuring the reliability and security of FPGAs in critical applications. Due to the proprietary nature of commercial FPGAs, it can be challenging to validate aging models on real silicon, and most previous work has relied on circuit simulations to study the effects of FPGA aging. In this work, we leverage low-level placement and routing APIs provided by RapidWright to create a series of stressor and characterization circuits that allow us to measure the effects of aging on individual LUTs and routing resources in a 28nm FPGA. We demonstrate how these techniques allow fine-grained control of the relative aging of different FPGA resources, even to the point of aging individual paths within a single LUT. Several different aging experiments are demonstrated, and in a cumulative test, we show how different signal and LUT configurations can influence the aging rate by over 2x.

关键词： Prevention and mitigation Aging Routing Silicon Table lookup Security logic Integrated circuit reliability field programmable gate arrays Stress measurement

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Efficient Design Space Exploration for Dynamic & Speculative High-Level Synthesis

Efficient Design Space Exploration for Dynamic & Speculative...

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international conference on field programmable logic and applications

作者： Dylan Leothaud Jean-Michel Gorius Simon Rokicki Steven Derrien CNRS IRISA Univ Rennes Inria

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

High-Level Synthesis performs well for compute-intensive loops with regular control but struggles to uncover parallelism in kernels with complex control-flow. Novel scheduling techniques based on dynamic scheduling and speculation have been proposed to address this issue. Although they outperform classical static scheduling techniques, they also come at a significant area overhead. Precisely determining where and by how much to apply these techniques remains an open problem, which we address in this work through an efficient exploration algorithm (combining pruning and search heuristics). We show that our approach can explore large solution spaces while producing efficient solutions.

关键词： Processor scheduling Heuristic algorithms Static analysis Aerospace electronics Parallel processing Dynamic scheduling Search problems Space exploration logic Kernel

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Design of Highly Reliable Fault Backtracking Calculation for Space applications 15

Design of Highly Reliable Fault Backtracking Calculation for...

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15th international conference on Computer Research and Development, ICCRD 2023

作者： Yu, Jiyang Huang, Dan Li, Jinyang Li, Wenjie Wang, Xianjie Shi, Xiaolong China Academy of Space Technology Beijing Institute of Spacecraft System Engineering Beijing China China Research and Development Academy of Machinery Equipment Beijing Chongqing China Chongqing University of Technology Chongqing Beijing China Chongqing Feima Innovation Research Institute Intelligent Equipment Research Department Chongqing China College of Computer Science and Engineering Chongqing University of Technology Chongqing China

ISBN: (纸本)9781665487504

the design architecture of backtracking calculation control processing for space large manipulator control is proposed. SRAM-Type FPGA is used to build the hardware full three-mode computing core, and the processor architecture is designed based on FPGA. the register value and cache access value of the single instruction calculation process of the three computing processors are used to compare the three modes in the anti-fuse FPGA. At the same time, the results of three computing processors were compared by SPARC CPU. Fault backtracking calculation control, when a single computing module occurs an error, first detect the instruction execution position of the faulty module, and then carry out register-level data recovery for the faulty module, and restore to the instruction before the fault to accelerate the operation to complete the 'backtracking' process, until the other two modules complete the calculation synchronization. According to the theoretical derivation and analysis, it is clear that under the linear increasing detection window, the maximum time of fault recovery is only related to the three-mode ratio transmission rate. According to this conclusion, the hardware digital logic design of the key modules of fault detection and recovery is carried out. the overall structure is simple and easy to implement, digital logic only occupies less than 100,000 logic gates. Compared with traditional methods, the fault recovery efficiency is improved by at least 90%. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs

StencilStream: A SYCL-based Stencil Simulation Framework Tar...

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international conference on field programmable logic and applications

作者： Jan-Oliver Opdenhövel Christoph Alt Christian Plessl Tobias Kenter Department of Computer Science Paderborn Center for Parallel Computing Paderborn University Friedrich Alexander Universität Erlangen

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Although High-Level Synthesis has dramatically improved the usability of FPGAs in High-Performance Computing applications, it still requires much experience to create well-performing FPGA designs. We introduce the stencil simulation framework StencilStream to separate the concerns of performance engineers and domain scientists. We have formulated our performance-oriented stencil simulation designs for FPGAs along with their management code as C++ templates using SYCL language features. Application developers instantiate these templates with their concrete stencil code and obtain a complete application with little management overhead. In this work, we describe the most interesting API features and the two backend architectures of StencilStream, along with their corresponding performance models. We then evaluate the performance of the architectures using three manually implemented sample applications and highlight the real-world usability of StencilStream further with shallow water simulations obtained from a code-generation flow. Compiled with Intel oneAPI for an Intel Stratix 10 GX 2800 target FPGA, the best-performing sample design exceeds a throughput of 1 TFLOPS.

关键词： Productivity Codes High performance computing Graphics processing units Computer architecture throughput logic Usability field programmable gate arrays Engines

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Meta-Heuristic Optimization of Custom Heterogeneous Blocks Defined eFPGA Design

Meta-Heuristic Optimization of Custom Heterogeneous Blocks D...

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international conference on VLSI Design

作者： D V Bhargav G Pradyumna Madhav Rao IIIT Bangalore

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Modern field-programmable Gate Arrays (FPGAs) are highly versatile, with reconfigurable logic functionality that allows designers to create custom designs. Unlike traditional fixed-function integrated circuits, FPGAs are reconfigured multiple times to perform different tasks, making them ideal for various applications. An Embedded FPGA (eFPGA) takes the concept of an FPGA and integrates it as an IP core within a larger System-on-Chip (SoC) or Application-Specific Integrated Circuit (ASIC). the proposed work employs Non-dominated Sorting Genetic Algorithm-II (NSGA-II) to evolve efficient and high-performing eFPGA architectures with reduced critical path delay and power defined by a sufficient number of Configurable logic Blocks (CLBs), custom Digital Signal Processors (DSPs) and Block RAM (BRAMs) for targetting workload under consideration. As a result, this work presents a well-balanced eFPGA architecture layout obtained for four workloads equipped with different numbers of heterogeneous and configurable logic blocks. the results showed a significant improvement of 44.62% in hardware parameters.

关键词： Layout Metaheuristics Digital signal processors Signal processing algorithms Computer architecture Silicon Fabrics logic IP networks field programmable gate arrays

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FlexWalker: An Efficient Multi-Objective Design Space Exploration Framework for HLS Design

FlexWalker: An Efficient Multi-Objective Design Space Explor...

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international conference on field programmable logic and applications

作者： Zheyuan Zou Cheng Tang Lei Gong Chao Wang Xuehai Zhou School of Computer Science and Technology University of Science and Technology of China School of Software Engineering University of Science and Technology of China

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

the HLS toolchain effectively reduces the design complexity of FPGA hardware accelerators. However, in scenarios involving the multi-objective optimization of large-scale HLS designs, determining the knob configurations of Pareto design points remains a challenging task for designers. Our work re-evaluates the key factors affecting the efficiency of multiobjective design space exploration in HLS design and proposes an efficient framework named FlexWalker. It utilizes the upper confidence bound algorithm to organize various heterogeneous regression models for predicting the quality of HLS designs with different knob configurations in the design space and introduces a probability sampling algorithm and an elastic Pareto frontier to counteract the negative impact of regression model errors. Experimental results show that our work can stably eliminate over 90% of non-Pareto frontier design points in the tested HLS design space, effectively enhancing the efficiency of multiobjective design space exploration.

关键词： Predictive models Prediction algorithms Space exploration Complexity theory logic Optimization Hardware acceleration field programmable gate arrays

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A Hardware Efficient Real-time Video processing on FPGA with OV 7670 camera interface and VGA 6

A Hardware Efficient Real-time Video processing on FPGA with...

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6th international conference on Electronics, Communication and Aerospace Technology, ICECA 2022

作者： Navaneethan, S. thanusha, Chenimineni Varshini, M. Amirdha Anil, Ankireddygari Saveetha Engineering College Dept. of Ece Chennai India

ISBN: (纸本)9781665482714

the aim of this work is to develop a video processing system with efficient hardware resource using a field programmable gate array (FPGA). the FPGA board contains several resources that may be implemented on both hardware and software platforms. Real-time video processing necessitates high-consuming logic resources, and fpga is an excellent choice for video processing applications. In this work, Omni vision (OV) 7670 and Video graphics array (VGA) interfaces with FPGA for video processing system. the tools utilized here are Xilinx Vivado and Verilog HDL to develop the system. the proposed video processing system implemented in Spartan 6 &Artix -7 FPGA which provides 530 slice registers. © 2022 IEEE.

关键词： field programmable gate arrays (FPGA)

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A Heterogeneous Acceleration System for Attention-Based Multi-Agent Reinforcement Learning

A Heterogeneous Acceleration System for Attention-Based Mult...

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international conference on field programmable logic and applications

作者： Samuel Wiggins Yuan Meng Mahesh A. Iyer Viktor Prasanna Ming Hsieh Department of Electrical and Computer Engineering University of Southern California Intel Corporation

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Multi-Agent Reinforcement Learning (MARL) is an emerging technology that has seen success in many AI applications. Multi-Actor-Attention-Critic (MAAC) is a state-of-the-art MARL algorithm that uses a Multi-Head Attention (MHA) mechanism to learn messages communicated among agents during the training process. Current implementations of MAAC using CPU and CPU-GPU platforms lack fine-grained parallelism among agents, sequentially executing each stage of the training loop, and their performance suffers from costly data movement involved in MHA communication learning. In this work, we develop the first high-throughput accelerator for MARL with attention-based communication on a CPU-FPGA heterogeneous system. We alleviate the limitations of existing implementations through a combination of data- and pipeline-parallel modules in our accelerator design and enable fine-grained system scheduling for exploiting concurrency among heterogeneous resources. Our design increases the overall system throughput by $4.6 \times$ and $4.1 \times$ compared to CPU and CPU-GPU implementations, respectively.

关键词： Training Concurrent computing Scheduling algorithms Reinforcement learning Computer architecture Parallel processing throughput logic field programmable gate arrays Multi-agent systems

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