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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1847 条记录，以下是591-600 订阅

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Exploring the use of shift register lookup tables for Keccak implementations on Xilinx FPGAs

Exploring the use of shift register lookup tables for Keccak...

引用

international conference on field programmable logic and applications

作者： Jori Winderickx Joan Daemen Nele Mentens KU Leuven ESAT/COSIC & iMinds Leuven Belgium STMicroelectronics Belgium Radboud University Nijmegen Netherlands

We explore the possibility of using shift register lookup tables (SRLs) for the implementation of Keccak on Xilinx FPGAs. the approach originates from the observation that the ρ step in combination with the state storage can be implemented as a collection of shift registers. this way, we achieve a slice-wise implementation using 25 shift registers of various lengths, resulting in 75 32-bit and 6 16-bit SRL primitives on a Virtex-5. this approach, however, does not comply efficiently with the common interface of Keccak. We therefore propose to utilize a modified interface in order to avoid the redundant storage of the state. this modified version of Keccak, with equivalent cryptographic strength, can be implemented without Block RAM, outperforming all previously proposed implementations in terms of the number of slices. Furthermore it outperforms several other lightweight slice-wise implementations in terms of throughput.

关键词： Shift registers Computer architecture field programmable gate arrays Clocks Random access memory throughput

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Characterisation of Feasibility Regions in FPGAs under Adaptive DVFS 25

Characterisation of Feasibility Regions in FPGAs under Adapt...

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25th international conference on field programmable logic and applications

作者： Dahir, Nizar Campos, Pedro Tempesti, Gianluca Trefzer, Martin Tyrrell, Andrew Univ York Dept Elect York YO10 5DD N Yorkshire England

ISBN: (纸本)9781467381239

Implementing Dynamic Voltage and Frequency Scaling (DVFS) is a non-trivial task on FPGAs and requires knowledge about the feasible voltage and frequency (VF) ranges as a first step. the VF feasible ranges depend not only on the size of the critical path in the design but also on the inter-and intra-die variability on the FPGA die. Moreover, the variations in the configuration of the FPGA highly affect feasible VF ranges. therefore, it is crucial to characterise feasibility by studying the relationship between feasible VF regions and these sources of variability in FPGAs. In this paper we employ a self-checking multiplier which uses residue codes and DVFS implemented on the programmable logic component of a Xilinx Zynq ZC702 device as an error-detection circuit to study these feasible regions. Results show that, as expected, feasible VF ranges vary with FPGA configuration. More interestingly, significant variation of the feasible VF regions is found for different dies. these results highlight the necessity of dynamic self-testing as a part of an adaptive DVFS implementation on FPGAs. Employing the techniques presented in this work enables the implementation of efficient adaptive on-line DVFS on programmable logic while ensuring reliability.

关键词： field programmable gate arrays residue codes Self tuning Multiplying circuits programmable dies

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Reconfigurable circuit for implementation of family of 4-phase latch protocols

Reconfigurable circuit for implementation of family of 4-pha...

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international conference on field programmable logic and applications

作者： Jotham Vaddaboina Manoranjan Kenneth S. Stevens Department of Electrical and Computer Engineering University of Utah

this paper presents a novel reconfigurable circuit capable of implementing the entire family of 4-phase latch protocols. the architecture utilizes look-up-table based reconfigurable logic structures and fixed signal paths. the implemented circuit creates a fabric to realize a variety of high speed and low power controllers for asynchronous circuits on FPGAs. the circuit is implemented on the IBM Artisan 65nm node and its performance is compared with implementations on a Xilinx Virtex-5 chip that is manufactured on a similar node. A 4× improvement in speed and 3.3× improvement in energy per cycle is achieved.

关键词： Protocols field programmable gate arrays Table lookup Latches Routing Hazards Fabrics

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Towards an all-digital antenna array transmitter

Towards an all-digital antenna array transmitter

引用

international conference on field programmable logic and applications

作者： Daniel C. Dinis R. F. Cordeiro Arnaldo S. R. Oliveira José Vieira Departamento de Electrónica Universidade de Aveiro Campus Universitário de Santiago Aveiro Portugal

this PhD work presents a potential architecture and implementation for an FPGA-based all digital antenna array transmitter for wireless radio communications. By enabling the design of antenna arrays without external Digital-to-Analog Converters (DACs), external upconversion stages and without complex layouts, the analog front-end can be summed up to just amplification, filtering and radiation.

关键词： Antenna arrays Radio transmitters Transmitting antennas Modulation field programmable gate arrays Radio frequency

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Multi-core for K-means clustering on FPGA

Multi-core for K-means clustering on FPGA

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international conference on field programmable logic and applications

作者： José Canilho Mário Véstias Horácio Neto INESC-ID Universidade de Lisboa Portugal INESC-ID Instituto Politécnico de Lisboa

In this paper, a configurable many-core hardware/software architecture is proposed to efficiently execute the widely known and commonly used K-means clustering algorithm. A prototype was designed and implemented on a Xilinx Zynq-7000 All programmable SoC. A single core configured with the slowest configuration achieves a 10× speed-up compared to the software only solution. the system is fully scalable and capable of achieving much higher speed-ups by increasing its parallelism.

关键词： Hardware Clustering algorithms Computer architecture field programmable gate arrays Algorithm design and analysis Measurement Parallel processing

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A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs 25

A portable open-source controller for safe Dynamic Partial R...

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25th international conference on field programmable logic and applications

作者： Di Carlo, Stefano Prinetto, Paolo Trotta, Pascal Andersson, Jan Politecn Torino Dip Automat & Informat Turin Italy Cobham Gaisler AB Gothenburg Sweden

ISBN: (纸本)9781467381239

thanks to their flexibility, increasing performances and low Non-Recurrent Engineering costs, SRAM-based field programmable Gate Array (FPGA) devices often represent the preferred platforms for the final deployment of highly reliable systems. In this context, Dynamic Partial Reconfiguration (DPR) is far from being widely adopted due to the additional complexity introduced during the hardware design phase, and the dependability issues related to the FPGA reconfiguration process itself. this paper presents a portable open-source controller for safely enabling self dynamic and partial reconfiguration of systems implemented on Xilinx FPGAs. the controller embeds configurable error detection and correction circuitry that enables a safe DPR by monitoring for partial bitstreams data errors. Experiments highlight the high performances achieved and the limited hardware resources needed to implement it on different devices. the HDL source code has been made available through the popular open-source Cobham Gaisler GRLIB IP-cores library.(1)

关键词： hardware resource Reconfiguration field programmable gate arrays open source HIGH-PERFORMANCE Controllers error detection and correction dial pulse receiver

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Enabling Seamless Execution on Hybrid CPU/FPGA Systems: Challenges & Directions 25

Enabling Seamless Execution on Hybrid CPU/FPGA Systems: Chal...

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25th international conference on field programmable logic and applications

作者： Belwal, Meena Purnaprajna, Madhura Sudarshan, T. S. B. Amrita Vishwavidya Peetham Amrita Univ Amrita Sch Engn Dept Comp Sci & Engn Bangalore Karnataka India

ISBN: (纸本)9781467381239

Today's computing systems are heterogeneous, with diverse micro-architectures. It is common to design systems comprising multi-core CPUs, Digital Signal Processors (DSP) and Graphic Processing Units (GPUs). In addition to these devices, the extensive configurability and parallelism in field programmable Gate Arrays (FPGAs) has proven to be advantageous for accelerating complex computational problems. In comparison to CPUs, DSPs and GPUs, FPGAs have a distinctly different microarchitecture. In this context, enabling seamless application execution in a system composed of FPGAs alongside CPUs, is a major challenge. As a consequence, simplifying programmability of hybrid CPU/FPGA systems demands innovations in system software support. there has been research in extending the traditional CPU-only system techniques to CPU/FPGA based hybrid systems to make way for FPGA-based mainstream computing. this article surveys techniques in dynamic task management aimed at reducing or completely eliminating the burden of operating system writers for CPU/FPGA hybrid systems and provide insight to researchers to explore further.

关键词： central processing units field programmable gate arrays hybrid systems task processing Systems software parallelism Technological Innovations Legal Executions Enabling Insight

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Estimating Circuit Delays in FPGAs after Technology Mapping 25

Estimating Circuit Delays in FPGAs after Technology Mapping

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25th international conference on field programmable logic and applications

作者： Severens, Berg Vansteenkiste, Elias Heyse, Karel Stroobandt, Dirk Univ Ghent Dept Elect & Informat Syst Comp Syst Lab Hardware & Embedded Syst Team B-9000 Ghent Belgium

ISBN: (纸本)9781467381239

An FPGA implementation requires a significant effort of the hardware designer, who optimizes FPGA designs by going through many time-consuming CAD flow iterations. these iterations provide two types of feedback: (1) the FPGA performance and (2) the identification of the parts having the highest impact on the FPGA performance. Both depend on the wirelength behavior. Studies have been dedicated to the estimation of local [5] and global [4] wirelengths, but to our knowledge both performance estimations and identification of the critical zone are not present in literature. therefore this paper, firstly, presents a comparison of three performance estimation techniques: logic depth, Monte Carlo simulation and fast placement (ordered from low to high accuracy and runtime). Secondly, four methods identifying the critical zone are compared. Results show that Monte Carlo simulations provide a good identification of the parts having the highest impact on the performance. We conclude that Monte Carlo simulations provide useful feedback within a short runtime (about 30 times faster than placement), reducing the time-tomarket of FPGA implementations.

关键词： field programmable gate arrays critical zone Monte Carlo technique Performance Evaluation Runtime placement HIGH IMPACT iterative methods IMPACT PROPERTIES

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Accurate Power Analysis for Near-V_t RRAM-based FPGA 25

Accurate Power Analysis for Near-<i>V<sub>t</sub></i> RRAM-b...

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25th international conference on field programmable logic and applications

作者： Tang, Xifan Gaillardon, Pierre-Emmanuel De Micheli, Giovanni Ecole Polytech Fed Lausanne Lausanne Switzerland

ISBN: (纸本)9781467381239

Resistive Random Access Memory (RRAM)-based FPGA architectures employ RRAMs not only as memories to store the configuration but embed them in the datapaths of programmable routing resources to propagate signals with improved performances. Sources of power consumption have been intensively studied for conventional Static Random Access Memories (SRAM)-based FPGAs. However, very limited works focused so far on studying the power characteristics of RRAM-based FPGAs. In this paper, we first analyze the power characteristics of RRAM-based multiplexer at circuit level and then use electrical simulations to study power consumption of RRAM-based FPGA architectures. Experimental results show that RRAM-based FPGAs achieve a Power-Delay Product reduced by 50% compared to SRAM-based FPGA at nominal voltage and 20% compared to near-V-t SRAM-based FPGA, respectively.

关键词： field programmable gate arrays (FPGA)

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Static Hardware Task Placement on Multi-Context FPGA Using Hybrid Genetic Algorithm 25

Static Hardware Task Placement on Multi-Context FPGA Using H...

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25th international conference on field programmable logic and applications

作者： Liang, Hao Sinha, Sharad Warrier, Rakesh Zhang, Wei Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Hong Kong Peoples R China Nanyang Technol Univ Sch Comp Engn Singapore Singapore

ISBN: (纸本)9781467381239

field programmable Gate Arrays (FPGAs) are becoming pervasive in various kinds of computationally demanding applications. Working in a tightly coupled processor-coprocessor architecture, FPGAs are often anticipated to accelerate multiple fine-grained or coarse-grained tasks simultaneously. Single-context FPGAs are commonly used in such systems. With the recent development of emerging memory technologies, multicontext FPGAs that support dynamic reconfiguration with high-density non-volatile memories become feasible. Compared to single-context FPGAs, multi-context FPGAs are able to accelerate significantly more tasks with only moderate area and power overhead. However, the best way to utilize the computation capacity advantage of multi-context FPGAs for hardware task mapping remains an interesting and unexploited problem. In this paper, we first propose the framework of a processor-coprocessor architecture with multi-context FPGA as the coprocessor for multiple-task acceleration. Under the framework, a hybrid placement strategy based on genetic and greedy algorithms is proposed to efficiently place a set of tasks onto the multi-context FPGA to achieve the best logic capacity utilization. Experiments on real and synthetic benchmarks demonstrate the efficiency of the proposed algorithm compared with other general approaches.

关键词： field programmable gate arrays (FPGA)

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