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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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Semi-dense SLAM on an FPGA SoC

Semi-dense SLAM on an FPGA SoC

引用

international conference on field programmable logic and applications

作者： Konstantinos Boikos Christos-Savvas Bouganis Department of Electrical and Electronic Engineering Imperial College London

Deploying advanced Simultaneous Localisation and Mapping, or SLAM, algorithms in autonomous low-power robotics will enable emerging new applications which require an accurate and information rich reconstruction of the environment. this has not been achieved so far because accuracy and dense 3D reconstruction come with a high computational complexity. this paper discusses custom hardware design on a novel platform for embedded SLAM, an FPGA-SoC, combining an embedded CPU and programmable logic on the same chip. the use of programmable logic, tightly integrated with an efficient multicore embedded CPU stands to provide an effective solution to this problem. In this work an average framerate of more than 4 frames/second for a resolution of 320×240 has been achieved with an estimated power of less than 1 Watt for the custom hardware. In comparison to the software-only version, running on a dual-core ARM processor, an acceleration of 2× has been achieved for LSD-SLAM, without any compromise in the quality of the result.

关键词： Simultaneous localization and mapping field programmable gate arrays Hardware Optimization Software Jacobian matrices

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An XDL alternative for interfacing RapidSmith and Vivado

An XDL alternative for interfacing RapidSmith and Vivado

引用

international conference on field programmable logic and applications

作者： thomas Townsend Brent Nelson Mike Wirthlin Dept. of Electrical and Computer Engineering Brigham Young University Provo UT USA

In recent years, the RapidSmith CAD tool [1] has been used with ISE to create custom CAD tools targeting Xilinx FPGAs. this tool flow was based on the Xilinx Design Language (XDL), a human-readable representation of a netlist that contains placement and routing information. the XDL interface also provided device representation files (XDLRC files), detailing the available resources of a given FPGA part. Using RapidSmith, a Xilinx design could be exported out of ISE at any stage of the design flow, manipulated in RapidSmith (logic modification, place, or route), and imported back into ISE to complete the remainder of implementation.

关键词： field programmable gate arrays Routing Wires Computers Electronic mail Performance evaluation Hardware

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ASIC-based Gauss Error Function Module Design for Neural Network Application 13

ASIC-based Gauss Error Function Module Design for Neural Net...

引用

2016 13th IEEE international conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Zhi-Tong Qiao Yan Han Jian Lei R.C.C.Cheung Will X.Y.Li Hiao-Xia Han Institute of Microelectronics and Nanoelectronics Zhejiang University Department of Electronic Engineering City University of Hong Kong School of Computer and Engineering Nanjing University of Science and Technology

ISBN: (纸本)9781467397209

the first ASIC-based Gauss error function(GEF module is proposed and fabricated in SMIC 180-nm process in this paper. A novel method is proposed to be used in the design. Experimental results show tha compared with the design based on Taylor expansion method, the proposed design decreases the absolute erro by 99.21%, reduces the area by 77.21% and reduces the delay by 11.96%. It can be used as a Soft Intellectua Property（IP） Core or Digital Signal Processor（DSP） to be easily applied to all kinds of Neural Network applications. the design proposed and the corresponding design and optimization methods can promote the research and development of the implantable neura prosthesis bio-chip and neural network.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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An Area-Efficient Low-Noise Bio-Sensing Amplifier with Continuous-Tunable Gain 13

An Area-Efficient Low-Noise Bio-Sensing Amplifier with Conti...

引用

2016 13th IEEE international conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Tao Yin Guocheng Huang Xiaodong Xu Yachao Zhang Xinxia Cai Haigang Yang Institute of Electronics Chinese Academy of Sciences University of the Chinese Academy of Sciences

ISBN: (纸本)9781467397209

this paper presents a low-power area-efficient instrumentation amplifier(IA) for biopotential *** proposed IA adopts a resistor-controlled- oscillator(RCO) to change the mid-band gain of the readout circuit for different biomedical applications. the switched-capacitor load of the IA changes with RCO’s output frequency, making the gain of IA continuous tunable. Measurement results show that the input referred noise of proposed IA is about 1.2μVRMS(BW=150Hz) and the NEF is 3.75. the range of tunable gain is from 22 to 35 dB. And the measured CMRR and PSRR at 50 Hz are larger than 70 d B. the power consumption of the IA is 790 nW at 1.2V supply. the active area of the IA is 0.035mm.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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POWER-EFFICIENT RANGE-MATCH-BASED PACKET CLASSIFICATION ON FPGA 25

POWER-EFFICIENT RANGE-MATCH-BASED PACKET CLASSIFICATION ON F...

引用

25th international conference on field programmable logic and applications

作者： Qu, Yun R. Prasanna, Viktor K. Univ Southern Calif Ming Hsieh Dept Elect Engn Los Angeles CA 90089 USA

ISBN: (纸本)9781467381239

Packet classification is a kernel application performed at network routers. Many classification engines are optimized for prefix and exact match, while a range-to-prefix translation can lead to rule set expansion. Under limited power budget, it is challenging to achieve high classification throughput. In this paper, we present a high-performance and power-efficient packet classification engine on FPGA. We construct a modular Processing Element ( PE);each PE compares a stride of the input packet header against a stride of a range boundary. We concatenate multiple PEs into a systolic array. Efficient power optimization techniques including self-enabled power gating and entropy-based scheduling are explored on our architecture. Experimental results show that, for 4 K 15-field rule sets, our prototype on a state-of-the-art FPGA can achieve 250 Million Packets Per Second (MPPS) throughput. Using the proposed power optimization techniques, our classification engine consumes 30 % of the power without sacrificing the throughput.

关键词： packet classification field programmable gate arrays power budget Energy sources Engines throughput Power (Psychology)

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Recent progress of graphene-based nanoelectronic devices and NEMS for challenging applications 13

Recent progress of graphene-based nanoelectronic devices and...

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2016 13th IEEE international conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Hiroshi Mizuta Ahmed Hammam Jothiramalingam Kulothungan Shunei Suzuki Marek E.Schmidt Jian Sun Manoharan Muruganathan Energy and Environmental Research Division School of Materials Science Japan Advanced Institute of Science and Technology (JAIST) Nanoelectronics and Nanotechnologies Group ECS Faculty of Physical Sciences and Engineering Univ. of Southampton

ISBN: (纸本)9781467397209

Graphene possesses remarkable electronic and mechanical properties and provides a promising platform to explore future nanoelectronic and nano electro-mechanical（NEM） devices for challenging applications. this paper presents a brief overview of ou recent attempts of developing novel graphene-based nanoscale devices. We first present state-of-the-ar fabrication technology for sub-10-nm graphene nanostructures using atomic-size focused helium ion beam. Secondly graphene-based tunnel FETs(GTFETs are discussed, which are expected to achieve advanced switching characteristics in comparison with conventional MOSFETs. We then describe graphene NEM（GNEM） switches with low voltage switching operation and GNEM chemical gas sensors with single-molecular-level detection limit.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Overoptimistic Voltage Scaling in Pre-Error AVS Systems and Learning-Based Alleviation 29

Overoptimistic Voltage Scaling in Pre-Error AVS Systems and ...

引用

29th IEEE international System-on-Chip conference (SOCC)

作者： Ting, Yi-Hsuan Wang, Chih-Yang Chang, Yu-Sian Lin, Tay-Jyi Chang, Shih-Chieh Wang, Jinn-Shyan Natl Chung Cheng Univ CCU Dept Comp Sci & Informat Engn Minxiong Township Chiayi Taiwan Natl Tsing Hua Univ Dept Comp Sci Hsinchu Taiwan CCU SoC Ctr Minxiong Township Chiayi Taiwan CCU AIM HI Ctr Minxiong Township Chiayi Taiwan CCU Dept Elect Engn Minxiong Township Chiayi Taiwan

ISBN: (纸本)9781509013678

In-situ timing error detection and correction mechanisms (such as Razor) monitor the performance of actual datapaths, and are believed more resilient in adaptive voltage scaling (AVS) systems, especially when considering local variations. However, Razor has serious hold time problems, of which the overwhelming buffer padding makes it infeasible in advanced process technologies. Pre-error (or in-situ canary) detection was then proposed as an alternative. In addition, sophisticated error correction is no longer needed accordingly. the Markov chain model was proposed by independent researchers to design the pre-error AVS controller to explicitly trade quality for energy, where the input patterns are assumed to have a Gaussian delay distribution. For error-tolerant applications where few errors are acceptable, pre-error AVS is shown more efficient than Razor-based approaches. In this paper, a pre-error AVS system has been constructed on a 28nm FPGA platform with programmable power supply. It is observed that when the delay distributions are time-varying and non-Gaussian, overoptimistic voltage scaling (OVS) can occur and may lead to serious problems in pre-error AVS. To resolve the OVS problem, we propose to insert certain logics to collect the delay criticality information, which is fed into a Q-learning model to create the learning-based AVS. Experimental results show that the proposed scheme saves 10.50% power while reducing 0.16% error rate for random inputs and saves 12.51% power while reducing 0.06% error rate for non-random inputs, compared with the original pre-error AVS that assumes a static Gaussian delay distribution.

关键词： Delays field programmable gate arrays logic gates Markov processes Decoding Clocks

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An Efficient Reconfigurable Architecture by Characterizing Most Frequent logic Functions 25

An Efficient Reconfigurable Architecture by Characterizing M...

引用

25th international conference on field programmable logic and applications

作者： Ahmadpour, Iman Khaleghi, Behnam Asadi, Hossein Sharif Univ Technol Dept Comp Engn Tehran Iran

ISBN: (纸本)9781467381239

Generous flexibility of Look-Up Tables (LUTs) in implementing arbitrary functions comes with significant performance and area overheads compared with their Application-Specific Integrated Circuit (ASIC) equivalent. One approach to alleviate such overheads is to use less flexible logic elements capable to implement majority of logic functions. In this paper, we first investigate the most frequently used functions in standard benchmarks and then design a set of less-flexible but area-efficient logic cells, called Hard logics (HL). Since higher input functions have diverse classes, we leverage Shannon decomposition to break them into smaller ones to either reduce the HL design space complexity or attain asymmetric low input functions. A heterogeneous LUT-HL architecture and a mapping scheme are also proposed to attain maximum logic resource usage. Experimental results on MCNC benchmarks demonstrate that the proposed architecture reduces area-delay product by 13% and 36% as compared to LUT4 and LUT6 based FPGAs, respectively. Considering the same area budget, our proposed architecture improves performance by 17% and 2% as compared to LUT4 and LUT6 based FPGAs.

关键词： logic functions Formal logic Reconfigurable architectures application specific integrated circuits input function BENCHMARKS Building construction LIPC gene ARCHITECTURE hectolitre

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A Variable Length Hash Method for Faster Short Read Mapping on FPGA 25

A Variable Length Hash Method for Faster Short Read Mapping ...

引用

25th international conference on field programmable logic and applications

作者： Sogabe, Yoko Maruyama, Tsutomu Univ Tsukuba Syst & Informat Engn 1-1-1 Ten Nou Dai Tsukuba Ibaraki 3058573 Japan

ISBN: (纸本)9781467381239

Short read mapping is a process to align the short reads, which are fixed-length fragments of the target genome, to a given reference genome to identify the mutations in the target genome. Because of the rapid development of Next Generation Sequencing (NGS) technologies, faster short read mapping is required. In this paper, we propose a variable length hash method to further accelerate FPGA short read mapping systems. In the hash-based short read mapping algorithms, a fixed length sub-string of each short read, called seed, is used as the key. However, many different seeds are mapped into the same hash slots because of the high ununiformity of the human genome, and many fruitless key comparisons are performed. To equalize the slot size, we propose an optimized hash function that changes the bit masks adaptively. With this approach, it is possible to improve the performance of all FPGA short read mapping systems based on hash functions. the performance for the comparison in our FPGA system on a Xilinx XC7VX690T and XC6VLX240T can be improved two-times, and the total performance outperforms any existing FPGA systems.

关键词： field programmable gate arrays (FPGA)

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An LZ77-Style Bit-Level Compression for Trace Data Compaction 25

An LZ77-Style Bit-Level Compression for Trace Data Compactio...

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25th international conference on field programmable logic and applications

作者： Irrgang, Kai-Uwe Preusser, thomas B. Brandenburg Tech Univ Cottbus Senftenberg Inst Med Technol Cottbus Germany Tech Univ Dresden Inst Comp Engn Dresden Germany

ISBN: (纸本)9781467381239

Online tracing is a powerful technique for monitoring and debugging embedded processors. the amount of data produced by tracing is enormous. thus, an on-the-fly trace data reduction close by its source is extremely valuable. Trigger-driven filtering and a compressed trace representation are popular measures to take. While effective methods for the compression of branch target addresses in instruction traces are known, modern processors also produce extensive execution bit streams to log the execution of conditional instructions. this paper proposes an LZ77-style compressor for these bit streams. In contrast to classic implementations, it operates on the bit level. It is demonstrated that this compressor is effective even when using a small dictionary. this allows an implementation within an FPGA close by the source or even on the same chip as the trace source. It is also shown that the compressor can keep pace with practically relevant trace data sources.

关键词： Data compression Compressors Bit Level level compression Trace bit stream Legal Executions data reduction Data sources field programmable gate arrays PROCESSOR Binary digits instruction tracing compression

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