检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,813 篇 会议
29 篇 期刊文献
5 册 图书

馆藏范围

1,847 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,202 篇 工学
- 1,019 篇 计算机科学与技术...
- 707 篇 软件工程
- 388 篇 电气工程
- 186 篇 电子科学与技术（可...
- 62 篇 信息与通信工程
- 60 篇 控制科学与工程
- 26 篇 机械工程
- 26 篇 仪器科学与技术
- 25 篇 动力工程及工程热...
- 24 篇 建筑学
- 16 篇 土木工程
- 14 篇 生物工程
- 11 篇 核科学与技术
- 10 篇 材料科学与工程（可...
- 9 篇 光学工程
- 8 篇 生物医学工程（可授...
- 8 篇 安全科学与工程
- 6 篇 化学工程与技术
- 6 篇 交通运输工程
146 篇 理学
- 97 篇 数学
- 33 篇 物理学
- 16 篇 生物学
- 14 篇 系统科学
- 10 篇 统计学（可授理学、...
- 6 篇 化学
52 篇 管理学
- 39 篇 管理科学与工程(可...
- 17 篇 工商管理
- 15 篇 图书情报与档案管...
14 篇 法学
- 12 篇 社会学
9 篇 经济学
- 9 篇 应用经济学
8 篇 医学
6 篇 农学
4 篇 军事学
2 篇 教育学

主题

816 篇 field programmab...
670 篇 field programmab...
271 篇 hardware
154 篇 computer archite...
119 篇 logic gates
111 篇 table lookup
94 篇 clocks
83 篇 throughput
78 篇 random access me...
72 篇 routing
71 篇 acceleration
71 篇 software
66 篇 optimization
63 篇 kernel
61 篇 delays
52 篇 registers
52 篇 logic
49 篇 switches
46 篇 algorithm design...
45 篇 computational mo...

机构

15 篇 univ toronto dep...
9 篇 department of co...
9 篇 imperial coll lo...
8 篇 ecole polytech f...
7 篇 univ british col...
7 篇 school of comput...
7 篇 brigham young un...
7 篇 imperial coll lo...
7 篇 tokyo inst techn...
6 篇 univ tsukuba tsu...
6 篇 university of ch...
6 篇 department of el...
6 篇 univ warwick sch...
6 篇 xilinx inc san j...
5 篇 univ manchester ...
5 篇 department of el...
5 篇 univ toronto dep...
5 篇 swiss fed inst t...
5 篇 xilinx inc 2100 ...
5 篇 altera corp san ...

作者

33 篇 luk wayne
21 篇 maruyama tsutomu
16 篇 wayne luk
16 篇 koch dirk
12 篇 wilton steven j....
12 篇 betz vaughn
12 篇 ienne paolo
11 篇 fahmy suhaib a.
11 篇 cheung peter y. ...
10 篇 vaughn betz
9 篇 constantinides g...
8 篇 suhaib a. fahmy
8 篇 prasanna viktor ...
8 篇 chow paul
8 篇 glesner manfred
8 篇 amano hideharu
8 篇 akash kumar
7 篇 kapre nachiket
7 篇 alonso gustavo
7 篇 hutchings brad

语言

1,838 篇 英文
9 篇 其他

检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1847 条记录，以下是631-640 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Tunable transfer behaviors of single-layer WSe＿2 field effect transistors by hydrazine 13

Tunable transfer behaviors of single-layer WSe＿2 field effe...

引用

2016 13th IEEE international conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Mengxing Sun Dan Xie Yilin Sun Zhixin Li Jianlong Xu Ruixuan Dai Xian Li Cheng Zhang Changjiu Teng Pu Yang Institute of Microelectronics and Tsinghua National Laboratory for Information Science and Technology (TNList) Tsinghua University Institute of Functional Nano & Soft Materials (FUNSOM) Jiangsu Key Laboratory for Carbon-Based Functional Materials & Devices Soochow University

ISBN: (纸本)9781467397209

Polarity modulation of single-layer WSe2 field effect transistor is investigated by using hydrazine as a solution-processable and effective n-type dopant for WSe2. Compared to the intrinsic hole-dominant ambipolar behaviors, highly effective n-type doping characteristics are achieved after hydrazine treatment. It is found that the on-current improves obviously by one order of magnitude and the metal-WSe2 contact resistance decreases at the same time. After hydrazine being removed, the electron doping effect disappears which indicates hydrazine treatment is a reversible doping process. this work provides a possibility for transition metal dichalcogenides-based logic device applications in the future.

关键词： Tunable transfer behaviors of single-layer WSe field effect transistors by hydrazine

来源：评论

学校读者我要写书评

暂无评论

Scavenger: Automating the Construction of Application-Optimized Memory Hierarchies 25

Scavenger: Automating the Construction of Application-Optimi...

引用

25th international conference on field programmable logic and applications

作者： Yang, Hsin-Jung Fleming, Kermin Adler, Michael Winterstein, Felix Emer, Joel MIT CSAIL Cambridge MA 02139 USA Intel Corp SSG Santa Clara CA 95051 USA European Space Agcy Ground Stn Syst Div F-75738 Paris 15 France NVIDIA Res Santa Clara CA USA

ISBN: (纸本)9781467381239

High-level abstractions separate algorithm design from platform implementation, allowing programmers to focus on algorithms while building increasingly complex systems. this separation also provides system programmers and compilers an opportunity to optimize platform services for each application. In FPGAs, this platform-level malleability extends to the memory system: unlike general-purpose processors, in which memory hardware is fixed at design time, the capacity, associativity, and topology of FPGA memory systems may all be tuned to improve application performance. Since application kernels often use few memory resources, substantial memory capacity may be available to the platform for use on behalf of the user program. In this work, we perform an initial exploration of methods for automating the construction of these application-specific memory hierarchies. Although exploiting spare resources can be beneficial, naively consuming all memory resources may cause frequency degradation. To relieve timing pressure in large BRAM structures, we provide microarchitectural techniques to trade memory latency for design frequency. We demonstrate, by examining both hand-assembled and HLS-compiled benchmarks, that our application-optimized memory system can improve preexisting application runtime by 25% on average.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

A survey on reconfigurable accelerators for cloud computing

A survey on reconfigurable accelerators for cloud computing

引用

international conference on field programmable logic and applications

作者： Christoforos Kachris Dimitrios Soudris Institute of Communication and Computer Systems (ICCS/NTUA) Athens Greece National Technical University of Athens (NTUA) Athens Greece

Data centers are experiencing an exponential increase in the amount of network traffic that they have to sustain due to cloud computing and several emerging web applications. To face this network load, large data centers are required with thousands of servers interconnected with high bandwidth switches. Current data center, based on general purpose processor, consume excessive power while their utilization is quite low. Hardware accelerators can provide high energy efficiency for many cloud applications but they lack the programming efficiency of processors. In the last few years, there several efforts for the efficient deployment of hardware accelerators in the data centers. this paper presents a thorough survey of the frameworks for the efficient utilization of the FPGAs in the data centers. Furthermore it presents the hardware accelerators that have been implemented for the most widely used cloud computing applications. Furthermore, the paper provides a qualitative categorization and comparison of the proposed schemes based on their main features such as speedup and energy efficiency.

关键词： Cloud computing field programmable gate arrays Hardware Data analysis Benchmark testing Sparks Measurement

来源：评论

学校读者我要写书评

暂无评论

Automatic Support for Multi-Module Parallelism from Computational Patterns 25

Automatic Support for Multi-Module Parallelism from Computat...

引用

25th international conference on field programmable logic and applications

作者： George, Nithin Lee, HyoukJoong Novo, David Owaida, Muhsen Andrews, David Olukotun, Kunle Ienne, Paolo Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland Stanford Univ Pervas Parallelism Laboratory Stanford CA 94305 USA Univ Arkansas Dept Comp Sci & Comp Engn Fayetteville AR 72701 USA

ISBN: (纸本)9781467381239

field programmable Gate Arrays (FPGAs) can be customized into application-specific architectures to achieve high performance and energy-efficiency. Unfortunately, they are yet to gain significant adoption by application developers due to their low-level programming model. Moreover, to obtain good performance in an FPGA design, one often needs to correctly parallelize computation and balance the computational throughput with the available data access bandwidth. To address the programming model problem, recent efforts have focused on composing applications out of parallel computational patterns, such as map, reduce, zipWith and foreach, and leveraging the properties of these patterns to generate highly parallel hardware modules capable of high performance. In this work, we focus on the problem of further improving the performance and show that we can utilize the knowledge of how data is consumed and produced by these computational patterns in conjunction with the information of the system architecture to automatically parallelize computations across multiple hardware modules. To achieve this, we automatically infer synchronization needs arising due to parallelization and generate a complete system that can obtain high performance for a given application. We evaluate our approach using seven applications from different domains and show that our automatically generated designs achieve performance improvements ranging from 1.8 to 9.4 times.

关键词： HIGH-PERFORMANCE hardware module AUTOMATIC multi modules field programmable gate arrays application developer Building systems parallelization Synclitism parallelism

来源：评论

学校读者我要写书评

暂无评论

Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer

Single-FPGA, scalable, low-power, and high-quality 3D ultras...

引用

international conference on field programmable logic and applications

作者： W. Simon A. C. Yüzügüler A. Ibrahim F. Angiolini M. Arditi J.-P. thiran G. De Micheli École Polytechnique Fédérale de Lausanne (EPFL) Switzerland Department of Radiology University Hospital Center (CHUV) and University of Lausanne (UNIL) Switzerland

We present an efficient FPGA architecture suitable for a medical 3D ultrasound beamformer. We tackle the delay calculation bottleneck, which is the heart and the most critical part of the beamformer, by proposing a computationally efficient design that is able to perform volumetric real-time beamforming on a single-chip FPGA. the design has been demonstrated for a 32×32-channel receive probe, and we extrapolated the requirements of the architecture for 80×80 channels.

关键词： Delays field programmable gate arrays three-dimensional displays Computer architecture Imaging Ultrasonic imaging Probes

来源：评论

学校读者我要写书评

暂无评论

Demonstration of a context-switch method for heterogeneous reconfigurable systems

Demonstration of a context-switch method for heterogeneous r...

引用

international conference on field programmable logic and applications

作者： Arief Wicaksana Alban Bourge Olivier Muller Frédéric Rousseau TIMA Laboratory - Grenoble-INP/UGA/CNRS Grenoble FRANCE

Nowadays, FPGAs are integrated in high-performance computing systems, servers, or even used as accelerators in System-on-Chip (SoC) platforms. Since the execution is performed in hardware, FPGA gives much higher performance and lower energy consumption compared to most microprocessor-based systems. However, the room to improve FPGA performance still exists, e.g. when it is used by multiple users. In multi-user approaches, FPGA resources are shared between several users. therefore, one must be able to interrupt a running circuit at any given time and continue the task at will. An image of the state of the running circuit (context) is saved during interruption and restored when the execution is continued. the ability to extract and restore the context is known as context-switch.

关键词： field programmable gate arrays Servers Context Interrupters Image restoration System-on-chip Hardware

来源：评论

学校读者我要写书评

暂无评论

Overcoming resource underutilization in spatial CNN accelerators

Overcoming resource underutilization in spatial CNN accelera...

引用

international conference on field programmable logic and applications

作者： Yongming Shen Michael Ferdman Peter Milder Stony Brook University

Convolutional neural networks (CNNs) are revolutionizing a variety of machine learning tasks, but they present significant computational challenges. Recently, FPGA-based accelerators have been proposed to improve the speed and efficiency of CNNs. Current approaches construct an accelerator optimized to maximize the overall throughput of iteratively computing the CNN layers. However, this approach leads to dynamic resource underutilization because the same accelerator is used to compute CNN layers of radically varying dimensions. We present a new CNN accelerator design that improves the dynamic resource utilization. Using the same FPGA resources, we build multiple accelerators, each specialized for specific CNN layers. Our design achieves 1.3× higher throughput than the state of the art when evaluating the convolutional layers of the popular AlexNet CNN on a Xilinx Virtex-7 FPGA.

关键词： Digital signal processing field programmable gate arrays throughput Convolutional codes Image segmentation Dynamic scheduling Adders

来源：评论

学校读者我要写书评

暂无评论

Modelling delay degradation due to NBTI in FPGA Look-up tables

Modelling delay degradation due to NBTI in FPGA Look-up tabl...

引用

international conference on field programmable logic and applications

作者： Mohammad Naouss François Marc University of Bordeaux IMS Laboratory Talence France

field-programmable Gate Arrays (FPGAs) benefit from the most advanced CMOS technology nodes, in order to meet the increasing demands of high performance and low power digital integrated circuits. this makes them susceptible to various reliability challenges at nano-scale. In this paper, we focus on aging degradation of the Look-up table (LUT) on FPGAs. We have characterized the delay degradation of LUT depending on the duty cycle of stress vectors. We have identified also that the duty cycle affects strongly the fall and moderately the rise delay of LUT due to the NBTI aging mechanism. Furthermore, a semi-empirical model of the degradation of LUT timing due to NBTI depending on the time and the duty cycle of stress vector has been investigated in this work. this model can be used to predict the degradation of a complex circuit implemented in a FPGA, and especially the risk of timing violations due to NBTI aging.

关键词： Delays Degradation Table lookup Stress field programmable gate arrays Aging Negative bias temperature instability

来源：评论

学校读者我要写书评

暂无评论

Hardware acceleration of feature detection and description algorithms on low-power embedded platforms

Hardware acceleration of feature detection and description a...

引用

international conference on field programmable logic and applications

作者： Onur Ulusel Christopher Picardo Christopher B. Harris Sherief Reda R. Iris Bahar School of Engineering Brown University Providence RI

Image features are broadly used in embedded computer vision applications, from object detection and tracking to motion estimation and 3D reconstruction. Efficient feature extraction and description are crucial due to the real-time requirements of such applications over a constant stream of input data. High-speed computation typically comes at the cost of high power dissipation, yet embedded systems are often highly power constrained, making discovery of power-aware solutions especially critical for these systems. In this paper, we present a power and performance evaluation of three low cost feature detection and description algorithms implemented on various embedded systems (embedded CPUs, GPUs and FPGAs). We show that FPGAs in particular offer attractive solutions for both performance and power and describe several design techniques utilized to accelerate feature extraction and description algorithms on low-cost Zynq SoC FPGAs.

关键词： Feature extraction Algorithm design and analysis field programmable gate arrays Acceleration Detectors Hardware Power dissipation

来源：评论

学校读者我要写书评

暂无评论

Serial and Parallel Interleaved Modular Multipliers on FPGA Platform 25

Serial and Parallel Interleaved Modular Multipliers on FPGA ...

引用

25th international conference on field programmable logic and applications

作者： Javeed, Khalid Wang, Xiaojun Scott, Mike Dublin City Univ Sch Elect Engn Dublin Ireland CertiVox UK London England

ISBN: (纸本)9781467381239

Modular multiplication is a core operation in all public key based cryptosystems. the performance of these cryptosystems can be enhanced substantially by incorporating an optimized modular multiplier. this paper presents serial and parallel radix-4 modular multipliers based on interleaved multiplication algorithm and Montgomery power laddering technique. A serial radix-4 interleaved modular multiplier provides 5 0 % reduction in the required clock cycles. In addition to the reduction in clock cycles, a parallel modular multiplier maintains a critical path delay comparable to the bit serial interleaved multipliers. the proposed designs are implemented in Verilog HDL and synthesized targeting virtex-6 FPGA platform using Xilinx ISE 14.2 Design suite. the serial radix-4 multiplier computes a 256-bit modular multiplication in 1.3 mu s, occupies 3.9K LUTs, and runs at 96 MHz. the parallel radix-4 multiplier takes 0.77 mu s, occupies 5.3K LUTs, and runs at 166 MHz. the results show that the parallel radix-4 modular multiplier provides 62 % and 49 % speed-up over the corresponding bit serial and bit parallel versions, respectively. thus, these designs are suitable to accelerate modular multiplication in many cryptographic processors.

关键词： Finite field elliptic curve cryptography (ECC) interleaved multiplication public key cryptography (PKC)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共185页 << < 60 61 62 63 64 65 66 67 68 69 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：