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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1847 条记录，以下是641-650 订阅

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Designing a virtual runtime for FPGA accelerators in the cloud

Designing a virtual runtime for FPGA accelerators in the clo...

引用

international conference on field programmable logic and applications

作者： Mikhail Asiatici Nithin George Kizheppatt Vipin Suhaib A. Fahmy Paolo Ienne Ecole Poly technique Fédérale de Lausanne (EPFL) School of Computer and Communication Sciences Mahindra Ecole Centrale School of Engineering Sciences University of Warwick School of Engineering Email

FPGAs can provide high performance and energy efficiency to many applications; therefore, they are attractive computing platforms in a cloud environment. However, FPGA application development requires extensive hardware design knowledge which significantly limits the potential user base. Moreover, in a cloud setting, allocating a whole FPGA to a user is often wasteful and not cost effective due to low device utilization. To make FPGA application development easier, firstly, we propose a methodology that provides clean abstractions with high-level APIs and a simple execution model that supports both software and hardware execution. Secondly, to improve device utilization and share the FPGA among multiple users, we developed a lightweight runtime system that provides hardware-assisted memory virtualization and memory protection, enabling multiple applications to simultaneously execute on the device.

关键词： Cloud computing field programmable gate arrays Performance evaluation Manuals Computer architecture

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Connect on the fly: Enhancing and prototyping of cycle-reconfigurable modules

Connect on the fly: Enhancing and prototyping of cycle-recon...

引用

international conference on field programmable logic and applications

作者： Hao Zhou Xinyu Niu Junqi Yuan Lingli Wang Wayne Luk School of Microelectronics Fudan University China Dept. of Computing Imperial College London UK

this paper introduces cycle-reconfigurable modules that enhance FPGA architectures with efficient support for dynamic data accesses: data accesses with accessed data size and location known only at runtime. the proposed module adopts new reconfiguration strategies based on dynamic FIFOs, dynamic caches, and dynamic shared memories to significantly reduce configuration generation and routing complexity. We develop a prototype FPGA chip with the proposed cycle-reconfigurable module in the SMIC 130-nm technology. the integrated module takes less than the chip area of 39 CLBs, and reconfigures thousands of runtime connections in 1.2 ns. applications for large-scale sorting, sparse matrix-vector multiplication, and Memcached are developed. the proposed modules enable 1.4 and 11 times reduction in area-delay product compared with those applications mapped to previous architectures and conventional FPGAs.

关键词： Runtime Clocks field programmable gate arrays Customer relationship management Routing Hardware System-on-chip

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Low-latency TCP/IP stack for data center applications

Low-latency TCP/IP stack for data center applications

引用

international conference on field programmable logic and applications

作者： David Sidler Zsolt István Gustavo Alonso Systems Group ETH Zürich

TCP/IP is widely used both in the Internet as well as in data centers. the protocol makes very few assumptions about the underlying network and provides useful guarantees such as reliable transmission, in-order delivery, or control flow. the price for this functionality is complexity, latency, and computational overhead, which is especially pronounced in software implementations. While for Internet communication this is acceptable, the overhead is too high in data centers. In this paper, we explore how to optimize a TCP/IP stack running on an FPGA for data center applications with an emphasis on data processing (e.g., key value stores). Using a key-value store and a low-latency consensus protocol implemented on an FPGA as an example of the requirements that arise in data centers, we provide an extensive analysis of the overheads of TCP/IP and the solutions that can be adopted to minimize such an overhead. the proposed optimized TCP/IP stack minimizes tail latencies (a key metric in distributed data processing) and is efficiently implemented so as to be able to share the FPGA with application logic.

关键词： field programmable gate arrays TCPIP Memory management Bandwidth Payloads Engines Protocols

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Memory efficient and high performance key-value store on FPGA using Cuckoo hashing

Memory efficient and high performance key-value store on FPG...

引用

international conference on field programmable logic and applications

作者： Wei Liang Wenbo Yin Ping Kang Lingli Wang State Key Laboratory of ASIC and System Fudan University

Key-value stores (KVS) become critical in many applications because of the data explosion recently. there is a strong demand to improve the throughput and reduce the latency for KVS. FPGA-based parallel architecture can bring excellent performance and power efficiency. Cuckoo hashing has proven to be an efficient approach to implement KVS with good memory utilization and constant worst case access time. In this paper, an FPGA-based KVS implementation is proposed based on Cuckoo hashing, with a decoupled storage to achieve 81.7% memory utilization, and a pipeline scheme to achieve high performance. the latency of insert, search and delete operations is only 40 ns. And the throughput for search and delete can be 200 million requests per second (MRPS) which is 5× faster than [1]. Even when the load factor becomes 0.9, the throughput for insert can still achieve 147 MRPS.

关键词： Pipelines Arrays throughput field programmable gate arrays Memory management Clocks Random access memory

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Transparent FPGA flow

Transparent FPGA flow

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international conference on field programmable logic and applications

作者： Baptiste Delporte Anthony Convers Roberto Rigamonti Alberto Dassatti HES-SO — REDS Institute HEIG-VD — School of Business and Engineering Yverdon-les-Bains Switzerland

In this demo we propose an automated flow that allows the transparent execution of ordinary code on a heterogeneous platform including an FPGA. Our solution requires no change in the code, not even pragma indications to guide the optimization, and dynamically adapts its behaviour to the available data and the workload of the system. thus, the developer does not need to be aware of the target platform details, nor she has to forecast usage patterns to prevent performance bottlenecks, as the system transparently identifies parallelizable, computationally-intensive code fragments and dispatches them to a data flow overlay architecture built on top of the FPGA. Since the bitstream we use is fixed, and contrary to HLS, we can alter the functionalities offered by the FPGA on-the-fly to adapt them to current usage. Finally, since we operate at the LLVM's Intermediate Representation (IR) level, our approach is language-agnostic.

关键词： field programmable gate arrays Computer architecture Flow graphs Acceleration Performance evaluation Optimization Computers

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Improved resource sharing for FPGA DSP blocks

Improved resource sharing for FPGA DSP blocks

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international conference on field programmable logic and applications

作者： Bajaj Ronak Suhaib A. Fahmy School of Computer Science and Engineering Nanyang Technological University Singapore School of Engineering University of Warwick Coventry UK

Sharing multi-cycle hardware blocks like the DSP48E1 primitive in Xilinx FPGAs can result in significant resource savings, but complicates scheduling. For high-throughput, DSP blocks must be pipelined, which results in a high initiation interval (II) for resource shared implementations. In this paper, we propose a resource reduction technique that minimises DSP block usage while also offering improved II over traditional approaches. this is integrated in a high-level tool which takes datapath descriptions in C and generates synthesisable Verilog RTL with different levels of resource sharing. We demonstrate significantly improved throughput compared to traditional resource sharing while achieving resource reduction compared to resource unconstrained and HLS implementations. the approach explores an otherwise infeasible design space between resource unconstrained and traditional resource sharing methods.

关键词： Digital signal processing Resource management Schedules throughput Processor scheduling field programmable gate arrays Clocks

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GraVF: A vertex-centric distributed graph processing framework on FPGAs

GraVF: A vertex-centric distributed graph processing framewo...

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international conference on field programmable logic and applications

作者： Nina Engelhardt Hayden Kwok-Hay So Department of Electrical and Electronic Engineering The University of Hong Kong

FPGAs are promising platforms to efficiently execute distributed graph algorithms. Unfortunately, they are notoriously hard to program, especially when the problem size and system complexity increases. In this paper, we propose GraVF, a high-level design framework for distributed graph processing on FPGAs. It leverages the vertex-centric paradigm, which is naturally distributed and requires the user to define only very small kernels and their associated message semantics for the target application. the user design may subsequently be elaborated and compiled to the target system automatically by the framework. To demonstrate the flexibility and capabilities of the proposed framework, 4 graph algorithms with distinct requirements have been implemented, namely breadth-first search, PageRank, single source shortest path, and connected component. Results show that the proposed framework is capable of producing FPGA designs with performance comparable to similar custom designs while requiring only minimal input from the user.

关键词： Kernel field programmable gate arrays Computational modeling Programming Algorithm design and analysis Hardware Computer architecture

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Configurable and scalable belief propagation accelerator for computer vision

Configurable and scalable belief propagation accelerator for...

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international conference on field programmable logic and applications

作者： Jungwook Choi Rob A. Rutenbar IBM T. J. Watson Research Center Yorktown Heights NY

We demonstrate a novel FPGA-based accelerator architecture that can tackle a range of standard computer vision (CV) problems, with scalable performance and attractive speedups. the architecture relies on multiple pipelined processing elements (PEs) that can be configured to support various belief propagation (BP) settings for different CV tasks. Inside each PE, innovative implementation of Jump Flooding for efficient computation of BP solves the core configurability challenge. A novel block-parallel memory interface supports parallelization by distributing BP inference workloads across the PEs. Experimental results demonstrate that our accelerator achieves scalable performance with 11-41× speedup over standard sequential CPU implementations across a subset of well-known Middlebury and OpenGM benchmarks, with no compromise in quality of inference results. To the best of our knowledge, this is the first FPGA hardware implementation of BP capable of running a range of standard CV benchmarks with significant speedups.

关键词： field programmable gate arrays Hardware Computer architecture Bandwidth Computer vision Message passing Belief propagation

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JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication

JetStream: An open-source high-performance PCI Express 3 str...

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international conference on field programmable logic and applications

作者： Malte Vesper Dirk Koch Kizheppatt Vipin Suhaib A. Fahmy School of Computer Science University of Manchester Mahindra École Centrale School of Engineering University of Warwick

Many FPGA-based accelerators are constrained by the available resources and multi-FPGA solutions can be necessary for building more capable systems. Available PCIe solutions provide only FPGA-to-Host communication. In this paper we present JetStream, an open-source 1 modular PCIe 3 library, supporting not only fast FPGA-to-Host communication, but also allowing direct FPGA-to-FPGA communication which fully bypasses the memory subsystem. the direct mode saves memory bandwidth for multicast modes and permits to connect multiple FPGAs in various software defined topologies. We show the benefits of JetStream with a large FIR filter spanning four FPGA boards, achieving throughputs of up to 7.09 GB/s per link. Utilizing direct FPGA-to-FPGA transfers reduces the required memory bandwidth by up to 75%.

关键词： field programmable gate arrays Registers Bandwidth Payloads throughput Engines Hardware

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Bayesian inference implemented on FPGA with stochastic bitstreams for an autonomous robot

Bayesian inference implemented on FPGA with stochastic bitst...

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international conference on field programmable logic and applications

作者： Hugo Fernandes M. Awais Aslam Jorge Lobo João Filipe Ferreira Jorge Dias ISR - Institute of Systems and Robotics University of Coimbra Portugal ISR - Institute of Systems and Robotics DEEC University of Coimbra Portugal DEEC Portugal Khalifa University Abu Dhabi UAE

this paper presents an FPGA implementation of a machine performing exact Bayesian inference using stochastic bitstreams. We revisited stochastic computing, not to perform better computations with unreliable hardware, but to perform approximate computations with less hardware. the underlying trade-off is between precision and computation time. An automatic design of probabilistic machines that compute soft inferences with an arithmetic based on stochastic bitstreams is presented. the computation tree provided by a Bayesian inference software is used to define the stochastic circuit. Tests were performed and results presented concerning accuracy and resource usage of the stochastic computing implementation of Bayesian machines performing exact inference. An application example is given of a Bayesian sensorimotor system that performs obstacle avoidance for an autonomous robot, fully implemented on an FPGA. Some conclusions were drawn on the followed approach, providing insights for future implementations.

关键词： Bayes methods Stochastic processes Robots field programmable gate arrays Computational modeling Probabilistic logic Probability distribution

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