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Comprehensive laser sensitivity profiling and data register bit-flips for cryptographic fault attacks in 65 Nm FPGA 6th

Comprehensive laser sensitivity profiling and data register ...

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6th international conference on Security, Privacy, and Applied Cryptography Engineering, SPACE 2016

作者： He, Wei Breier, Jakub Bhasin, Shivam Jap, Dirmanto Ong, Hock Guan Gan, Chee Lip Lab of Physical Analysis and Cryptographic Engineering Nanyang Technological University Singapore Singapore School of Physical and Mathematical Sciences Nanyang Technological University Singapore Singapore School of Materials Science and Engineering Nanyang Technological University Singapore Singapore Temasek Laboratories Nanyang Technological University Singapore Singapore

ISBN: (纸本)9783319494449

FPGAs have emerged as a popular platform for security sensitive applications. As a practical attack methodology, laser based fault analyses have drawn much attention in the past years due to its superior accuracy in fault perturbation into security-critical Integrated Circuits (ICs). However, due to the insufficient device information, the practical injections work are not so efficient as expected. In this paper, we thoroughly analyze the laser fault injections to data flip-flops, instead of the widely studied configuration memory bits, of a modern nanoscale FPGA. A profiling campaign based on laser chip scan is performed on an exemplary 65 nm Virtex-5 FPGA, through the delayered silicon substrate, to identify the laser sensitivity distribution of the resource array and the fundamental logic cells. the sophisticated flip-flop bit flips are realized by launching fine-grained laser perturbations on an identified Configurable logic Block (CLB) region. the profiled laser fault sensitivity map to FPGA resource significantly facilitate high-precision logic navigation and fault injection in practical cryptographic fault attacks. We show that the observed single- and multiple-bit faults are compatible with most proposed differential or algebraic fault analyses (DFA/AFA). Finally, further discussions on capability of reported fault models to bypass fault countermeasures like parity and dual-rail logic are also given. © Springer international Publishing AG 2016.

关键词： field programmable gate arrays (FPGA)

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Annotation-based finite-state transducers on reconfigurable devices

Annotation-based finite-state transducers on reconfigurable ...

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international conference on field programmable logic and applications

作者： Raphael Polig Kubilay Atasu Christoph Hagleitner theresa Xu Akihiro Nakayama IBM Research - Zurich Rueschlikon Switzerland IBM Systems Toronto Canada IBM Watson Tokyo Japan

With the ever growing amount of unstructured data, high-speed content analysis becomes ever more important. Enabling efficient search functions to help locate specific and relevant information hidden in this big data is a crucial task of today's enterprise systems, and can lead to valuable insights. A key component of content analysis systems are text parsers, which transform unstructured text data into structured information. Cascaded grammars offer a popular and powerful representation of text parsers by enabling the definition of more complex patterns in terms of simpler ones in a hierarchical fashion. this work presents a compilation framework to generate an optimized FPGA pipeline from a cascaded grammar description. We also describe the system integration and the way FPGA-based accelerators can be used as part of larger analysis tasks within Unstructured Information Management Application (UIMA) pipelines. We compare the performance of the hardware-accelerated system and a commercial software implementation using real-life UIMA pipelines from the healthcare domain. We show that the FPGA-accelerated system processes the parsing stage of a UIMA pipeline up to 31 times faster than the software implementation running on a high-end server, which results in an acceleration of up to 5 times for the complete pipeline.

关键词： Grammar Computer architecture Transducers field programmable gate arrays Pipelines Registers Engines

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Resource efficient real-time processing of Contrast Limited Adaptive Histogram Equalization

Resource efficient real-time processing of Contrast Limited ...

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international conference on field programmable logic and applications

作者： Burak Unal Ali Akoglu Department of Electrical and Computer Engineering The University of Arizona Tucson USA

Contextual Contrast Limited Adaptive Histogram Equalization (C-CLAHE) is an effective method for solving the noise amplification effect of the adaptive histogram equalization (AHE), and enhancing the visibility of local details of an image. Even though C-CLAHE has a smaller memory foot print than CLAHE, complexity of the interpolation process increases the computation demand dramatically. therefore, FPGA based implementations have been limited to CLAHE only. In this study we introduce three key modifications to the C-CLAHE, and for the first time make it feasible to implement on a resource limited FPGA. We restructure the method so that the histogram redistribution stage is realized with fewer number of iterations. We implement contrast limitation calculations earlier during the histogram generation stage instead of during the histogram redistribution stage, which reduces the block RAM demand. We finally mathematically derive an alternative interpolation calculation used during the remapping stage, which reduces the computation complexity in terms of required multipliers by a factor of 2×, without sacrificing the image quality. these algorithmic modifications allowed us to reduce the block RAM demand by a factor of 12×, logic block demand by a factor of 6.7× compared to the state of the art FPGA based CLAHE implementation, and achieve real time processing of 640 × 480 images at a rate of 354 frames per second.

关键词： Histograms field programmable gate arrays Random access memory Real-time systems Complexity theory Interpolation Adaptive equalizers

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Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs

Automated extra pipeline analysis of applications mapped to ...

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international conference on field programmable logic and applications

作者： Ilya Ganusov Henri Fraisse Aaron Ng Rafael Trapani Possignolo Sabya Das Xilinx Inc. San Jose CA Dept. of Computer Engineering University of California Santa Cruz CA

this paper describes the methodology and algorithms behind extra pipeline analysis tools released in the Xilinx Vivado Design Suite version 2015.3. Extra pipelining is one of the most effective ways to improve performance of FPGA applications. Manual pipelining, however, often requires significant efforts from FPGA designers who need to explore various changes in the RTL and re-run the flow iteratively. the automatic pipelining approach described in this paper, in contrast, allows FPGA users to explore latency vs. performance trade-offs of their designs before investing time and effort into modifying RTL. We describe algorithms behind these tools which use simple cut heuristics to maximize performance improvement while minimizing additional latency and register overhead. To demonstrate the effectiveness of the proposed approach, we analyse a set of 93 commercial FPGA applications and IP blocks mapped to Xilinx UltraScale+ and UltraScale generations of FPGAs. the results show that extra pipelining can provide from 18% to 29% potential Fmax improvement on average. It also shows that the distribution of improvements is bimodal, with almost half of benchmark suite designs showing no improvement due to the presence of large loops. Finally, we demonstrate that highly-pipelined designs map well to UltraScale+ and UltraScale FPGA architectures. Our approach demonstrates 19% and 20% Fmax improvement potential for the UltraScale+ and UltraScale architectures respectively, with the majority of applications reaching their loop limit through pipelining.

关键词： Pipeline processing Registers field programmable gate arrays Pins Table lookup Algorithm design and analysis Pipelines

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A survey of AIS-20/31 compliant TRNG cores suitable for FPGA devices

A survey of AIS-20/31 compliant TRNG cores suitable for FPGA...

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international conference on field programmable logic and applications

作者： Oto Petura Ugo Mureddu Nathalie Bochard Viktor Fischer Lilian Bossuet UMR 5516 CNRS Jean Monnet University Saint-Etienne Saint-Etienne France

FPGAs are widely used to integrate cryptographic primitives, algorithms, and protocols in cryptographic systems-on-chip (CrySoC). As a building block of CrySoCs, True Random Number Generators (TRNGs) exploit analog noise sources in electronic devices to generate confidential keys, initialization vectors, challenges, nonces, and random masks in cryptographic protocols. TRNGs aimed at cryptographic applications must fulfill the security requirements defined in the German Federal Bureau for Information Security's (BSI) recommendations AIS-20/31, which has become a de facto standard in Europe. Many TRNG cores have already been published, only a few of which are suitable for FPGAs and even fewer comply with AIS-20/31. Here we present the results of the implementation of AIS-20/31 compliant TRNG cores in three FPGA families: Xilinx Spartan 6, Altera Cyclone V and Microsemi SmartFusion 2. In addition to common design parameters like area, bit rate and power/energy consumption, we compare and discuss the feasibility of generator cores in different FPGAs and the statistical quality of their output. these results will help designers select the best generator and the device family to match the requirements of the data security application. To ensure reproducibility of the results, the open source VHDL code of all generators adapted to individual families can be downloaded from the dedicated web page.

关键词： field programmable gate arrays Generators Clocks Jitter Ring oscillators Entropy Cryptography

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SRI-SURF: A better SURF powered by scaled-RAM interpolator on FPGA

SRI-SURF: A better SURF powered by scaled-RAM interpolator o...

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international conference on field programmable logic and applications

作者： Xijie Jia Kaiyuan Guo Wenqiang Wang Yu Wang Huazhong Yang Kunming Institute of Physics Kunming China E.E. Dept. Tsinghua University Beijing China Microsoft Research Asia Beijing China

Speed-Up Robust Feature (SURF) is an effective algorithm for feature extraction. We propose a novel Scaled-RAM Interpolator (SRI) on FPGA to deal with the high complexity of SURF by introducing two methods. 1) Interpolation of Integral Image (I 3 ) restores the sub-pixel details of image to improve matching precision, and halves the memory access to achieve acceleration; 2) Multi-Scaled RAM (MSR) normalizes the storage allocation by scale to decrease complexity of memory access and reject redundant memory. With SRI, our system achieves better matching precision, higher processing speed, and lower storage occupation. the results of evaluation implemented on Stratix III EP3SL340 FPGA show that 1) our SRI-SURF system performs better in matching than OpenSURF; 2) the system is capable to process 241K feature points per second (PPS), which is about 7× of previous work on FPGA and is comparable to the recent ASIC solution; 3) the maximal frame rate reaches 488FPS at VGA and 72FPS at 1080P, which outperforms designs in other publications; 4) our design is compact, which only occupies about 22% logic resource and about 43% RAM resource at 1080P. the proposed SRI-SURF meets the demand of real-time embedded applications with better precision at high resolution.

关键词： field programmable gate arrays Feature extraction Random access memory Interpolation Algorithm design and analysis IP networks Hardware

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Controller architecture for low-latency access to phase-change memory in OpenPOWER systems

Controller architecture for low-latency access to phase-chan...

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international conference on field programmable logic and applications

作者： A. Prodromakis N. Papandreou E. Bougioukou U. Egger N. Toulgaridis th. Antonakopoulos H. Pozidis E. Eleftheriou University of Patras Rio-Patras Greece IBM Research - Zurich Rüschlikon Switzerland University of Patras Patras GR

Novel forms of nonvolatile memory, such as phase-change memory (PCM), promise low latency and small granularity of read and write access at high storage density. they also feature very high endurance. these characteristics make them highly desirable for emerging high-capacity (hybrid) memory applications such as in-memory databases and in-memory processing. In this work, we present the architecture, implementation and experimental performance results of an FPGA-based PCM memory controller for OpenPOWER servers. the memory controller leverages the Coherent Accelerator Processor Interface (CAPI) of the POWER processor in order to offer low-latency access to the CPU memory space. In addition, the memory controller implements an efficient management protocol that supports a dynamic size of pending read and write requests in order to offer high bandwidth under mixed-type workloads. We describe the architecture and implementation details of the memory controller and we demonstrate its performance using a prototype platform based on different types of OpenPOWER servers equipped with CAPI-enabled FPGA cards. the developed PCM controller is evaluated in terms of sustained data rates (MBps) and access latency (us). Experimental results are based on legacy commercial 90nm PCM chips as well as on accurate HW emulation of next generation PCM chips.

关键词： Phase change materials Nonvolatile memory field programmable gate arrays Servers Memory management Next generation networking Engines

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FPGA-based accelerator design from a domain-specific language

FPGA-based accelerator design from a domain-specific languag...

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international conference on field programmable logic and applications

作者： M. Akif Özkan Oliver Reiche Frank Hannig Jürgen Teich Friedrich-Alexander University of Erlangen-Ntirnberg (FAU) Germany

A large portion of image processing applications often come with stringent requirements regarding performance, energy efficiency, and power. FPGAs have proven to be among the most suitable architectures for algorithms that can be processed in a streaming pipeline. Yet, designing imaging systems for FPGAs remains a very time consuming task. High-Level Synthesis, which has significantly improved due to recent advancements, promises to overcome this obstacle. In particular, Altera OpenCL is a handy solution for employing an FPGA in a heterogeneous system as it covers all device communication. However, to obtain efficient hardware implementations, extreme code modifications, contradicting OpenCL's data-parallel programming paradigm, are necessary. In this work, we explore the programming methodology that yields significantly better hardware implementations for the Altera Offline Compiler. We furthermore designed a compiler back end for a domain-specific source-to-source compiler to leverage the algorithm description to a higher level and generate highly optimized OpenCL code. Moreover, we advanced the compiler to support arbitrary bit width operations, which are fundamental to hardware designs. We evaluate our approach by discussing the resulting implementations throughout an extensive application set and comparing them with example designs, provided by Altera. In addition, as we can derive multiple implementations for completely different target platforms from the same domain-specific language source code, we present a comparison of the achieved implementations in contrast to GPU implementations.

关键词： Kernel Hardware Computer architecture Programming field programmable gate arrays Image processing

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Optimizing hardware design for Human Action Recognition

Optimizing hardware design for Human Action Recognition

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international conference on field programmable logic and applications

作者： Xiaoyin Ma Jose Rodriguez Borbon Walid Najjar Amit K. Roy-Chowdhury University of California Riverside CA USA

Human action recognition (HAR) is an important topic in computer vision having a wide range of applications: health care, assisted living, surveillance, security, gaming, etc. Despite significant amount of work having been conducted in this area in recent years, the execution speed still limits real-time applications. Moreover, it is highly desirable to have the compute-intensive feature extraction stage done right at the output of the camera to extract and transfer only action feature in multi-camera network setting and hence reduce network bandwidth requirement. In this work, we first evaluate the possibility to perform feature extraction under reduced precision fixed-point arithmetic to ease hardware resource requirements. We compared the Histogram of Oriented Gradient in 3D (HOG3D) feature extraction with state-of-the-art Convolutional Neural Networks (CNNs) methods and shown the later to be 75× slower than the former. Our experiment shows that by re-training the classifier with reduced data precision, the classification performs as well as the original double-precision floating-point. Based on this result, we implement an FPGA-based HAR feature extraction for near camera processing using fixed-point data representation and arithmetic. this implementation, using a single Xilinx Virtex 6 FPGA, achieves about 70× speedup over multicore CPU. Furthermore, a GPU implementation of HAR is introduced with 80× speedup over CPU (on an Nvidia Tesla K20). Last but not least, a power comparison is presented for the three platforms.

关键词： Feature extraction field programmable gate arrays Histograms three-dimensional displays Cameras Hardware Bandwidth

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Quantifying observability for in-system debug of high-level synthesis circuits

Quantifying observability for in-system debug of high-level ...

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international conference on field programmable logic and applications

作者： Jeffrey Goeders Steven J.E. Wilton Department of Electrical and Computer Engineering University of British Columbia Vancouver Canada

In recent years high-level synthesis (HLS) has seen considerable attention as it promises to increase designer productivity and make custom hardware implementation accessible to software developers. A challenge facing those developing HLS technologies is how to allow users to understand, debug and optimize their final hardware systems. Recently, several techniques have been developed to provide in-system debugging capabilities for HLS circuits. these techniques instrument the user's design with some debugging circuitry to provide observability into the circuit during execution. Due to resource constraints, it is usually infeasible to view all variable values for the entire circuit execution. Rather, instrumentation usually captures only some variable values and for only a portion of the circuit execution. In this paper we present a metric for measuring the observability into an executing HLS circuit. this metric reflects the portion of variable accesses that are available to the user, the duration of execution for which these values are available, as well as accommodating variations in importance between source code variables. this metric can be used to understand how different circuit observation networks can provide the user with different levels of observability into the HLS circuit execution. As a demonstration of the applicability of the metric, we first study differences between recent debugging approaches for HLS circuits, and quantify the level of observability provided by such architectures. We then explore different schemes to select which variables are accessible in the observation network, and measure impact on variable availability and length of captured execution trace.

关键词： Debugging Software Hardware Observability Measurement Computer bugs field programmable gate arrays

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