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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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An evaluation on the accuracy of the minimum width transistor area models in ranking the layout area of FPGA architectures

An evaluation on the accuracy of the minimum width transisto...

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international conference on field programmable logic and applications

作者： Farheen Fatima Khan Andy Ye Department of Electrical and Computer Engineering Ryerson University Toronto Canada

this work provides an evaluation on the accuracy of the minimum width transistor area models in ranking the actual layout area of FPGA architectures. Both the original VPR area model and the new COFFE area model are compared against the actual layouts with up to 3 metal layers for the various FPGA building blocks. We found that both models have significant variations with respect to the accuracy of their predictions across the building blocks. In particular, the original VPR model overestimates the layout area of larger buffers and full adders by as much as 34% while underestimate the layout area of smaller buffers and multiplexers by as much as 59% for an overall prediction error variation of 93%. the newer COFFE model also significantly overestimates the layout area of full adders by 13% and underestimates the layout area of multiplexers by a maximum of 58% for a prediction error variation of 71%. Such variations are particularly significant considering sensitivity analyses are not routinely performed in FPGA architectural studies. Our results suggest that such analyses are extremely important in studies that employing the minimum width area models so the tolerance of the architectural conclusions against the prediction error variations can be quantified. Furthermore, an open source version of the layouts of the actual FPGA building blocks should be created, so their actual layout area can be used to achieve a highly accurate ranking of the implementation area of FPGA architectures built upon these layouts.

关键词： Layout field programmable gate arrays Transistors Mathematical model Computer architecture Architecture Multiplexing

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Liquid: Fast placement prototyping through steepest gradient descent movement

Liquid: Fast placement prototyping through steepest gradient...

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international conference on field programmable logic and applications

作者： Elias Vansteenkiste Seppe Lenders Dirk Stroobandt Department of Electronics and Information Systems Ghent University Belgium

FPGA design compilation takes too much time to allow efficient design turnaround times. the largest runtime consuming steps of the compilation are placement and routing. To speed up the FPGA placement process, analytical placement techniques have become more popular in the last decade. Analytical techniques produce a placement in two steps, a placement prototyping step and a refinement step. In this work we focus on fast FPGA placement prototyping. Placement prototypes are also used to obtain fast accurate timing estimations and speed up the design cycle. In conventional analytical placement prototyping techniques the placement problem is formulated as a linear system which is solved several times to find a good legal placement. the most time consuming step of that process is solving the linear system. We show that it is not necessary to exactly solve this system, but that it is sufficient to optimize the placement following the steepest gradient descent in between legalization phases. this technique is implemented in our new placement tool called Liquid. In Liquid each block's position is updated several times following an accelerated gradient simulation. We compare this new technique with conventional analytical placement. the Titan23 designs and the Stratix IV FPGA are used for benchmarking. the net effect is that the runtime can be reduced by 2× on average compared to conventional analytical placement without losing any quality.

关键词： Liquids Runtime field programmable gate arrays Linear systems Timing Optimization Law

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Survey of domain-specific languages for FPGA computing

Survey of domain-specific languages for FPGA computing

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international conference on field programmable logic and applications

作者： Nachiket Kapre Samuel Bayliss School of Computer Science and Engineering Nanyang Technological University Singapore Department of Electrical and Electronic Engineering Imperial College London London

High-performance FPGA programming has typically been the exclusive domain of a small band of specialized hardware developers. they are capable of reasoning about implementation concerns at the register-transfer level (RTL) which is analogous to assembly-level programming in software. Sometimes these developers are required to push further down to manage even lower levels of abstraction closer to physical aspects of the design such as detailed layout to meet critical design constraints. In contrast, software programmers have long since moved away from textual assembly-level programming towards relying on graphical integrated development environments (IDEs), high-level compilers, smart static analysis tools and runtime systems that optimize, manage and assist the program development tasks. Domain-specific languages (DSLs) can bridge this productivity gap by providing higher levels of abstraction in environments close to the domain of application expert. DSLs carefully limit the set of programming constructs to minimize programmer mistakes while also enabling a rich set of domain-specific optimizations and program transformations. With a large number of DSLs to choose from, an inexperienced FPGA user may be confused about how to select an appropriate one for the intended domain. In this paper, we review a combination of legacy and state-of-the-art DSLs available for FPGA development and provide a taxonomy and classification to guide selection and correct use of the framework.

关键词： field programmable gate arrays Hardware DSL Hardware design languages Software Programming Productivity

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FPGA based nonlinear Support Vector Machine training using an ensemble learning 25

FPGA based nonlinear Support Vector Machine training using a...

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25th international conference on field programmable logic and applications, FPL 2015

作者： Rabieah, Mudhar Bin Bouganis, Christos-Savvas Department of Electrical and Electronic Engineering Imperial College London London United Kingdom

ISBN: (纸本)9780993428005

Support Vector Machines (SVMs) are powerful supervised learning methods in machine learning. However, their applicability to large problems has been limited due to the time consuming training stage whose computational cost scales quadratically with the number of examples. In this work, a complete FPGA-based system for nonlinear SVM training using ensemble learning is presented. the proposed framework builds on the FPGA architecture and utilizes a cascaded multi-precision training flow, exploits the heterogeneity within the training problem by tuning the number representation used, and supports ensemble training tuned to each internal memory structure so to address very large datasets. Its performance evaluation shows that the proposed system achieves more than an order of magnitude better results compared to state-of-the-art CPU and GPU-based implementations. © 2015 Imperial College.

关键词： field programmable gate arrays (FPGA)

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CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing 25

CoRAM++: Supporting data-structure-specific memory interface...

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25th international conference on field programmable logic and applications, FPL 2015

作者： Weisz, Gabriel Hoe, James C. Carnegie Mellon University PittsburghPA United States

ISBN: (纸本)9780993428005

Facilitating DRAM access is an essential part of an application programming environment for FPGA computing. Existing FPGA application programming environments primarily focus on support for simple, regular memory access patterns, such as block copy and streaming. this paper presents CoRAM++, a programming environment for FPGA computing that is based on an extensible set of data-structure-specific memory interfaces. CoRAM++ supports complex data structures, such as multidimensional arrays and linked lists, in addition to simple data access patterns. CoRAM++ defines an appropriate application-level interface for each supported data structure, and provides a specialized soft-logic implementation of the supporting datapath to memory We evaluated the effectiveness of the CoRAM++ data-structure-specific approach in three application scenarios based on streams, multi-dimensional arrays and linked lists. Our results show that the CoRAM++ programming environment can offer convenient application-level interfaces without penalizing DRAM access performance. © 2015 Imperial College.

关键词： field programmable gate arrays (FPGA)

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Stress-aware routing to mitigate aging effects in SRAM-based FPGAs

Stress-aware routing to mitigate aging effects in SRAM-based...

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international conference on field programmable logic and applications

作者： Behnam Khaleghi Behzad Omidi Hussam Amrouch Jörg Henkel Hossein Asadi Department of Computer Engineering Sharif University of Technology Tehran Chair for Embedded Systems Karlsruhe Institute of Technology Germany

Continuous shrinking of transistor size to provide high computation capability along with low power consumption has been accompanied by reliability degradations due to e.g., aging phenomenon. In this regard, with huge number of configuration bits, field-programmable Gate Arrays (FPGAs) are more susceptible to aging since aging not only degrades the performance, it may additionally result in corrupting the configuration cells and thus causing permanent circuit malfunctioning. While several works have investigated the aging effects in Look-Up Tables (LUTs), the routing fabric of these devices is seldom studied - even though it contributes to the majority of FPGAs' resources and configuration bits. Furthermore, there is a high prospect that errors in its state to propagate to the device outputs. In this paper, we first investigate aging effects in the routing fabric of FPGAs with respect to performance and reliability degradations. Based on this investigation, we enhance the conventional routing algorithm to mitigate the impact of aging by increasing the recovery time (i.e., the mechanism used to heal aging-induced defects) of transistors used in the routing resources. We examine our proposed method as reduction in stress time and required guardband to protect against aging in the routing fabric, as well as in improving the FPGA's lifetime. Our experiments show that the proposed method reduces the average stress time and aging-induced delay of routing resources by 41% and 18.3%, respectively. this, in turn, leads to improving the device lifetime by 130% compared to baseline routing. the proposed method can be applied by simple amending of conventional routing algorithms. thus, it incurs negligible delay overhead.

关键词： Aging Routing field programmable gate arrays Table lookup Stress Delays Transistors

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Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA

Scalable and modularized RTL compilation of Convolutional Ne...

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international conference on field programmable logic and applications

作者： Yufei Ma Naveen Suda Yu Cao Jae-sun Seo Sarma Vrudhula Computer and Energy Engineering Arizona State University Tempe USA Decision Systems Engineering Arizona State University Tempe USA

Despite its popularity, deploying Convolutional Neural Networks (CNNs) on a portable system is still challenging due to large data volume, intensive computation and frequent memory access. Although previous FPGA acceleration schemes generated by high-level synthesis tools (i.e., HLS, OpenCL) have allowed for fast design optimization, hardware inefficiency still exists when allocating FPGA resources to maximize parallelism and throughput. A direct hardware-level design (i.e., RTL) can improve the efficiency and achieve greater acceleration. However, this requires an in-depth understanding of both the algorithm structure and the FPGA system architecture. In this work, we present a scalable solution that integrates the flexibility of high-level synthesis and the finer level optimization of an RTL implementation. the cornerstone is a compiler that analyzes the CNN structure and parameters, and automatically generates a set of modular and scalable computing primitives that can accelerate various deep learning algorithms. Integrating these modules together for end-to-end CNN implementations, this work quantitatively analyzes the complier's design strategy to optimize the throughput of a given CNN model with the FPGA resource constraints. the proposed methodology is demonstrated on Altera Stratix-V GXA7 FPGA for AlexNet and NIN CNN models, achieving 114.5 GOPS and 117.3 GOPS, respectively. this represents a 1.9× improvement in throughput when compared to the OpenCL-based design. the results illustrate the promise of the automatic compiler solution for modularized and scalable hardware acceleration of deep learning.

关键词： field programmable gate arrays Convolution Hardware Kernel Acceleration Memory management Algorithm design and analysis

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AdapNoC: A fast and flexible FPGA-based NoC simulator

AdapNoC: A fast and flexible FPGA-based NoC simulator

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international conference on field programmable logic and applications

作者： Hadi Mardani Kamali Shahin Hessabi Sharif University of Technology Tehran Tehran IR Department of Computer Engineering Sharif University of Technology Tehran Iran

Network on Chip (NoC) is the most common interconnection platform for multiprocessor systems-on-chips (MPSoCs). In order to explore the design space of this platform, we need a high-speed, cycle-accurate, and flexible simulation tool. In this paper, we present AdapNoC, a configurable cycle-accurate FPGA-based NoC simulator, which can be configured via software. A wide range of parameters are configurable in FPGA side of the proposed simulator, and the software side is implemented on an embedded soft-core processor. We transfer some parts of simulator, such as Traffic Generators (TGs) and Traffic Receptors (TRs), to software side without any degradation in simulation speed. Moreover, we implement a dual-clock architecture as an innovation in virtualization methodology, which is also capable to share idle time-slots, which helps not only simulate bigger NoCs, but also reduce simulation time drastically. Also, by employing a traffic aggregator architecture, AdapNoC provides table-based adaptive routing algorithm as a configurable parameter in router microarchitecture. We evaluate simulation time of AdapNoC by using Xilinx Virtex-6 XC6VLX240T, and demonstrate 53x-180x speed-up against BOOKSIM. Also, due to our proposed virtualization, and TGs and TRs migration to software side, we can implement a 64-node non-virtualized or a 1024-node virtualized mesh network in only %72 of Xilinx Virtex-6 XC6VLX240T resources.

关键词： field programmable gate arrays Routing Software Virtualization Computer architecture Adaptation models Time division multiple access

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Relational query processing on OpenCL-based FPGAs

Relational query processing on OpenCL-based FPGAs

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international conference on field programmable logic and applications

作者： Zeke Wang Johns Paul Hui Yan Cheah Bingsheng He Wei Zhang NTU Singapore NUS Singapore HKUST Hong Kong

the release of OpenCL support for FPGAs represents a significant improvement in extending database applications to the reconfigurable domain. Taking advantage of the programmability offered by the OpenCL HLS tool, an OpenCL database can be easily ported and re-designed for FPGAs. A single SQL query in these database systems usually consists of multiple operators, and each one of these operators in turn consists of multiple OpenCL kernels. Due to the specific properties of FPGAs, each OpenCL kernel can have different FPGA-specific optimization combinations, in terms of CU (compute unit) and SIMD (kernel vectorization), which are critical to the overall performance of query processing. Due to the resource limitation of an FPGA image, our query plan also considers the possibility of using multiple FPGA images. In this paper, we propose an FPGA-specific cost model to determine the optimal query plan in less than one minute. In particular, the FPGA synthesis time is significantly reduced by avoiding the need to evaluate all the feasible query plans on real FPGAs. Our cost model has two components: unit cost and optimal query plan generation. the first component generates multiple (unit cost, resource utilization) pairs for each kernel. the second component employs a dynamic programming approach to generate the optimal query plan which considers the possibility of using multiple FPGA images. the experiments show that 1) our cost model can accurately predict the performance of each feasible query plan for the input query, and can guide the optimal query plan generation, 2) our optimized query plan achieves a performance speedup 1.5×-4× over the state-of-the-art query processing on OpenCL-based FPGAs.

关键词： field programmable gate arrays Kernel Optimization Query processing Resource management

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ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning

ParaFRo: A hybrid parallel FPGA router using fine grained sy...

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international conference on field programmable logic and applications

作者： Chin Hau Hoo Yajun Ha Akash Kumar Department of Electrical & Computer Engineering National University of Singapore Singapore Institute for Infocomm Research (I2R) A*STAR Singapore Technische Universität Dresden Center for Advancing Electronics Dresden Germany

Routing of nets is one of the most time-consuming steps in the FPGA design flow. While existing works have described ways of accelerating the process through parallelization, they are not scalable. In this paper, we propose ParaFRo, a two-phase hybrid parallel FPGA router using fine-grained synchronization and partitioning. the first phase of the router aims to exploit the maximum parallelism available by routing nets while minimizing load imbalance. Instead of resolving contention with expensive software transactional memory, synchronization among threads is realized using lightweight spin mutexes. In the case where the algorithm detects that convergence is not possible in phase one, it transitions into phase two where convergence is prioritized over maximum parallelism. To achieve convergence, each thread in phase two routes only congested nets that have been assigned to it by a partitioner. the partitioner aims to reduce the contention among threads at the cost of an unbalanced load. In addition, periodic rip up of the entire route tree is employed to break the algorithm out from a local minimum. When only congested nets are rerouted, ParaFRo with 8 threads achieves an average speedup of 26.2× relative to VTR. In contrast, existing works managed to obtain an average speedup of up to 9.42× with 8 threads. Besides, ParaFRo is able to maintain the high speedups while producing similar quality of result as VTR in terms of critical path delay. Finally, the quality of result is relatively independent of the number of the threads.

关键词： Routing field programmable gate arrays Program processors Partitioning algorithms Parallel processing Algorithm design and analysis Synchronization

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