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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1847 条记录，以下是711-720 订阅

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Novel lightweight FF-APUF design for FPGA

Novel lightweight FF-APUF design for FPGA

引用

IEEE international SOC conference

作者： Chongyan Gu Yijun Cui Neil Hanley Máire O'Neill CSIT Queen's University Belfast Belfast U.K. Nanjing University of Aeronautics and Astronautics Nanjing China

ISBN: (纸本)9781509013685

Physical unclonable functions (PUFs), are a new type of physical security primitive which enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). Due to their flexibility and lower time to market, FPGAs are increasingly used for many applications. Arbiter PUFs (APUFs) are among the most widely studied PUF designs. However, they often suffer from poor uniqueness and reliability characteristics, are difficult to implement in FPGAs and consume excessive FPGA resources. To address these problems, a new Flip-flop based APUF (FF-APUF) design is proposed that offers a compact architecture, combined with strong uniqueness and good reliability. It is specifically designed for FPGAs. the proposed work is verified on a low-cost Nexys4 board based on the latest 28 nm technology Xilinx Artix-7 FPGA. the proposed FF-APUF circuit for generating a 1-bit response consumes only 44 slices, which is a saving of more than 66% in hardware resources over previous related research. Moreover, experimental results show improvements in both uniqueness and reliability. In particular, the expected uniqueness of the response bits is 40% on FPGA, which significantly improves upon a uniqueness of 9% achieved in previous work.

关键词： Reliability logic gates field programmable gate arrays Latches

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Reconfigurable analog classifier for knee-joint rehabilitation

Reconfigurable analog classifier for knee-joint rehabilitati...

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Annual international conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

作者： Sahil Shah Hakan Toreyin Omer T. Inan Jennifer Hasler School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta Georgia

ISBN: (纸本)9781457702198

We present a System-On-Chip field programmable Analog Array (FPAA) for analyzing and processing the signals off an accelerometer for a wearable joint health assessment device. FPAAs have been shown to compute with an efficiency of 1000 times, as well as area efficiencies of 100 times, more than digital solutions. this work presents a low power signal processing system which allows us to extract features from the output of the accelerometer. these features are used by the classifier, implemented using a vector matrix multiplication and a two output 1-winner-take-all, to detect flexion and extension cycles in the subject. the compiled design consumes 0.636 μW of power for the front end analog signal processing chain where as the single layer classifier uses 13 μW of power. thus the system is highly suitable for wearable applications where power consumption is a major concern. the current FPAA is fabricated in a 0.35 μm CMOS process and is operated at a power supply of 2.5 volts. the Gm-C filters and other circuits are operated in the subthreshold regime of the transistor to obtain the highest transconductance to current ratio offered by the process.

关键词： field programmable analog arrays Accelerometers Virtual machine monitors Feature extraction Band-pass filters logic gates

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A Flexible Profiling Sub-System for Reconfigurable logic Architectures

A Flexible Profiling Sub-System for Reconfigurable Logic Arc...

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Euromicro conference on Parallel, Distributed and Network-Based Processing

作者： G. Valente V. Muttillo L. Pomante F. Federici M. Faccio A. Moro S. Ferri C. Tieri DEWS Center of Excellence Università Degli Studi Dell'Aquila L'Aquila Italy

In recent years, embedded applications have been characterized by increasingly stringent requirements, both from functional and non-functional point of view. this led to the adoption of complex hardware platforms (multi-core and many-core architectures), able to guarantee high computational power with low energy consumption and reduced footprint. An efficient characterization of these platforms can be problematic, given the large number of hardware resources and the complexity of software applications. For this reason, the need for a runtime analysis support should be taken in account during the design phase (a design "for monitorability"). this paper introduces "Adaptive Profiling Hardware Sub-system" (AIPHS), a hardware profiling tool supporting the development of runtime monitorable systems. Two different multicore platforms are considered in order to evaluate AIPHS functionalities: an asymmetric dual-MicroBlaze system and a quad-Leon3 system supporting symmetric multiprocessing.

关键词： FPGAs Leon3 MicroBlaze Multi-core architectures OpenMP Profiling core construction symmetric multiprocessor Reconfigurable logic field programmable gate arrays ARCHITECTURE hardware resource applications software low energy consumption computational power Platform design phases Runtime

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Exploring static and dynamic flash-based FPGA design topologies

Exploring static and dynamic flash-based FPGA design topolog...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Monther Abusultan Sunil P Khatri ECE Department Texas A&M University College Station TX

field programmable gate arrays (FPGAs) are the implementation platform of choice when it comes to design flexibility. However, SRAM-based FPGAs suffer from high power consumption, prolonged boot delays (due to the volatility of the configuration bits), and a significant area overhead (due to the use of 5T SRAM cells for the configuration bits). Floating gate (flash) based FPGAs can avert these problems. this paper presents a study of flash-based FPGA designs (both static and dynamic), and presents the tradeoff of delay, power dissipation and energy consumption of the various designs. Our work differs from previously proposed flash-based FPGAs, since we embed the flash transistors (which store the configuration bits) directly within the logic and interconnect fabrics. We also present a detailed description of how the programming of the configuration bits is accomplished. Our delay and power estimates are derived from circuit level simulations. Our proposed static flash-based LUT structure yields 10% faster operation, 12% lower dynamic power dissipation, 21% lower energy consumption and 29% lower static power dissipation compared to a traditional SRAM-based LUT. We also show that, for high performance applications, a dynamic flash-based LUT can achieve further performance improvements (32% lower delay) with higher energy consumption (37% higher) compared to an SRAM-based LUT. We also show that a flash-based interconnect structure provides 89% lower delay and 71% lower overall power consumption compared to the traditional interconnect structure used in SRAM-based FPGAs.

关键词： field programmable gate arrays Table lookup logic gates Transistors Delays Nonvolatile memory Integrated circuit interconnections

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FPGA Implementation of Iris Recognition Based on Fast DCT Coding 25

FPGA Implementation of Iris Recognition Based on Fast DCT Co...

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25th international conference on Computer theory and applications, ICCTA 2015

作者： Gad, Ramadan Zorkany, M. El-Fishawy, Nawal El-Sayed, Ayman Menoufia University Faculty of Electronic Engineering Computer Science and Engineering Dept. Egypt National Telecommunication Institute Electronic and Communication Engineering Dept. Egypt

ISBN: (纸本)9781509002177

Iris is a touch-less automated real-time biometric system for user authentication. Most iris recognition approaches suffer from high cost, long development times, power consumption, and computationally intensive. Extracting valuable features from iris is computational burden, computational time, and limited memory storage. Classification of irises is most time consuming phase, repeated in recognition. In addition, general purpose systems are low speed and not portable solution. In this paper, off-line iris approach implemented on PC and hardware. Both Fast Discrete Cosine Transform (FDCT)-based feature extraction and Hamming Distance for matching stages are synthesized and implemented using low-cost Xilinx Spartan-3E FPGA chip. Simulation and implementation results indicate that the proposed solution improved the execution time with equivalent accuracy and error rates achieved by computer solution. Iris recognition based on FDCT system is more reliable, more saving in computations cost, small size, and good interclass separation in minimum time. © 2015 IEEE.

关键词： field programmable gate arrays (FPGA)

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Performance analysis of transistor-based circuits through TAMAMS Web: From bulk to molecular devices

Performance analysis of transistor-based circuits through TA...

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international conference on Electronic Devices, Systems and applications (ICEDSA)

作者： Izhar Hussain Fabrizio Riente Massimo Ruo Roch Gianluca Piccinini Mariagrazia Graziano Department of Electronics and Telecommunications Politecnico di Torino Italy

ISBN: (纸本)9781509053070

To meet the challenges associated with transistor scaling and short channel devices, the structure of MOS devices has undergone an incredible evolution. From Bulk devices, technology has shifted through Silicon-On-Insulator (SOI) devices, reaching now FinFET transistors, the next steps in the evolutionary path are represented by Gate-All-Around (GAA) and Molecular Transistors. Using analytical compact models for standard (BULK, SOI, FinFET) and emerging devices (GAA, Molecular FET (MOLFET)), it is possible to predict the system level performance of future NANO electronic circuits. In this work, we show how circuit's performance can be predicted and analyzed at system level using our tool, TAMTAMS Web. Starting from Bulk transistors down to a nanometer scale Molecular FET, TAMTAMS Web incorporates models to analyze device quantities (Drive current, Subthresold current...) up to system level. We have developed a compact model of Virtex 4 FPGA CLB block that is used as benchmark. the work here presented not only highlights the potentialities of TAMTAMS, but it also provides useful hints on the evolution of transistor based technology.

关键词： Transistors logic gates field programmable gate arrays Gallium arsenide Semiconductor device modeling Integrated circuit modeling Performance evaluation

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High-level FPGA logic synthesis from .NET programs for software developers

High-level FPGA logic synthesis from .NET programs for softw...

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international conference on field programmable logic and applications

作者： Zoltán Lehóczky Richárd Tóth Krisztián Somogyi Lombiq Technologies Ltd Budapest Hungary

FPGA circuit design, and thus the unique computing power of FPGAs is currently mostly only accessible to experts working in the field. the Hastlayer project aims to give a tool to software developers familiar with the .NET platform to automatically transform performance-critical parts of their programs into seamlessly usable FPGA-implemented hardware, yielding faster program execution and lower power consumption.

关键词： Software field programmable gate arrays Hardware Acceleration Computer languages Artificial intelligence Image processing

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Design and simulation tools for Embedded NOCs on FPGAs

Design and simulation tools for Embedded NOCs on FPGAs

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international conference on field programmable logic and applications

作者： Mohamed S. Abdelfattah Andrew Bitar Ange Yaghi Vaughn Betz Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada

We propose embedding hard NoCs on FPGAs to improve system-level communication as detailed in our previous studies [1-6]. this demo paper outlines the three main design and simulation tools that we have been using to e... 详细信息

关键词： field programmable gate arrays Measurement Ports (Computers) Fabrics XML Computational modeling Bandwidth

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Review of NoC-Based FPGAs Architectures 5

Review of NoC-Based FPGAs Architectures

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5th international conference on Energy Aware Computing Systems & applications (ICEAC)

作者： Salaheldin, Alaa Abdallah, Karim Gamal, Noha Mostafa, Hassan Cairo Univ Elect & Commun Engn Dept Giza 12613 Egypt AUC Ctr Nanoelect & Devices New Cairo 11835 Egypt Zewail City Sci & Technol New Cairo 11835 Egypt

ISBN: (纸本)9781479917723

Nowadays, FPGAs serve as fields programmable Systems on Chip (FPSoC) and are widely used to implement computationally intensive world applications. As the number of components in FPSoCs increases, the interconnect schemes based on Network on Chip (NoC) approach are increasingly used to overcome the problems of traditional bus based and point-to-point interconnect scheme. In this paper, we review several designs based on their contributions, architectures, implementations and future works. We also made our comparison between three of these routes to analyze the effect of varying the number of Virtual Channels (VCs), flit data width and buffer depth on the operating frequency, logic Look-Up Tables (LUTs) and registers to help choosing the appropriate NoC based on system requirements.

关键词： field programmable gate arrays Network topology Ports (Computers) Registers Routing Table lookup field programmable gate arrays Table lookup Registers Network topology Network routing ARCHITECTURE system requirements

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A framework for integrated monitoring of real-time embedded SoC

A framework for integrated monitoring of real-time embedded ...

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international conference on field programmable logic and applications

作者： Giacomo Valente Department of Information Engineering Computer Science and Mathematics L'Aquila Italy

the presented Ph.D. work deals with the development of a framework to support the design of embedded systems. In particular, it focuses on the development of a unobtrusive profiling system to support, at run-time, both the definition of the best execution platform and its resource optimization. the final goal is the definition of a framework exploiting reconfigurable logic, based on monitoring actions and run-time decisions. the profiling system under development and its high portability toward different architectures, representing current status of Ph.D. work, are described. Planned future steps, including benchmarking by means of industrial applications, are illustrated.

关键词： Monitoring Embedded systems Optimization Hardware Power demand field programmable gate arrays Runtime

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