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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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A software configurable coprocessor-based state-space controller

A software configurable coprocessor-based state-space contro...

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international conference on field programmable logic and applications

作者： Aaron Mills Pei Zhang Sudhanshu Vyas Joseph Zambreno Phillip H. Jones Iowa State University Ames Iowa USA

We present a software configurable coprocessor-based state-space controller that can control physical processes representable by a linear state-space model. Our proposed architecture has distinct advantages over purely software or purely hardware approaches. It differs from other hardware controllers in that it is not hardwired to control one or a small range of plant types (e.g. only electric motors). Via software, an embedded systems engineer can easily reconfigure the controller to suit a wide range of controls applications that can be represented as a state-space linear model. Additionally, we introduce a novel design methodology to help bridge the gap between controls and embedded system engineering. Control of the well-understood inverted pendulum on a cart is used as an illustrative example of how the proposed hardware accelerator architecture supports our envisioned design methodology for helping bridge the gap between controls and embedded software engineering.

关键词： Software Hardware field programmable gate arrays Computational modeling Random access memory Mathematical model Delays

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rrBox: A remote dynamically reconfigurable network processing middlebox

rrBox: A remote dynamically reconfigurable network processin...

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international conference on field programmable logic and applications

作者： Tze Hon Tan Chia Yee Ooi M. N. Marsono Faculty of Electrical Engineering Universiti Teknologi Malaysia Skudai Johor Malaysia Malaysia-Japan International Institute of Technology Universiti Teknologi Malaysia Kuala Lumpur KL Malaysia

this paper presents a remote dynamically reconfigurable network processing middlebox. the packet forwarding and other network functional circuitry in the data plane of this middlebox can be updated remotely at run-time by client computer through 1Gbps Ethernet connection. the proposed architecture is stand-alone and uses a customized reconfiguration controller and Internal Configuration Access Port to achieve dynamic reconfiguration. Data plane functional update enables feature extension, customization, optimization and patch on design flaws, which is crucial for application to cope with the changes in operational constraints. A case study on network protection using this platform is included to verify the developed platform and to demonstrate the benefits of remote functional updates. Based on experimental result, the implemented middlebox achieved roughly 350Mbps reconfiguration throughput, which is beneficial in mass remote update with low device downtime for functional update.

关键词： Middleboxes Ports (Computers) Payloads Computer architecture throughput Hardware field programmable gate arrays

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Power-efficient range-match-based packet classification on FPGA

Power-efficient range-match-based packet classification on F...

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international conference on field programmable logic and applications

作者： Yun R. Qu Viktor K. Prasanna Ming Hsieh Department of Electrical Engineering University of Southern California Los Angeles CA

Packet classification is a kernel application performed at network routers. Many classification engines are optimized for prefix and exact match, while a range-to-prefix translation can lead to rule set expansion. Under limited power budget, it is challenging to achieve high classification throughput. In this paper, we present a high-performance and power-efficient packet classification engine on FPGA. We construct a modular Processing Element (PE); each PE compares a stride of the input packet header against a stride of a range boundary. We concatenate multiple PEs into a systolic array. Efficient power optimization techniques including self-enabled power gating and entropy-based scheduling are explored on our architecture. Experimental results show that, for 4K 15-field rule sets, our prototype on a state-of-the-art FPGA can achieve 250 Million Packets Per Second (MPPS) throughput. Using the proposed power optimization techniques, our classification engine consumes 30% of the power without sacrificing the throughput.

关键词： field programmable gate arrays Clocks Entropy throughput Engines Arrays Optimization

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Data protection using recursive inverse function

Data protection using recursive inverse function

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international conference on field programmable logic and applications

作者： Teng Xu Hongxiang Gu Miodrag Potkonjak Computer Science Department University of California Los Angeles

Data security and privacy have emerged to become an important issue in various types of applications. Although many cryptographic cyphers are proposed to leverage the issue, they normally suffer from the problems of either requiring large power/bandwidth consumption or employing linear system which is easy to break. To solve the problem of traditional cyphers, we have proposed a new hardware security primitive: recursive inverse function (RIF) designed on the field-programmable gate array (FPGA). the RIF takes advantage of a pair of inverse functions, building a recursive scheme for message encryption and decryption. the inverse functions are defined as a pair of functions where each function implements a mapping being inverse to the mapping of the other function. On the top of it, the recursive structure guarantees the input-output mapping to be statistically extremely hard to predict. the RIF can be easily implemented using hierarchical lookup-table (LUT) structures with low delay and power overhead. Using our proposed RIF structure, we have demonstrated how the RIF can be incorporated into a processor design to enable the data protection. Finally, we implement our scheme on a Xilinx Spartan-6 FPGA device to analyze the performance and the overhead.

关键词： Table lookup Encryption Data protection field programmable gate arrays Ciphers

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ParaLaR: A parallel FPGA router based on Lagrangian relaxation

ParaLaR: A parallel FPGA router based on Lagrangian relaxati...

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international conference on field programmable logic and applications

作者： Chin Hau Hoo Akash Kumar Yajun Ha Department of Electrical and Computer Engineering National University of Singapore Singapore

Routing of nets is one of the most time consuming steps in the FPGA design flow. While existing works have described ways of accelerating the process through parallelization, they are not scalable. In this paper, we propose a scalable way of parallelizing the routing algorithm through Lagrangian relaxation. the FPGA routing problem is formulated as a linear programming problem, and the channel width constraints, which limit the amount of parallelism, are relaxed by incorporating them into the objective function. the result of the relaxation yields independent sub-problems that we solve using minimum Steiner tree algorithms. Our approach outperforms the state-of-the-art FPGA parallel router by producing an average self-relative speedup of 7.05X with 8 threads, reduces the total wire length by 22.4% on average and has similar channel width requirements as VPR, albeit at the cost of 7.5% longer critical path. Another advantage of our algorithm is that the number of threads and the order in which the nets are routed has totally no impact on the quality of result.

关键词： Routing Steiner trees field programmable gate arrays Algorithm design and analysis Linear programming Wires Parallel processing

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Building a distributed key-value store with FPGA-based microservers

Building a distributed key-value store with FPGA-based micro...

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international conference on field programmable logic and applications

作者： Zsolt István David Sidler Gustavo Alonso Dept. of Computer Science Systems Group ETH Zurich Switzerland

Energy efficiency is one of the major challenges in datacenters, and a promising way to tackle it are microservers. these scaled down machines with smaller CPUs, less peripherals and tighter integration improve energy efficiency, but often at the expense of lower performance. In this work we explore the tailoring of standard software components to specialized hardware as a way to get the energy efficiency of microservers without compromising performance. Our specialized microserver implements memcached, a common component in many web stacks, on a cluster of FPGAs. the design explores aspects such as pipelining techniques, tight integration with the network stack, dealing with the memory bottleneck, and shows how to build a complete system out of individual microservers. To our knowledge this is the first stand-alone FPGA-based solution that can be used as a drop-in replacement for the software version. Beyond the per-node performance, in this demo we focus on the replication and the integration aspects of our system. We run a common benchmark on a PostgreSQL database with a two-node deployment of FPGAs acting as a cache for query results.

关键词： Hardware field programmable gate arrays Benchmark testing Software Workstations Pipeline processing Databases

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Generating FPGA accelerators for chemical similarity assessment

Generating FPGA accelerators for chemical similarity assessm...

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international conference on field programmable logic and applications

作者： Nikolaos Alachiotis Dept. of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA

Numerical measures of similarity/distance between objects represented by binary vectors are common in a wide range of disciplines. Searching in large-scale chemical databases requires billions of comparisons between molecules that are represented by binary fingerprints to capture the atomic structure. the performance bottleneck here is the enumeration of set bits in vectors (population count). Due to the discrete representation, similarity measures between binary fingerprints should fit well to FPGAs. We present an architecture to accelerate binary similarity assessment, evaluate various design points, and compare performance to highly optimized CPU and GPU implementations. We implement an RTL generation software, SimGenRTL, to generate accelerators of various sizes based on the proposed architecture. We find that accelerators with fewer and wider population counters allow better distribution of the hardware resources, outperforming significantly accelerators with more and narrower bit-enumeration components. SimGenRTL is available for download to allow rapid design space exploration of the computational core ahead of a full custom system implementation.

关键词： Sociology Statistics Computer architecture field programmable gate arrays Databases Chemicals Graphics processing units

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Static hardware task placement on multi-context FPGA using hybrid genetic algorithm

Static hardware task placement on multi-context FPGA using h...

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international conference on field programmable logic and applications

作者： Hao Liang Sharad Sinha Rakesh Warrier Wei Zhang Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong School of Computer Engineering Nanyang Technological University Singapore

field programmable Gate Arrays (FPGAs) are becoming pervasive in various kinds of computationally demanding applications. Working in a tightly coupled processor-coprocessor architecture, FPGAs are often anticipated to accelerate multiple fine-grained or coarse-grained tasks simultaneously. Single-context FPGAs are commonly used in such systems. With the recent development of emerging memory technologies, multi-context FPGAs that support dynamic reconfiguration with high-density non-volatile memories become feasible. Compared to single-context FPGAs, multi-context FPGAs are able to accelerate significantly more tasks with only moderate area and power overhead. However, the best way to utilize the computation capacity advantage of multi-context FPGAs for hardware task mapping remains an interesting and unexploited problem. In this paper, we first propose the framework of a processor-coprocessor architecture with multi-context FPGA as the coprocessor for multiple-task acceleration. Under the framework, a hybrid placement strategy based on genetic and greedy algorithms is proposed to efficiently place a set of tasks onto the multi-context FPGA to achieve the best logic capacity utilization. Experiments on real and synthetic benchmarks demonstrate the efficiency of the proposed algorithm compared with other general approaches.

关键词： Kernel field programmable gate arrays Context Hardware Computer architecture Genetic algorithms Acceleration

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SPINE: From C loop-nests to highly efficient accelerators using Algorithmic Species

SPINE: From C loop-nests to highly efficient accelerators us...

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international conference on field programmable logic and applications

作者： Mark Wijtvliet Shakith Fernando Henk Corporaal Department of Electrical Engineering Eindhoven University of Technology The Netherlands

In modern embedded systems, heterogeneous architectures are crucial in achieving desired performance requirements under area and energy constraints. Many of these systems combine a multi-processor system-on-chip and a field programmable Gate Array to enable hardware acceleration. Although the introduction of High-Level Synthesis significantly reduced the complexity of utilizing these systems, a programmer is still required to have expert knowledge of both the High-Level Synthesis tool and the target hardware and to perform time consuming manual iterations to achieve efficient implementations. In this paper we present SPINE, a design flow for automatic generation of efficient hardware accelerators based on Algorithmic Species. SPINE allows the designer to focus on the algorithm by automatically applying hardware specific optimizations and parallelization techniques to the design. As a case study, we present a design space exploration of nine different loop-nests used in image processing kernels and show how SPINE rapidly generates multiple area-performance trade-offs. Furthermore, we compare our results the state of the art and show that SPINE is a promising direction for accelerator generation as the average performance and area improvement with SPINE are respectively 107% and 75% over the state of the art.

关键词： Kernel Skeleton Hardware design languages Hardware Algorithm design and analysis field programmable gate arrays Manuals

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An efficient reconfigurable architecture by characterizing most frequent logic functions

An efficient reconfigurable architecture by characterizing m...

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international conference on field programmable logic and applications

作者： Iman Ahmadpour Behnam Khaleghi Hossein Asadi Department of Computer Engineering Sharif University of Technology Tehran

Generous flexibility of Look-Up Tables (LUTs) in implementing arbitrary functions comes with significant performance and area overheads compared with their Application-Specific Integrated Circuit (ASIC) equivalent. One approach to alleviate such overheads is to use less flexible logic elements capable to implement majority of logic functions. In this paper, we first investigate the most frequently used functions in standard benchmarks and then design a set of less-flexible but area-efficient logic cells, called Hard logics (HL). Since higher input functions have diverse classes, we leverage Shannon decomposition to break them into smaller ones to either reduce the HL design space complexity or attain asymmetric low input functions. A heterogeneous LUT-HL architecture and a mapping scheme are also proposed to attain maximum logic resource usage. Experimental results on MCNC benchmarks demonstrate that the proposed architecture reduces area-delay product by 13% and 36% as compared to LUT4 and LUT6 based FPGAs, respectively. Considering the same area budget, our proposed architecture improves performance by 17% and 2% as compared to LUT4 and LUT6 based FPGAs.

关键词： Delays Benchmark testing Table lookup Silicon Routing

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