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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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Wotan: A tool for rapid evaluation of FPGA architecture routability without benchmarks

Wotan: A tool for rapid evaluation of FPGA architecture rout...

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international conference on field programmable logic and applications

作者： Oleg Petelin Vaughn Betz Department of Electrical and Computer Engineering University of Toronto Toronto Canada

FPGA routing architectures consist of routing wires and programmable switches which together account for a significant portion of the fabric delay and area. Routing architectures have traditionally been evaluated using a full CAD flow with a suite of benchmark circuits. While the results of such a flow can be accurate, CAD tools are often tuned to a specific architecture type and can take a long time to run which prohibits quick exploration of different architectures early in the design process. In this paper we present an alternative approach that quickly estimates routability for a wide range of architectures without the use of benchmark circuits. Our new routability predictor first assigns congestion probabilities to the architecture's routing resources based on demand estimates found via efficient path enumeration through the routing graph. Next, we compute the probabilities of successfully routing different source/sink connections and finally we combine them to assign an overall routability score. We describe our predictor and present routability estimates for a range of 6-LUT and 4-LUT architectures, showing reasonable agreement with routability results from the full VPR CAD flow in much less CPU time.

关键词： Routing field programmable gate arrays Design automation Wires Benchmark testing Reliability Pins

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FPGA Autonomous logic Analyzer Using Innovative BERC Filter Optimization 7

FPGA Autonomous Logic Analyzer Using Innovative BERC Filter ...

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7th international conference on Electronics, Computers and Artificial Intelligence (ECAI)

作者： Ioan, Aleodor Daniel Ignat, Mihael Cristian Gh Asachi Tech Univ Automat Control & Appl Informat Dept Iasi Romania Digilent RO SRL Dept Res & Dev Cluj Napoca Romania

ISBN: (纸本)9781467366472

In this work is presented a new hardware implementation of a high speed logic analyzer inside FPGA (field programmable Gate Array) chips that is fully autonomous by directly driving a VGA compatible computer monitor for multiple signals display. It can be used as a very low cost and real time testing instrument for both external hardware and internal FPGA designs. the implementation is optimized at schematic level by proposing an innovative solution called BERC (Begin-End-Reset-Cell) as hardware digital filter that eliminates any magnitude or equality comparators usually inferred from hardware description languages to decode the counters signals. this new technique is much more efficient because it reduces the combinatorial resources to a minimum, and it can be generalized for all kind of video interfaces.

关键词： logic analyzer FPGA implementation VGA interface line mapped BERC filter optimization

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Hoplite: Building austere overlay NoCs for FPGAs

Hoplite: Building austere overlay NoCs for FPGAs

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international conference on field programmable logic and applications

作者： Nachiket Kapre Jan Gray Nanyang Technological University Singapore Gray Research LLC Bellevue WA

Customized unidirectional, bufferless, deflection-routed torus networks can outperform classic, bidirectional, buffered mesh networks for single-flit-oriented FPGA applications by as much as 1.5× (best achievable throughputs for a 10×10 system) or 2.5× (allocating same FPGA resources to both NoCs) for uniform random traffic. We present Hoplite, an efficient, lightweight, fast FPGA overlay NoC that is designed to be small and compact by (1) eliminating input buffers, and (2) reducing the cost of switch crossbar that have traditionally limited speeds and imposed heavy resource costs in conventional FPGA overlay NoCs. We implement bufferless deflection routing cheaply, requiring the generation of only output multiplexer controls and no backpressure handshakes. Additionally, we use directional channels that help reduce crossbar cost by restricting the number of inputs to the crossbar to three instead of four. When compared to buffered mesh switches, FPGA-based deflection routers are ≈3.5× smaller (HLS-generated switch) and 2.5× faster (clock period) for 32b payloads. In a separate experiment, we hand-crafted a prototype RTL version of our switch with RLOCS that requires only 60 LUTs and 100 FFs per router and runs at 2.9 ns.

关键词： Switches field programmable gate arrays Routing Table lookup Payloads Fabrics Ports (Computers)

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Over effective hard real-time hardware tasks scheduling and allocation

Over effective hard real-time hardware tasks scheduling and ...

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international conference on field programmable logic and applications

作者： Zakarya Guettatfi Omar Kermia Abdelhakim Khouas CDTA University M'Hamed Bougara of Boumerdes Algiers Algeria

Hardware task scheduling and allocation at runtime increase the chip utilization ration and improve the system performance by exploring partially reconfigurable field-programmable Gate Arrays (FPGAs). Partial reconfiguration enables to change all or parts of the system hardware during the execution, in order to gain efficiency over static system. Hardware-software real-time operating systems (RTOS) are often used to develop applications for embedded systems with complex time and resource constraints. In hard real-time systems, failure to meet its time constraints may lead to disastrous consequences. However, reconfigurable systems still lack an OS foundation that covers both software and hardware tasks dor hard real-time requirements. the objective of this work is to formalize an abstraction layer combining safety-critical RTOS, like SafeRTOS, μC/OS-II or Xenomai. on the one hand. On the other hand, we give some leads on hardware tasks scheduling and allocation effective algorithms in order to manage a hard real time software-hardware configuration. this paper presents, succinctly, a preliminary work which can allow the utilization of a safety-critical RTOS for managing software tasks, while hardware tasks are relocatabled and multi-shaped through GoAhead.

关键词： Hardware Real-time systems Software field programmable gate arrays Shape Job shop scheduling

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A technology mapper for depth-constrained FPGA logic cells

A technology mapper for depth-constrained FPGA logic cells

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international conference on field programmable logic and applications

作者： Zhenghong Jiang Grace Zgheib Colin Yu Lin David Novo Zhihong Huang Liqun Yang Haigang Yang Paolo Ienne System on Programmable Chip Research Department Institute of Electronics Chinese Academy of Sciences Beijing China Ecole Polytechnique Federale de Lausanne (EPFL) School of Computer and Communication Sciences Lausanne Switzerland

In the last decade, progress in logic synthesis has brought about new advantageous circuit representations. these representations, such as And-Inverter Graphs in the ubiquitous open-source synthesizer ABC, have inspired new designs of field programmable Gate Arrays (FPGAs), which, instead of using Look-Up Tables (LUTs), mimic the topology of the circuit representation in the basic logic cells. More recent examples are Majority-Inverter Graphs, another uniform representation which has triggered considerable interest in synthesis and which naturally suggests new logic cells. Yet, in this paper we observe how naïvely adapting technology mapping solutions for classic LUT-based FPGAs to these new architectures incurs severe shortcomings. the key issue is that LUTs are inherently input-constrained (the logic function they implement is irrelevant) and have generally a single output; on the other hand, logic cells made of uniform networks of some fundamental logic function (e.g., And-Invert) are constrained in terms of logic depth and multiple outputs are an integral feature. We introduce novel and effective solutions to address these differences; the result is a highly versatile mapper - thus enabling further research in these new architectures - with a significantly better performance than what is described in literature for one such architecture. Specifically, when we compare with the state of the art on one sample architecture, we obtain a significant decrease in area (on average 18% over several benchmarks) while also improving slightly the critical path (a reduction of 3%).

关键词： Table lookup Delays field programmable gate arrays Linear programming Libraries logic gates

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Recursive pipelined genetic propagation for bilevel optimisation

Recursive pipelined genetic propagation for bilevel optimisa...

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international conference on field programmable logic and applications

作者： Shengjia Shao Liucheng Guo Ce Guo thomas C.P. Chau David B. thomas Wayne Luk Stephen Weston Department of Computing Department of Electrical and Electronic Engineering Maxeler Technologies Imperial College London

the bilevel optimisation problem (BLP) is a subclass of optimisation problems in which one of the constraints of an optimisation problem is another optimisation problem. BLP is widely used to model hierarchical decision making where the leader and the follower correspond to the upper level and lower level optimisation problem, respectively. In BLP, the optimal solutions to the lower level optimisation problem are the feasible solutions to the upper level problem, which makes it particularly difficult to solve. this paper proposes a novel hardware architecture known as Recursive Pipelined Genetic Propagation (RPGP), to solve BLP efficiently on FPGA. RPGP features a graph of genetic operation nodes which can be scaled to exploit hardware resources. In addition, the topology of the RPGP graph can be changed at run-time to escape from local optima. We evaluate the proposed architecture on an Altera Stratix-V FPGA, using a benchmark bilevel optimisation problem set. Our experimental results show that RPGP can achieve a significant speed-up against previous work.

关键词： Optimization field programmable gate arrays Genetic algorithms Genetics Linear programming Topology Switches

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A variable length hash method for faster short read mapping on FPGA

A variable length hash method for faster short read mapping ...

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international conference on field programmable logic and applications

作者： Yoko Sogabe Tsutomu Maruyama Systems and Information Engineering University of Tsukuba Ibaraki JAPAN Tsukuba Daigaku Tsukuba Ibaraki JP

Short read mapping is a process to align the short reads, which are fixed-length fragments of the target genome, to a given reference genome to identify the mutations in the target genome. Because of the rapid development of Next Generation Sequencing (NGS) technologies, faster short read mapping is required. In this paper, we propose a variable length hash method to further accelerate FPGA short read mapping systems. In the hash-based short read mapping algorithms, a fixed length sub-string of each short read, called seed, is used as the key. However, many different seeds are mapped into the same hash slots because of the high ununiformity of the human genome, and many fruitless key comparisons are performed. To equalize the slot size, we propose an optimized hash function that changes the bit masks adaptively. With this approach, it is possible to improve the performance of all FPGA short read mapping systems based on hash functions. the performance for the comparison in our FPGA system on a Xilinx XC7VX690T and XC6VLX240T can be improved two-times, and the total performance outperforms any existing FPGA systems.

关键词： Indexes Genomics Bioinformatics field programmable gate arrays Random access memory Accuracy Computers

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A run time interpretation approach for creating custom accelerators

A run time interpretation approach for creating custom accel...

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international conference on field programmable logic and applications

作者： Sen Ma Zeyad Aklah David Andrews Department of Computer Science and Computer Engineering University of Arkansas Fayetteville AR USA

the world of software development has the notion of just-in-time compilation, run time binary translation, and language interpretation. these dynamic run time techniques support increased code portability and designer productivity. there are no such equivalences to increase the productivity or portability of creating new hardware components within field programmable Gate Arrays (FPGAs). Instead, creating a new hardware component requires hardware design skills and the overhead of running through synthesis, place and route. If a change is made to even a single line of code, the synthesis, place and route steps must be repeated. In this paper we present a new approach that allows hardware accelerators to be built and run using compilation and run time interpretation. Our results show the approach can enable software programmers without any hardware skills to create hardware accelerators at productivity levels consistent with software development and compilation. the same accelerator can be compiled 100× faster than synthesis. Even though the approach is focused on productivity, our observed performance results are promising. Our initial application test cases show the same accelerator written by a software programmer and synthesized through Vivado HLS or written using our DSL and compiled within our approach achieves equivalent performance.

关键词： Software field programmable gate arrays Hardware Productivity Benchmark testing DSL Switches

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Automatic support for multi-module parallelism from computational patterns

Automatic support for multi-module parallelism from computat...

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international conference on field programmable logic and applications

作者： Nithin George HyoukJoong Lee David Novo Muhsen Owaida David Andrews Kunle Olukotun Paolo Ienne Ecole Polytechnique Federale de Lausanne (EPFL) School of Computer and Communication Sciences. Stanford University Pervasive Parallelism Laboratory Department of Computer Science and Computer Engineering. University of Arkansas

field programmable Gate Arrays (FPGAs) can be customized into application-specific architectures to achieve high performance and energy-efficiency. Unfortunately, they are yet to gain significant adoption by application developers due to their low-level programming model. Moreover, to obtain good performance in an FPGA design, one often needs to correctly parallelize computation and balance the computational throughput with the available data access bandwidth. To address the programming model problem, recent efforts have focused on composing applications out of parallel computational patterns, such as map, reduce, zipWith and foreach, and leveraging the properties of these patterns to generate highly parallel hardware modules capable of high performance. In this work, we focus on the problem of further improving the performance and show that we can utilize the knowledge of how data is consumed and produced by these computational patterns in conjunction with the information of the system architecture to automatically parallelize computations across multiple hardware modules. To achieve this, we automatically infer synchronization needs arising due to parallelization and generate a complete system that can obtain high performance for a given application. We evaluate our approach using seven applications from different domains and show that our automatically generated designs achieve performance improvements ranging from 1.8 to 9.4 times.

关键词： Kernel Hardware Synchronization Parallel processing field programmable gate arrays Optimization Bandwidth

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Scavenger: Automating the construction of application-optimized memory hierarchies

Scavenger: Automating the construction of application-optimi...

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international conference on field programmable logic and applications

作者： Hsin-Jung Yang Kermin Fleming Michael Adler Felix Winterstein Joel Emer CSAIL Massachusetts Institute of Technology SSG Intel Corporation Ground Station Systems Division European Space Agency NVIDIA Research

High-level abstractions separate algorithm design from platform implementation, allowing programmers to focus on algorithms while building increasingly complex systems. this separation also provides system programmers and compilers an opportunity to optimize platform services for each application. In FPGAs, this platform-level malleability extends to the memory system: unlike general-purpose processors, in which memory hardware is fixed at design time, the capacity, associativity, and topology of FPGA memory systems may all be tuned to improve application performance. Since application kernels often use few memory resources, substantial memory capacity may be available to the platform for use on behalf of the user program. In this work, we perform an initial exploration of methods for automating the construction of these application-specific memory hierarchies. Although exploiting spare resources can be beneficial, naïvely consuming all memory resources may cause frequency degradation. To relieve timing pressure in large BRAM structures, we provide microarchitectural techniques to trade memory latency for design frequency. We demonstrate, by examining both hand-assembled and HLS-compiled benchmarks, that our application-optimized memory system can improve pre-existing application runtime by 25% on average.

关键词： field programmable gate arrays Program processors System-on-chip Microarchitecture Memory management Random access memory Kernel

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