检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,813 篇 会议
30 篇 期刊文献
5 册 图书

馆藏范围

1,848 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,203 篇 工学
- 1,020 篇 计算机科学与技术...
- 707 篇 软件工程
- 388 篇 电气工程
- 186 篇 电子科学与技术（可...
- 62 篇 信息与通信工程
- 60 篇 控制科学与工程
- 26 篇 机械工程
- 25 篇 动力工程及工程热...
- 24 篇 建筑学
- 23 篇 仪器科学与技术
- 16 篇 土木工程
- 14 篇 生物工程
- 11 篇 核科学与技术
- 10 篇 材料科学与工程（可...
- 9 篇 光学工程
- 8 篇 生物医学工程（可授...
- 8 篇 安全科学与工程
- 6 篇 化学工程与技术
- 6 篇 交通运输工程
146 篇 理学
- 97 篇 数学
- 33 篇 物理学
- 16 篇 生物学
- 14 篇 系统科学
- 10 篇 统计学（可授理学、...
- 6 篇 化学
52 篇 管理学
- 39 篇 管理科学与工程(可...
- 17 篇 工商管理
- 15 篇 图书情报与档案管...
14 篇 法学
- 12 篇 社会学
9 篇 经济学
- 9 篇 应用经济学
8 篇 医学
6 篇 农学
4 篇 军事学
2 篇 教育学

主题

817 篇 field programmab...
670 篇 field programmab...
271 篇 hardware
155 篇 computer archite...
119 篇 logic gates
111 篇 table lookup
94 篇 clocks
83 篇 throughput
78 篇 random access me...
72 篇 routing
71 篇 acceleration
71 篇 software
66 篇 optimization
63 篇 kernel
62 篇 delays
52 篇 registers
52 篇 logic
49 篇 switches
46 篇 algorithm design...
45 篇 computational mo...

机构

15 篇 univ toronto dep...
9 篇 department of co...
9 篇 imperial coll lo...
8 篇 ecole polytech f...
7 篇 univ british col...
7 篇 school of comput...
7 篇 brigham young un...
7 篇 imperial coll lo...
7 篇 tokyo inst techn...
6 篇 univ tsukuba tsu...
6 篇 university of ch...
6 篇 department of el...
6 篇 univ warwick sch...
6 篇 xilinx inc san j...
5 篇 univ manchester ...
5 篇 department of el...
5 篇 univ toronto dep...
5 篇 swiss fed inst t...
5 篇 xilinx inc 2100 ...
5 篇 altera corp san ...

作者

33 篇 luk wayne
21 篇 maruyama tsutomu
16 篇 wayne luk
16 篇 koch dirk
12 篇 wilton steven j....
12 篇 betz vaughn
12 篇 ienne paolo
11 篇 fahmy suhaib a.
11 篇 cheung peter y. ...
10 篇 vaughn betz
9 篇 constantinides g...
8 篇 suhaib a. fahmy
8 篇 prasanna viktor ...
8 篇 chow paul
8 篇 glesner manfred
8 篇 amano hideharu
8 篇 akash kumar
7 篇 kapre nachiket
7 篇 alonso gustavo
7 篇 hutchings brad

语言

1,823 篇 英文
25 篇 其他
1 篇 中文

检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1848 条记录，以下是781-790 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Using island-style bi-directional intra-CLB routing in low-power FPGAs

Using island-style bi-directional intra-CLB routing in low-p...

引用

international conference on field programmable logic and applications

作者： Oluseyi Ayorinde He Qi Yu Huang Benton H. Calhoun Department of Electrical Engineering University of Virginia Charlottesville Virginia

Increased clustering in field programmable Gate Arrays (FPGAs) has shifted a larger fraction of the overall routing load into the configurable logic blocks (CLBs), reducing usage of the costly global interconnect. However, increases in CLB size introduce additional overheads inside CLBs, which can limit the savings gained by minimizing the global interconnect use, motivating more efficient intra-CLB routing. this paper explores different topologies for the intra-CLB connectivity and identifies how the optimal local-CLB interconnect changes for different FPGA architecture and circuit parameters. this work compares area, delay, and energy for two intra-CLB topologies: multiplexer-based routing and island-style bi-directional routing, similar to the global FPGA interconnect, but used inside the CLB (which we call a mini-FPGA). the mini-FPGA style of local CLB interconnect prove to be favorable for minimum-energy operation, as they can reduce transistor count by as much as 62%, and consume as much as 77.9% less energy. Multipexer-based CLBs have performance benefits by reducing delays by almost 3×. Multiplexer-based CLBs can consume less energy at nominal voltages, but only if additional measures are taken to limit power consumption in the multiplexers. A 130-nm CMOS test chip confirms that simulation results track measured data for mini-FPGA CLBs.

关键词： Multiplexing field programmable gate arrays Transistors Topology Delays Energy consumption Routing

来源：评论

学校读者我要写书评

暂无评论

Limits of FPGA acceleration of 3D Green's Function computation for geophysical applications

Limits of FPGA acceleration of 3D Green's Function computati...

引用

international conference on field programmable logic and applications

作者： Nachiket Kapre Jayakrishnan Selva Kumar Parjanya Gupta Sagar Masuti Sylvain Barbot School of Computer Engineering Nanyang Technological University Singapore Earth Observatory of Singapore Nanyang Technological University Singapore

FPGA-based accelerators can outperform multi-core, GPU and Xeon Phi based platforms by at as much as 2.8× for 3D Green's Function processing in geophysics while delivering superior energy efficiency. FPGAs can efficiently implement a complex mixture of compute patterns that include data-parallelism, reductions, dataflow and streaming computations using spatial parallelism to deliver these speedups and power benefits. Since 3D Green's Function is highly-parallel but communication bound, we optimize the FPGA implementation by considering loop restructuring and tiling optimizations to minimize and regularize off-chip accesses. Furthermore, we configure the FPGA to implement the key compute intensive kernels at double-precision as well as single-precision to exploit the uncertainty in measurements of earthquake monitoring sensors. For 512×512×512 problem size, the Xilinx SX475T (Maxeler MAX3) outperforms the fastest architecture by 1.1-1.4× (double-precision), 2.2-2.8× (single-precision) with 1.2× better energy efficiency.

关键词： field programmable gate arrays Green's function methods Graphics processing units three-dimensional displays Kernel Mathematical model Random access memory

来源：评论

学校读者我要写书评

暂无评论

Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference

Fast hierarchical implementation of sequential tree-reweight...

引用

international conference on field programmable logic and applications

作者： Skand Hurkat Jungwook Choi Eriko Nurvitadhi José F. Martínez Rob A. Rutenbar Computer Systems Laboratory Cornell University Ithaca NY USA Dept. of Electrical and Computer Engineering Intel Labs Hillsboro OR USA Dept. of Computer Science University of Illinois at Urbana-Champaign Urbana IL USA

Maximum a posteriori probability (MAP) inference on Markov random fields (MRF) is the basis of many computer vision applications. Sequential tree-reweighted belief propagation (TRW-S) has been shown to provide very good inference quality and strong convergence properties. However, software TRW-S solvers are slow due to the algorithm's high computational requirements. A state-of-the-art FPGA implementation has been developed recently, which delivers substantial speedup over software. In this paper, we improve upon the TRW-S algorithm by using a multi-level hierarchical MRF formulation. We demonstrate the benefits of Hierarchical-TRW-S over TRW-S, and incorporate the proposed improvements on a Convey HC-1 CPU-FPGA hybrid platform. Results using four Middlebury stereo vision benchmarks show a 21% to 53% reduction in inference time compared with the state-of-the-art TRW-S FPGA implementation. To the best of our knowledge, this is the fastest hardware implementation of TRW-S reported so far.

关键词： Convergence Benchmark testing Belief propagation Hardware Software algorithms field programmable gate arrays Inference algorithms

来源：评论

学校读者我要写书评

暂无评论

Domain-specific optimisation for the high-level synthesis of CellML-based simulation accelerators

Domain-specific optimisation for the high-level synthesis of...

引用

international conference on field programmable logic and applications

作者： Julian Oppermann Andreas Koch Ting Yu Oliver Sinnen Embedded Systems and Applications Group Technische Universität Darmstadt Germany Parallel and Reconfigurable Computing Group University of Auckland New Zealand

the simulation of biomedical models often requires the numerical integration of ordinary differential equation systems, a computationally intensive task that can be accelerated well by deeply-pipelined FPGA-based accelerators. Since the main design target is throughput, larger FPGA devices can easily be exploited by scaling-up the number of parallel datapath instances on a chip. To this end, reducing the area of each datapath becomes a key optimisation. High-level synthesis can be employed to generate custom simulation accelerators from standardised cell descriptions in CellML. In this work, we improve this process by inserting LLVM into the flow to pre-optimise the simulation models generated from CellML for hardware synthesis. this is achieved not only by the selective application of general-purpose optimisation passes, but also by adding new domain-specific optimisations, including unsafe floating-point transformations, to the optimisation flow. We investigate their effect on the quality-of-results and show that a novel strategy using our optimisations outperforms standard strategies, such as LLVM's -Oz (aggressive size reduction), when applied for hardware synthesis in 99 out of 146 example models. Our approach, which reduces area by up to 25%, leads to the smallest implementations for four models examined in detail, and allows a particularly complex cell model to fit on the target FPGA device for the first time.

关键词： Mathematical model Optimization Computational modeling Biological system modeling Numerical models Hardware field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

SysAlloc: A hardware manager for dynamic memory allocation in heterogeneous systems

SysAlloc: A hardware manager for dynamic memory allocation i...

引用

international conference on field programmable logic and applications

作者： Zeping Xue David B. thomas Department of Electrical and Electronic Engineering Imperial College London London UK

System-on-chip designs are increasingly complex and dynamic, with many IP cores, CPUs and off-chip Memories interconnected via shared buses. Static allocation of RAM resources requires designers to analyse the memory needs of each component, which can lead to poor memory efficiency, and is infeasible in a dynamically changing system. Dynamic memory allocation is one solution to this problem, but is usually only supported in software. We propose SysAlloc, a hardware-based dynamic memory allocation scheme for heterogeneous systems, which allows software and hardware to access a shared memory allocator, and allows dynamic memory allocation in the absence of software. Our allocation protocol is accessible to any client which can perform memory reads and writes over a shared bus, including software, RTL, and HLS clients, and can scale at run-time to any number of active clients. In contrast to existing designs, the proposed allocator can manage DDR-scale memories while having constant FPGA resource utilisation. We evaluate SysAlloc's protocol and memory manager in a Zynq system with both software and hardware clients, demonstrating scaling to 15 concurrent clients, and a peak system allocation rate of 1.36 million allocations/second when managing 128MB of DDR for 4 clients.

关键词： Resource management Hardware Memory management Random access memory Software field programmable gate arrays System-on-chip

来源：评论

学校读者我要写书评

暂无评论

Temperature-triggered behavioral IPs HW Trojan detection method with FPGAs

Temperature-triggered behavioral IPs HW Trojan detection met...

引用

international conference on field programmable logic and applications

作者： Xiaotong Li Benjamin Carrion Schafer Department of Electronic and Information Engineering The Hong Kong Polytechnic University

this works targets the detection of temperature triggered HW Trojans, in particular for third party behavioral IPs (3PBIPs) given in ANSI-C. One of the biggest advantages of C-Based VLSI design is its ability to automatically generate architectures with different trade-offs by only setting different synthesis options. this work uses this property to detect temperature-triggered HW Trojan. A complete design flow is presented. It comprises two main phases: (1) In the first phase, a design space explorer generates micro-architectures with different area vs. power trade-offs automatically for the given behavioral IP. (2) the second phase, maps three of these micro-architectures with different power profiles onto a reconfigurable computing board to create a 3-way redundant system. this system combined with a majority voter scheme is used to detect if a HW Trojan is present in the behavioral IP. Having different power profiles implies that each micro-architecture has a different thermal behavior and thus will trigger the HW Trojan at different time intervals. the outputs of the three designs are compared for discrepancies at regular intervals, allowing our method to therefore exactly pinpoint the exact trigger temperature of the HW Trojan. A case study is presented showing the effectiveness of our method.

关键词： Trojan horses field programmable gate arrays Temperature measurement Temperature sensors Hardware

来源：评论

学校读者我要写书评

暂无评论

Serial and parallel interleaved modular multipliers on FPGA platform

Serial and parallel interleaved modular multipliers on FPGA ...

引用

international conference on field programmable logic and applications

作者： Khalid Javeed Xiaojun Wang Mike Scott School of Electronics Engineering Dublin City University Dublin Ireland CertiVox UK United Kingdom

Modular multiplication is a core operation in all public key based cryptosystems. the performance of these cryptosystems can be enhanced substantially by incorporating an optimized modular multiplier. this paper presents serial and parallel radix-4 modular multipliers based on interleaved multiplication algorithm and Montgomery power laddering technique. A serial radix-4 interleaved modular multiplier provides 50% reduction in the required clock cycles. In addition to the reduction in clock cycles, a parallel modular multiplier maintains a critical path delay comparable to the bit serial interleaved multipliers. the proposed designs are implemented in Verilog HDL and synthesized targeting virtex-6 FPGA platform using Xilinx ISE 14.2 Design suite. the serial radix-4 multiplier computes a 256-bit modular multiplication in 1.3μs, occupies 3.9K LUTs, and runs at 96 MHz. the parallel radix-4 multiplier takes 0.77μs, occupies 5.3K LUTs, and runs at 166 MHz. the results show that the parallel radix-4 modular multiplier provides 62% and 49% speed-up over the corresponding bit serial and bit parallel versions, respectively. thus, these designs are suitable to accelerate modular multiplication in many cryptographic processors.

关键词： field programmable gate arrays Adders Clocks Hardware Elliptic curve cryptography Table lookup Multiplexing

来源：评论

学校读者我要写书评

暂无评论

An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs

An automated technique to generate relocatable partial bitst...

引用

international conference on field programmable logic and applications

作者： Roel Oomen Tuan Nguyen Akash Kumar Henk Corporaal State Key Laboratory of Fluid Power Transmission and Control Zhejiang University Hangzhou China Woodruff School of Mechanical Engineering Huazhong University of Science and Technology Wuhan GA China

Partial reconfiguration is a technique used to increase the flexibility of an FPGA-based system by reprogramming parts of the system dynamically without interrupting the operation of the other modules. Despite the runtime benefits offered by partially reconfigurable (PR) systems, creating and storing partial bitstreams (PBs) are becoming major concerns for system architects when the numbers of reconfigurable partitions (RPs) and PR modules (PRMs) increase. It takes significant amount of time to generate the PBs for PR systems with large number of RPs and PRMs. More importantly, when the mapping relationship between PRMs and RPs is many-to-many, several almost-identical PBs of one PRM must be stored separately which leads to inefficient utilization of the memory storage. therefore, bitstream relocation is drawing interests from the research community as a viable solution. Yet almost none of the works are able to demonstrate a coherent method to not only create relocatable PBs for complex and large PRMs in variable-size RPs but also how to do that automatically to free the designer from the tedious and error prone manual processes. In this paper, we propose a new technique to fill that gap. the method is successfully developed for Xilinx Virtex 7 devices using Vivado design tool flow.

关键词： field programmable gate arrays Table lookup Routing Timing Pins Runtime Algorithm design and analysis

来源：评论

学校读者我要写书评

暂无评论

A resilient, flash-free soft error mitigation concept for the CBM-ToF read-out chain via GBT-SCA

A resilient, flash-free soft error mitigation concept for th...

引用

international conference on field programmable logic and applications

作者： Andrei-Dumitru Oancea Christian Stuellein Jano Gebelein Udo Kebschull University of Frankfurt Frankfurt Germany

the ToF detector read-out chain of the upcoming CBM experiment at FAIR will be equipped with FPGA-based read-out boards (ROBs), which are going to be operated in a radiation environment. Flash-based FPGAs are not an option for this experiment due to their low total ionizing dose limit compared to SRAM-based FPGAs, and therefore the latter is foreseen for the ROBs. Consequently, precautions against soft errors in the configuration memories of the FPGAs need to be taken to keep the chain operational. the proposed approach merges on-chip single upset correction with external intervention for multiple-bit upsets and resets. the external intervention is going to be implemented via the control path of the chain through the GBT-SCA, which offers a JTAG interface, as well as interrupt-capable GPIOs among other features. thus, the use of the GBT-SCA enables an event-driven configuration upset mitigation concept, while being itself radiation hardened by design. Conventional blind configuration scrubbing would cause a continuous load on the control path, while the selective frame scrubbing reduces this load significantly. the concept has been validated in beamtests conducted at COSY, FZ Juelich, Germany. the concept, the beamtest results and limitations of the implementation are presented and discussed in this paper.

关键词： IP networks field programmable gate arrays Data acquisition Protons Equalizers Monitoring Maintenance engineering

来源：评论

学校读者我要写书评

暂无评论

Software-in-the-Loop simulation of embedded control applications based on Virtual Platforms

Software-in-the-Loop simulation of embedded control applicat...

引用

international conference on field programmable logic and applications

作者： Stephan Werner Leonard Masing Fabian Lesniak Jürgen Becker Institute for Information Processing Technologies (ITIV) Karlsruhe Institute of Technology (KIT) Karlsruhe Germany

One challenge in developing complex software for embedded systems is the missing option of rapid prototyping in early stages of the development cycle. In this paper we present the use of the High Level Simulation Framework “Open Virtual Platforms” (OVP) for Software-in-the-Loop simulation of embedded control applications. therefore, we investigate and evaluate different methods allowing the data exchange between the simulated platform and the host machine running the simulation environment. the insights we gain are used to design peripherals which appear to the simulated processor system like devices available on the targeted hardware platform and allow the access to files stored on the host machine on one hand, and the communication with hardware devices connected to the host on the other hand. In both cases the cross-compiled application code for the targeted embedded platform including the operating system (OS) and the hardware abstraction layer (HAL) can be executed by the virtual platform (VP) without any modifications. Additionally, we introduce a method for controlling the synchronization of OVP with the host, which can be used to either run simulations in fast motion mode, or to collaborate with hardware devices or other applications. the approach is verified with two use cases: (1) a motor control application processing data by accessing files and (2) an image processing application interacting with real hardware devices directly coupled with the virtual platform.

关键词： Hardware Software Data models Computational modeling Tuning Space exploration Synchronization

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共185页 << < 75 76 77 78 79 80 81 82 83 84 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：