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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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Hybrid breadth-first search on a single-chip FPGA-CPU heterogeneous platform

Hybrid breadth-first search on a single-chip FPGA-CPU hetero...

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international conference on field programmable logic and applications

作者： Yaman Umuroglu Donn Morrison Magnus Jahre Department of Computer and Information Science Norwegian University of Science and Technology Trondheim Norway

Large and sparse small-world graphs are ubiquitous across many scientific domains from bioinformatics to computer science. As these graphs grow in scale, traversal algorithms such as breadth-first search (BFS), fundamental to many graph processing applications and metrics, become more costly to compute. the cause is attributed to poor temporal and spatial locality due to the inherently irregular memory access patterns of these algorithms. A large body of research has targeted accelerating and parallelizing BFS on a variety of computing platforms, including hybrid CPU-GPU approaches for exploiting the small-world property. In the same spirit, we show how a single-die FPGA-CPU heterogeneous device can be used to leverage the varying degree of parallelism in small-world graphs. Additionally, we demonstrate how dense rather than sparse treatment of the BFS frontier vector yields simpler memory access patterns for BFS, trading redundant computation for DRAM bandwidth utilization and faster graph exploration. On a range of synthetic small-world graphs, our hybrid approach performs 7.8× better than software-only and 2× better than accelerator-only implementations. We achieve an average traversal speed of 172 MTEPS (millions of traversed edges per second) on the ZedBoard platform, which is more than twice as effective as the best previously published FPGA BFS implementation in terms of traversals per bandwidth.

关键词： Random access memory field programmable gate arrays Bandwidth Switches Sparse matrices Parallel processing Arrays

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High speed ECC implementation on FPGA over GF(2m)

High speed ECC implementation on FPGA over GF(2m)

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international conference on field programmable logic and applications

作者： Zia U. A. Khan Mohammed Benaissa Department of Electronic and Electrical Engineering University of Sheffield Sheffield UK

High speed Elliptic Curve Cryptography (ECC) implementations on field programmable Gate Array (FPGA) are highly desirable for applications requiring high speed cost effective and flexible implementations of public key cryptography. Recently, many binary ECC hardware accelerators have been presented based on the Montgomery point multiplication by exploiting the underlying parallelism of the point multiplication (PM). In this paper, we present a combined Montgomery point multiplication algorithm to achieve low latency ECC point multiplication by using novel pipelined full precision parallel multipliers over GF(2 m ). We adopt a careful schedule of point operations to achieve low latency and a smart pipelining in the ECC architecture to reduce the critical path delay. Our proposed ECC architecture is implemented on Virtex5 (XCV5LX110) for a fair comparison and on Virtex7 (XC7VX550T) to quantify performance. Our Virtex5 based implementation over GF(2 163 ), consumes 10363 slices, takes only 5.1 μs for an ECC point multiplication with a frequency of 153 MHz, and has a latency of 780 clock cycles. Our Virtex-5 performance outperforms the fastest reported work on the same platform. Our Virtex7 implementation which can compute an ECC PM in 3.50 μs at a frequency of 223 MHz while utilising only 8736 slices is the highest speed implementation reported to date on FPGA.

关键词： Clocks Pipeline processing Delays Elliptic curve cryptography field programmable gate arrays Computer architecture Registers

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High-Level-Synthesis extensions for scalable Single-Chip Many-Accelerators on FPGAs

High-Level-Synthesis extensions for scalable Single-Chip Man...

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international conference on field programmable logic and applications

作者： Dionysios Diamantopoulos Sotirios Xydis Kostas Siozios Dimitrios Soudris School of Electrical and Computer Engineering National Technical University of Athens Greece

Accelerator-coupled systems have been introduced as a promising architectural paradigm that can boost performance and improve power of general-purpose computing platforms. this research focuses on the accelerators' scalability problem due to resource under-utilization in FPGA-based accelerator-coupled platforms. By recognizing that static memory allocation the de-facto memory management mechanism supported by modern design techniques and synthesis tools forms the main source of memory-induced under-utilization, i.e. leading up to 75% of dark silicon, we propose the development of a) a Single-Chip Many-Accelerator (SCMA) architecture that reduces energy budget by providing high-throughput processing nodes hooked under the same low-latency FPGA die and b) a novel design framework that extends conventional RTL and High Level Synthesis (HLS) design flows with dynamic memory management (DMM) features to leverage scalability by enabling accelerators to dynamically adapt their allocated memory to the runtime memory requirements, thus maximizing the overall accelerator count through effective sharing of FPGA's memories resources. By applying these novel techniques in the state-of-art Vivado-HLS tool, we managed to increase accelerator density up to 3.8× for a Xilinx Ultrascale device and deliver architecture solutions that trade-off per-accelerator latency overhead (1.2×- 19.9×) with overall system's throughput (2.6×- 23.1×) and performance-per-watt (0.09×- 21.7×).

关键词： field programmable gate arrays Memory management Resource management throughput Silicon System-on-chip

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Hierarchical library based power estimator for versatile FPGAs

Hierarchical library based power estimator for versatile FPG...

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international conference on field programmable logic and applications

作者： Hao Liang Wei Zhang Sharad Sinha Yi-Chung Chen Hai Li Department of Electronic and Computer Engineering The Hong Kong University of Science and technology (HKUST) Clear Water Bay Kowloon Hong Kong Department of Electrical and Computer Engineering University of Pittsburgh Pittsburgh Pennsylvania USA

FPGA is a promising hardware accelerator in modern high-performance computing systems. In such a system, power is a key factor in the design requiring thermal and energy-saving considerations. Modern power estimators for FPGA either support specific hardware provided by FPGA vendors or contain power models for certain types of conventional FPGA architectures. However, with technology advancement, novel versatile FPGA architectures are introduced to further augment current FPGA architecture, such as emerging FPGA with non-volatile memory, nano-wire interconnection of reconfigurable array, etc. To evaluate the power consumption of various FPGA designs, the power estimator has to be made more flexible and extensible to support new devices and architectures. We introduce a novel power estimator with hierarchical library supporting power models at different levels, e.g. novel circuits of components, emerging memory devices, time-multiplexing architecture etc. the power estimator also supports coarse-grain or fine-grain power estimation defined by users for achieving complexity-accuracy trade-off. Simulation results of benchmarks on the proposed power estimator against commercial estimators demonstrate accuracy of our tool. the proposed tool demonstrates flexibility to estimate power for both existing FPGA architectures and new architectures.

关键词： field programmable gate arrays Estimation Libraries Power demand Routing Table lookup

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A Scheduling and Binding Heuristic for High-Level Synthesis of Fault-Tolerant FPGA applications 26

A Scheduling and Binding Heuristic for High-Level Synthesis ...

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26th international conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Shastri, Aniruddha Stitt, Greg Riccio, Eduardo Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA

ISBN: (纸本)9781479919253

Space computing systems commonly use field-programmable gate arrays to provide fault tolerance by applying triple modular redundancy (TMR) to existing register-transfer-level (RTL) code. Although effective, this approach has a 3x area overhead that can be prohibitive for many designs that often allocate resources before considering effects of redundancy. Although a designer could modify existing RTL code to reduce resource usage, such a process is time consuming and error prone. Integrating redundancy into high-level synthesis is a more attractive approach that enables synthesis to rapidly explore different tradeoffs at no cost to the designer. In this paper, we introduce a scheduling and binding heuristic for high-level synthesis that explores tradeoffs between resource usage, latency, and the amount of redundancy. In many cases, an application will not require 100% error correction, which enables significant flexibility for scheduling and binding to reduce resources. Even for applications that require 100% error correction, our heuristic is able to explore solutions that sacrifice latency for reduced resources, and typically save up to 47% when relaxing the latency up to 2x. When the error constraint is reduced to 70%, our heuristic achieves typical resource savings ranging from 18% to 49% when relaxing the latency up to 2x, with a maximum of 77%. Even when comparing with optimized RTL designs, our heuristic uses up to 61% fewer resources than TMR.

关键词： high level synthesis Heuristics Resistor Transistor logic Latency redundancy field programmable gate arrays error correction Fault tolerance Designers tunneling magnetoresistance tradeoffs

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Test Results of an ITER Relevant FPGA when Irradiated with Neutrons 4

Test Results of an ITER Relevant FPGA when Irradiated with N...

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4th international conference on Advancements in Nuclear Instrumentation Measurement Methods and their applications (ANIMMA)

作者： Batista, Antonio J. N. Leong, Carlos Santos, Bruno Fernandes, Ana Ramos, Ana Rita Santos, Joana P. Marques, Jose G. Teixeira, Joao P. Goncalves, Bruno Univ Lisbon Inst Super Tecn Inst Plasmas & Fusao Nucl P-1049001 Lisbon Portugal Inst Engn Sistemas & Comp Invest & Desenvolviment P-1000029 Lisbon Portugal Univ Lisbon Inst Super Tecn Ctr Ciencias & Tecnol Nucl P-2695066 Bobadela Portugal

ISBN: (纸本)9781479999187

the data acquisition and control instrumentation in port cell cubicles of tokamak ITER will be irradiated with neutrons, during the fusion reactor operation. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR hoard, included in the ITER Catalog of I&C products - Fast Controllers. the Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), functional data stored in dedicated Block RAM (BRAM) and functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons causes soft errors, unintended changes (bit-tlips) to the values stored in state elements of the FPGA. the SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA configuration memory. SEU sensors with Error Correction Code (ECC) detect and repair the BRAM memories. Proper management of SEU can increase reliability and availability of control instrumentation hardware for nuclear applications. the results of the tests performed using the SEM controller and the BRAM SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1F11 G1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU errors in the configuration and BRAM memories.

关键词： field programmable gate arrays (FPGA)

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A deep convolutional neural network based on nested residue number system

A deep convolutional neural network based on nested residue ...

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international conference on field programmable logic and applications

作者： Hiroki Nakahara Tsutomu Sasao Ehime University Japan Meiji University Japan

A pre-trained deep convolutional neural network (DCNN) is the feed-forward computation perspective which is widely used for the embedded vision systems. In the DCNN, the 2D convolutional operation occupies more than 90% of the computation time. Since the 2D convolutional operation performs massive multiply-accumulation (MAC) operations, conventional realizations could not implement a fully parallel DCNN. the RNS decomposes an integer into a tuple of L integers by residues of moduli set. Since no pair of modulus have a common factor with any other, the conventional RNS decomposes the MAC unit into circuits with different sizes. It means that the RNS could not utilize resources of an FPGA with uniform size. In this paper, we propose the nested RNS (NRNS), which recursively decompose the RNS. It can decompose the MAC unit into circuits with small sizes. In the DCNN using the NRNS, a 48-bit MAC unit is decomposed into 4-bit ones realized by look-up tables of the FPGA. In the system, we also use binary to NRNS converters and NRNS to binary converters. the binary to NRNS converter is realized by on-chip BRAMs, while the NRNS to binary one is realized by DSP blocks and BRAMs. thus, a balanced usage of FPGA resources leads to a high clock frequency with less hardware. the ImageNet DCNN using the NRNS is implemented on a Xilinx Virtex VC707 evaluation board. As for the performance per area GOPS (Giga operations per second) per a slice, the proposed one is 5.86 times better than the existing best realization.

关键词： Table lookup field programmable gate arrays Convolution Kernel Neural networks Clocks Dynamic range

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Fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAs

Fine-tuning CLB placement to speed up reconfigurations in NV...

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international conference on field programmable logic and applications

作者： Yuan Xue Patrick Cronin Chengmo Yang Jingtong Hu Department of Electrical and Computer Eng University of Delaware Newark DE USA School of Electrical and Computer Eng Oklahoma State University Stillwater OK USA

Non-volatile memories (NVMs) outperform traditional SRAMs in terms of low power consumption, high capacity, near-zero power-on delay, and high error-resistance. Researchers have demonstrated the possibilities of implementing FPGA building blocks with various types of NVMs. However, NVMs also bring several new design challenges to FPGAs: the slow write performance of NVM may degrade FPGA (re)configuration speed, while the limited write endurance of NVM constrains the number of times that the FPGA can be (re)configured. Unfortunately, none of these NVM features are taken into consideration in current FPGA synthesis tools, which have been optimized solely for SRAM-based FPGAs. To tackle this limitation, we propose to make the FPGA placement process aware of the slow and costly NVM writes. Our contributions are three-fold: We first construct mathematical models to characterize reconfiguration costs in NVM-based FPGAs. Second, we identify three types of flexibilities that can be exploited to reduce the reconfiguration cost. Finally, we present three approaches for designers to fine-tune the placement process to balance the reconfiguration cost and traditional timing and routability constraints according to their needs. the proposed algorithms are incorporated in Verilog-to-Routing (VTR) CAD tool. Experiments on standard MCNC benchmark circuits show that our approach eliminates up to 67% NVM writes during the reconfiguration process, thus effectively improving the performance and endurance of NVM-based FPGAs.

关键词： field programmable gate arrays Table lookup Nonvolatile memory Video recording Random access memory Timing Optimization

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A study of data partitioning on OpenCL-based FPGAs

A study of data partitioning on OpenCL-based FPGAs

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international conference on field programmable logic and applications

作者： Zeke Wang Bingsheng He Wei Zhang Nanyang Technological University Singapore Hong Kong University of Science and Technology

A lot of research efforts have been devoted to accelerating relational database applications on FPGAs, due to their high energy efficiency and high throughput. Most of the existing studies are based on hardware description languages (HDLs). Recently, FPGA vendors have started to develop OpenCL SDKs for much better programmability. In this paper, we investigate the performance of relational database applications on OpenCL-based FPGAs. As a start, we study the performance of data partitioning, a core operation widely used in relational databases. Due to random memory accesses, data partitioning is time-consuming and can become a major bottleneck for database operators such as hash join. We start with the state-of-the-art OpenCL implementation which was originally designed for CPUs/GPUs, and find that it suffers from lock overheads and memory bandwidth overheads. To reduce lock overheads, we develop a simple yet efficient multi-kernel approach to leverage two emerging features of Altera OpenCL SDK, namely task kernel and channel. Moreover, on-chip buckets are employed to reduce the number of memory transactions. We further develop a cost model to guide the parameter configuration. We evaluate the proposed design on a recent Altera Stratix V FPGA. Our results demonstrate 1) our cost model can accurately predict the performance of data partitioning under different parameter settings; 2) our proposed multi-kernel approach can achieve 10.7X; speedup over the existing OpenCL implementation. Also, the experiments with three case studies show that the optimized implementations can achieve 4-12X performance improvement over the original implementations.

关键词： Kernel Indexes field programmable gate arrays Radiation detectors throughput System-on-chip Partitioning algorithms

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FPGA implementation to estimate the number of endmembers in hyperspectral images

FPGA implementation to estimate the number of endmembers in ...

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international conference on field programmable logic and applications

作者： Carlos González Daniel Mozos Sebastian Lopez Roberto Sarmiento Department of Computer Architecture and Automatics Complutense University of Madrid Madrid Spain Institute for Applied Microelectronics (IUMA) University of Las Palmas de Gran Canaria Spain

Spectral unmixing is an important task for remotely sensed hyperspectral data exploitation. It amounts the identification of pure spectral signatures (endmembers) in the data, and the estimation of the abundance of each endmember in each (possibly mixed) pixel. A challenging problem in spectral unmixing is how to determine the number of endmembers in a given scene. For this purpose, many algorithms have been proposed in the recent literature, being the estimation of the Virtual Dimensionality (VD) of the hyperspectral image and the hyperspectral signal subspace estimator (HySime) two of the most popular choices. Unfortunately, the high dimensionality of the hyperspectral data provided by modern sensors as well as the inherent computational complexity clearly make the use of these algorithms prohibitive for applications under real-time or near real-time constraints. Hence, the utilization of high performance computing platforms in order to accelerate the process of unmixing a hyperspectral image becomes mandatory for such scenarios. Reconfigurable hardware solutions such as field programmable gate arrays (FPGAs) have consolidated during the last years as one of the preferred choices for the fast processing of hyperspectral remotely sensed images due to their advantages over other high performance computing systems, such as clusters of computers, multicore processors and/or graphical processing units (GPUs). this paper uncovers two FPGA-based architectures for accelerating the process of estimating the number of endmembers that constitute a hyperspectral image according to the VD and the HySime algorithms. the proposed methods have been implemented on a Virtex-7 XC7VX690T FPGA and tested using real hyperspectral data collected by NASAs Airborne Visible Infra-Red Imaging Spectrometer (AVIRIS) over the Cuprite mining district in Nevada and the World Trade Center in New York. Experimental results demonstrate that the VD implementation exhibits real-time performance while

关键词： Hyperspectral imaging Estimation Noise Covariance matrices Correlation field programmable gate arrays

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