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From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis

From low-architectural expertise up to high-throughput non-b...

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international conference on field programmable logic and applications

作者： Joao Andrade Nithin George Kimon Karras David Novo Vitor Silva Paolo Ienne Gabriel Falcao Dept. Electrical and Computer Engineering University of Coimbra Portugal École Polytechnique Fédéralc de Lausanne School of Computer and Communication Sciences Lausanne Switzerland Xilinx Research Labs Dublin Ireland

HLS tools have been introduced with the promise of easening and shortening the design cycle of tedious and error-prone RTL-based development of hardware accelerators. However, they do so either by concealing meaningful hardware decisions which model the computing architecture-such as OpenCL compilers-or by abstracting them away into a high-level programming language-usually C-based. In this paper, we show that although Vivado HLS is sufficiently mature to generate a functionally correct FPGA accelerator from a naive description, reaching an accelerator which optimizes the FPGA resource utilization in a way that conveys maximum performance is a process for a hardware architect mindset. We use a highly demanding application, that requires real-time operation, and develop a non-binary LDPC decoder on a state-of-the-art Virtex 7 FPGA, using the Vivado HLS framework. Despite using the same programming syntax as a C-language software compiler, the underlying programming model is not the same, thus, the optimizations required in code refactoring are distinct. Moreover, directive-based optimizations that tweak the synthesized C description hardware must be used in order to attain efficient architectures. these processes are documented in this paper, to guide the reader on how an HLS-based accelerator can be designed, which in our case can come close to the performance achieved with dedicated hand-made RTL descriptions.

关键词： Decoding Optimization Parity check codes field programmable gate arrays Computer architecture Hardware Random access memory

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First results of the silicon telescope using an 'artificial retina' for fast track finding 4

First results of the silicon telescope using an 'artificial ...

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4th international conference on Advancements in Nuclear Instrumentation Measurement Methods and their applications (ANIMMA)

作者： Neri, N. Abba, A. Bedeschi, F. Caponio, F. Cenci, R. Citterio, M. Coelli, S. Fu, J. Geraci, A. Grizzuti, M. Lusardi, N. Marino, P. Monti, M. Morello, M. J. Ninci, D. Petruzzo, M. Piucci, A. Punzi, G. Ristori, L. Spinella, F. Stracka, S. Tonalli, D. Walsh, J. INFN Sez Milano Milan Italy INFN Milano Milan Italy Politecn Milan Milan Italy INFN Pisa Pisa Italy Scuola Normale Super Pisa Pisa Italy Univ Pisa Pisa Italy CERN Geneva Switzerland Fermilab Natl Accelerator Lab Batavia IL USA

ISBN: (纸本)9781479999187

We present the first results of the prototype of a silicon tracker with trigger capabilities based on a novel approach for fast track finding. the working principle of the "artificial retina" is inspired by the processing of visual images by the brain and it is based on extensive parallelisation of data distribution and pattern recognition. the algorithm has been implemented in commercial FPGAs in three main logic modules: a switch for the routing of the detector hits, a pool of engines for the digital processing of the hits, and a block for the calculation of the track parameters. the architecture is fully pipelined and allows the reconstruction of real-time tracks with a latency less then 100 clock cycles, corresponding to 0.25 microsecond at 400 MHz clock. the silicon telescope consists of 8 layers of single-sided silicon strip detectors with 512 strips each. the detector size is about 10 cm x 10 cm and the strip pitch is 183 jam. the detectors are read out by the Beetle chip, a custom ASICs developed for LHCb, which provides the measurement of the hit position and pulse height of 128 channels. the "artificial retina" algorithm has been implemented on custom data acquisition boards based on FPGAs Xilinx Kintcx 7 1x160. the parameters of the tracks detected arc finally transferred to host PC via USB 3.0. the boards manage the read-out ASICs and the sampling of the analog channels. the read-out is performed at 40 MHz on 4 channels for each ASIC that corresponds to a decoding of the telescope information at 1.1 MHz. We report on the first results of the fast tracking device and compare with simulations.

关键词： field programmable gate arrays (FPGA)

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SCFDM based communication system for UAV applications

SCFDM based communication system for UAV applications

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international conference on Radioelektronika

作者： Gyula Mikó András Németh BHE Bonn Hungary Electronics Ltd. Budapest Hungary National University of Public Service Budapest Hungary

Our current activities are focusing on the research and development of a data communication system for unmanned aerial vehicle applications with the features of bi-directional data flow, radio navigation and ranging. the system is in the implementation phase by using software defined radio architecture. the heart of the system is a Xilinx FPGA combined with an SDR chip of Analog Devices Inc. the result is a small form factor MIMO capable hardware with high signal processing power required by the real-time modulation, demodulation and beamforming tasks. In this paper the system description, the hardware platform and test results will be presented.

关键词： field programmable gate arrays Radio frequency Hardware OFDM Timing Demodulation

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Optimization of an Arithmetic logic Unit using Generic Floating Point Algorithm for 12-Bit Architecture 5

Optimization of an Arithmetic Logic Unit using Generic Float...

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5th IEEE international conference on Control System, Computing and Engineering (ICCSCE)

作者： Anacan, Rommel M. Technol Inst Philippines Dept Elect Engn Manila Philippines

ISBN: (纸本)9781479982523

A proposed high speed generic floating point algorithm for 12-Bit Architecture is consist of adder, subtractor, multiplier, divisor, square root, and cube root modules. A novel algorithm was proposed for each modules using VHDL to optimize the speed and area as well as to attain the highest maximum operating frequency. A top down approach was applied for the modules and these were further subdivided into sub-modules for the two inputs to be combined. the novel algorithm was written in VHDL code, simulated in Xilinx 9.2i and 13.1 version and implemented in Xilinx FPGA Virtex boards. the results were analyzed and compared with different algorithms. As the FPGAs' (field programmable Gate Array) popularity increases rapidly, they are becoming more suitable in many applications that require dense computations and high frequency. the improvement in the performance of electronic systems can be traced to developments in integrated circuits which form the fundamental building blocks of modern electronics technology. As with the modern technology fast-approaching, the development of integrated circuits can also be attributed with the help of hardware description language (HDL) such as VHDL and Verilog. the need to improve the face of the ICs through the use HDL also defines the speed and area of the whole circuitry. the basis for conceptualizing the design, development, and evaluation of a generic algorithm is to provide a direct impact of improving the existing modules that was implemented on many design applications in DSP. Prior, to the development of the VHDL modules, other studies involving ALU similar to the paper were considered to determine the parameters to be observed. the enhancement of the existing VHDL modules in the other papers are implemented for the ALU and this includes the development of the new modules such as the square and cube root.

关键词： ALU Optimization Floating Point FPGA VHDL

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TCAM-based flow lookup design on FPGA and its applications 8

TCAM-based flow lookup design on FPGA and its applications

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8th international conference on Advanced Technologies for Communications, ATC 2015

作者： Nguyen-Viet, Tuan Le, Duc-Hung Faculty of Electronics and Telecommunications University of Science-VNUHCM Ho Chi Minh City Viet Nam

ISBN: (纸本)9781467383745

TCAM is now emulated using FPGAs and based on memory known as RAM or register. Most of them are made just using register- or RAM-based resource individually when mapped to FPGA hardware. this paper presents a 4×4 flexible Basic-TCAM architecture that can be flexibly designed based selectively on memory-based or register-based FPGA resource or both of them in combined manner. In addition, it can also allow a scalable architecture. A wider and deeper TCAM of size 512×36 built based on it seizes only 73,728 bits and 1,503 logic utilization and supports competitive search latency of 1 clock cycle over Altera Cyclone V FPGA. A typical flow lookup design based on this Basic-TCAM architecture uses a TCAM of size 4×16 and a simple parser to do a flow lookup. this design application is then taken place in a simple VLAN-based switch system for further feasible application of the TCAM in this work. © 2015 IEEE.

关键词： field programmable gate arrays (FPGA)

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An efficient FPGA implementation of the Harris corner feature detector

An efficient FPGA implementation of the Harris corner featur...

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IAPR international conference on Machine Vision applications (MVA)

作者： Tak Lon Chao Kin Hong Wong The Dept. of Electronic Engineering The Chinese University of Hong Kong The Dept. of Comp Sci. and Engin. The Chinese University of Hong Kong

ISBN: (纸本)9781479982479

In computer vision, the Harris corner feature detector is one of the most essential early steps in many useful applications such as 3-D reconstruction. However, if it is implemented in software, the resulting code is probably not able to be executed in real time under low cost mobile processors. this paper proposes an efficient hardware approach that offloads the repetitive feature extraction procedures into logic gates hence the solution is low cost to produce and low power to operate compared to its software counterpart. In this project, the system is built and tested on a popular prototyping FPGA (field programmable Gate Arrays) platform (Zed-board) with a small FPGA device. the experiments and demos show that the speed and accuracy of the feature detector are good enough for many real world applications.

关键词： Hardware Feature extraction Detectors field programmable gate arrays Digital signal processing Cameras Table lookup

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Review of NoC-based FPGAs architectures

Review of NoC-based FPGAs architectures

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international conference on Energy Aware Computing

作者： Alaa Salaheldin Karim Abdallah Noha Gamal Hassan Mostafa Electronics and Communications Engineering Department Cairo University Giza Egypt Cairo University Giza EG

Nowadays, FPGAs serve as fields programmable Systems on Chip (FPSoC) and are widely used to implement computationally intensive world applications. As the number of components in FPSoCs increases, the interconnect schemes based on Network on Chip (NoC) approach are increasingly used to overcome the problems of traditional bus based and point-to-point interconnect scheme. In this paper, we review several designs based on their contributions, architectures, implementations and future works. We also made our comparison between three of these routes to analyze the effect of varying the number of Virtual Channels (VCs), flit data width and buffer depth on the operating frequency, logic Look-Up Tables (LUTs) and registers to help choosing the appropriate NoC based on system requirements.

关键词： Table lookup field programmable gate arrays Routing Registers Network topology Ports (Computers)

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Dynamic power reduction through clock gating technique for low power memory applications

Dynamic power reduction through clock gating technique for l...

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international conference on Electronics, Communication and Computing Technologies (ICECCT)

作者： G. S. R. Srivatsava Pooran Singh Siddharth Gaggar Santosh Kumar Vishvakarma Indian Institute of Technology Delhi New Delhi Delhi IN Department of Electrical Engineering Indian Institute of Technology Indore India

ISBN: (纸本)9781479960866

Clock gating is an effective technique for minimizing dynamic power in sequential circuits. this paper aims at reducing the power of a dual port register memory by removing the unwanted switching activity on a major portion of the clock network using clock gating. To realize this, two register based Random Access Memories (RAMs) have been designed, one with clock gating and the other without clock gating. their performance on various Xilinx field programmable Gate Array (FPGA) platforms has been discussed to emphasize the effect of this technique at various technology nodes. A reduction of 25% to 70% in the dynamic power and 15% to 32% in the total power of the memory has been observed. this reduction in the power of the memory is attributed to the register level application of clock gating technique the designs have been synthesized, implemented and simulated using Xilinx ISE design suite 13.4 and the power has been estimated using XPower Analyzer.

关键词： Random access memory Clocks logic gates Switches field programmable gate arrays Hardware

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An emulation of transparent interface design based on TCP/IP implemented onto FPGA of an Altera Nios® Board

An emulation of transparent interface design based on TCP/IP...

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international conference on Telecommunication Systems, Services, and applications (TSSA)

作者： Arthur Silitonga Mervin Hutabarat Study Program of Electrical Engineering - President University Bekasi Indonesia School of Electrical Engineering and Informatics - Institut Teknologi Bandung Bandung Indonesia

A TCP/IP-based interface design has been designed, and the interface can process data based on the Ethernet IEEE 802.3 Standard. this interface is able to identify Ethernet Frame IEEE 802.3, Header of LLC 802.2, Header and the Packet Data of IP Datagram. In addition, the interface can perform simple encryption process, and renew FCS (Frame Check Sequence) data of an ethernet frame. After the interface design had been simulated, it was implemented onto Altera Stratix EP1S10F780C6ES FPGA of an Altera Nios® Board. the interface's synthesis result shows that the interface's internal frequency is up to 78.01 MHz. Moreover, the implementation result was verified using SignalTap II logic Analyzer. the interface functions as an emulator properly which can operate in half duplex mode.

关键词： TCPIP Protocols Encryption field programmable gate arrays IEEE 802.3 Standard

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the new ATLAS/LUCID detector

The new ATLAS/LUCID detector

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international conference on Advancements in Nuclear Instrumentation Measurement Methods and their applications (ANIMMA)

作者： Marco Bruschi INFN ATLAS/LUCID collaboration Bologna Italy

ISBN: (纸本)9781479999194

the new ATLAS luminosity monitor has many innovative aspects implemented. Its photomultipliers tubes are used as detector elements by using the Cherenkov light produced by charged particles above threshold crossing the quartz windows. the analog shaping of the readout chain has been improved, in order to cope with the 25 ns bunch spacing of the LHC machine. the main readout card is a quite general processing unit based on 12 bit -320 MS/s Flash ADC and on FPGAs, delivering the processed data to 1.3 Gb/s optical links. the article will describe all these aspects and will outline future perspectives of the card for next generation high energy physics experiments.

关键词： Detectors Large Hadron Collider field programmable gate arrays Readout electronics Monitoring Aluminum Calibration

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