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A low-cost and flexible FPGA implementation for SPECK block Cipher

A low-cost and flexible FPGA implementation for SPECK block ...

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international ISC conference on Information Security and Cryptology (ISCISC)

作者： Ali Nemati Soheil Feizi Arash Ahmadi Vahab Al-din Makki Department of Electrical Engineering Razi University Kermanshah Iran Department of Electrical Engineering University of Windsor Ontario Canada

field programmable Gate Arrays (FPGAs) are quickly becoming a fundamental flexible integrated circuit building block of choice for many applications such as aerospace, military and defense systems. In addition, instead of using a large number of logic gates, FPGA today can be used to implement any circuits that you want. Furthermore, FPGAs can be configured as system on a chip (SoC). In June 2013 American National Security Agency (NSA) proposed a new block cipher family named SPECK. In this paper, two methods are used to implement this algorithm. First method is used high level synthesis for give more flexibility and to achieve suitable throughput in our implementation. Second method is used bit serialized architecture to achieve minimum area and cost in our design. In second methodology, we have implemented SPECK, with a very small hardware architecture only costs 34 slices and 68 LUTs on a Spartan-3 FPGA. the results show that with a tantamount security level, SPECK is 85% smaller than AES, 68% smaller than PRESENT (a standardized low-cost AES Superseded and an ISO lightweight algorithm).

关键词： Algorithm design and analysis field programmable gate arrays Ciphers Hardware Encryption Software algorithms

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Test results of an ITER relevant FPGA when irradiated with neutrons

Test results of an ITER relevant FPGA when irradiated with n...

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international conference on Advancements in Nuclear Instrumentation Measurement Methods and their applications (ANIMMA)

作者： Antonio J. N. Batista Carlos Leong Bruno Santos Ana Fernandes Ana Rita Ramos Joana P. Santos José G. Marques João P. Teixeira Bruno Gonçalves The Instituto de Plasmas e Fusão Nuclear Universidade de Lisboa Lisboa Portugal Investigação e Des envolvimento The Instituto de Engenharia de Sistemas e Computadores Lisboa Portugal The Centro de Ciências e Tecnologias Nucleares Universidade de Lisboa Bobadela Portugal

the data acquisition and control instrumentation in port cell cubicles of tokamak ITER will be irradiated with neutrons, during the fusion reactor operation. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of I&C products - Fast Controllers. the Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), functional data stored in dedicated Block RAM (BRAM) and functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons causes soft errors, unintended changes (bit-flips) to the values stored in state elements of the FPGA. the SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA configuration memory. SEU sensors with Error Correction Code (ECC) detect and repair the BRAM memories. Proper management of SEU can increase reliability and availability of control instrumentation hardware for nuclear applications. the results of the tests performed using the SEM controller and the BRAM SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU errors in the configuration and BRAM memories.

关键词： field programmable gate arrays Neutrons Single event upsets Sensors Radiation effects Data acquisition Software

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A 600V FS-IGBT using locally isolated P-well structures for improved short circuit ruggedness

A 600V FS-IGBT using locally isolated P-well structures for ...

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international conference on Power Electronics (ICPE)

作者： Jisun Kim Sooseong Kim Kwang-Hoon Oh Chongman Yun TRinno Technology Co. Ltd. Anyang-si Gyunggi-do Republic of Korea

ISBN: (纸本)9781479988006

Trench gate field stop (FS) IGBT is widely used in various power applications owing to its low conduction and switching losses. However, the trench gate FS-IGBT induces the high saturation current due to its high cell density so that it deteriorates the short circuit ruggedness, which is essential for the power applications such as welding machines and motor controls. In this paper, a 600V trench gate FS-IGBT having improved short circuit capability is proposed. the proposed IGBT employs locally isolated P-well structure in the active region. thereby the IGBT shows sufficient short circuit withstanding time with V CE, SAT of 1.5V and E OFF of 25|jJ/A by means of the carrier stored effect.

关键词： logic gates Insulated gate bipolar transistors Charge carrier processes Current density Switching loss Leakage currents Switches

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A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs 24

A novel modular adder for one thousand bits and more using f...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Rogawski, Marcin Homsirikamol, Ekawat Gaj, Kris Volgenau School of Engineering George Mason University FairfaxVA22030 United States

ISBN: (纸本)9783000446450

In this paper a novel, low-latency family of high-radix Parallel Prefix Network adders and modular adders has been proposed. this family efficiently takes advantage of fast carry chains of modern FPGAs. the implementation results reveal that these adders have great potential for efficient implementation of modular addition with the long integers used in various public key cryptography schemes. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Using an OpenCL framework to evaluate interconnect implementations on FPGAs 24

Using an OpenCL framework to evaluate interconnect implement...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Mirian, Vincent Chow, Paul Department of Computer and Electrical Engineering University of Toronto Toronto Canada

ISBN: (纸本)9783000446450

field programmable Gate Arrays (FPGAs) are an ideal platform for building systems with custom hardware accelerators, however managing these systems is still a major challenge. the OpenCL standard has become accepted as a good programming model for managing heterogeneous platforms due to its rich constructs. Although commercial OpenCL frameworks are now emerging, there is a need for an open-source OpenCL framework that facilitates the exploration of the overall system architecture and software, as well as the implementation and architectures of the custom hardware accelerators (devices). In this paper, we use an OpenCL framework to compare interconnect implementations for a simple multiprocessor accelerator. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Optimization design of a low power asynchronous DES for security applications based on Balsa and synchronous tools

Optimization design of a low power asynchronous DES for secu...

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international conference on Electronics, Communications and Computers (CONIELECOMP)

作者： Qihui Zhang Jian Cao Xixin Cao Xing Zhang Yin Ye Yanguang Zhao Botao Chen School of Software and Microelectronics Peking University Beijing China Department of Smart Card Platform CEC Huada Electronic Design Co. Ltd. Beijing China

ISBN: (纸本)9781479974375

DES has been widely used in current financial security application, but side-channel attacks are considered as serious threats to DES cryptographic algorithm. Asynchronous DES design will be a proper solution because of its natural properties. First, a low power asynchronous DES architecture and sub key generation architecture are proposed. then, optimized Balsa implementation, GTECH-based implementation and black-box-based implementation are described to reduce area and power. Furthermore, a dual-rail implementation is carried out for future security applications and a Spartan-6 FPGA verification is checked before taping out. ASIC implementation results show that our proposed asynchronous DES architecture and black-box-based scheme can achieve about 20% lower power with 25% area increase of its synchronous equivalent, and its energy is only 8.2% and 27.3% of those reported in other papers, respectively. FPGA experimental results show that our proposed asynchronous DES exhibits an operation frequency of 196.2 MHz and costs only 4% slice LUTs. Moreover, it can be suitably integrated into contactless smart cards.

关键词： logic gates Computer architecture Optimization field programmable gate arrays Application specific integrated circuits Hardware design languages Libraries

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Fast and accurate SEU-tolerance characterization method for Zynq SoCs 24

Fast and accurate SEU-tolerance characterization method for ...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Villata, Igor Bidarte, Unai Kretzschmar, Uli Astarloa, Armando Lazaro, Jesus Department of Electronics and Telecommunications University of the Basque Country UPV/EHU Bilbao Spain

ISBN: (纸本)9783000446450

In this paper a new SEU (Single Event Upset) emulation method for testing fault tolerant systems in FPGAs is presented. It is implemented on a 'Xilinx Zynq®-7000 All programmable System on Chip (SoC)' device, which combines a hard microprocessor with programmable logic. An important new feature is that an internal hardware configuration interface controlled by this microprocessor is provided. this interface is used for injecting faults into the configuration bitstream in order to emulate radiation effects. Since both the processing system and the programmable logic are in the same chip, this method has the high speed characteristics of internal fault injection methods. As a hard internal configuration interface is provided, a configuration bit belonging to the internal interface port cannot be flipped and injection side effects are avoided. this method is especially suitable for testing complex real fault-tolerant FPGA designs because no substantial modifications need to be added to the original design. A universal verification system is proposed to avoid designing complex external application-dependent testbenches. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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A design support tool set for asynchronous circuits with bundled-data implementation on FPGAs 24

A design support tool set for asynchronous circuits with bun...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Takizawa, Keitaro Hosaka, Shunya Saito, Hiroshi University of Aizu 965-8580 Japan

ISBN: (纸本)9783000446450

In this paper, we propose a design support tool set for asynchronous circuits with bundled-data implementation to implement them on commercial FPGAs easily considering a latency constraint. the design support tool set consists of six tools to automate constraint generation, timing verification, and delay adjustment for bundled-data implementation. In the experiments, we synthesize two circuits using the proposed tool set and compare area, performance, power consumption, and energy consumption with the synchronous counterparts. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Source-level debugging for FPGA high-level synthesis 24

Source-level debugging for FPGA high-level synthesis

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24th international conference on field programmable logic and applications, FPL 2014

作者： Calagar, Nazanin Brown, Stephen D. Anderson, Jason H. Dept. of Electrical and Computer Engineering University of Toronto TorontoON Canada

ISBN: (纸本)9783000446450

We describe a source-level debugging framework for FPGA high-level synthesis (HLS) that offers gdb-like step, break, and data inspection functionality for an HLS-generated hardware circuit. With the proposed framework, the user can inspect the values of logic signals in the hardware from the C source code perspective. the logic signal values come from one of two sources: 1) a logic simulation of the RTL, or 2) an actual execution of the hardware on an FPGA. In addition to the software-like ecosystem for FPGA HLS debugging, the framework provides the user with insight on the RTL produced by the HLS tool for each C statement, and permits concurrent hardware and software debugging to discover the first point at which any logic signal in the hardware mismatches with its corresponding variable in software. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Automatic Generation of Parallelized FFT logic for Implementation in FPGA Chips 12

Automatic Generation of Parallelized FFT Logic for Implement...

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12th IEEE international New Circuits and Systems conference (IEEE NEWCAS)

作者： Sokalski, Tayler Manjikian, Naraig Nakina Syst Ottawa ON K2K 2T8 Canada Queens Univ Dept Elect & Comp Engn Kingston ON K7L 3N6 Canada

ISBN: (纸本)9781479948857

this paper considers the automatic generation of parallelized fast-Fourier-transform (FFT) logic for field-programmable gate-array (FPGA) chips. A custom software tool has been created to generate VHDL logic descriptions for parallelized radix-4 FFT architectures using decimation-infrequency (DIF). these architectures accept N simultaneously-provided fixed-point complex-valued input samples every cycle for applications that demand high throughput. Two approaches are described for generating the product terms in complex multiplications involving twiddle constants: standard single-cycle multiplication, and multi-cycle shift-and-add multiplication. Synthesis results are reported for parallelized FFT implementations of different sizes targeting low-cost Cyclone III chips and high-end Stratix III and IV chips from Altera. the shift-and-add approach for constant multiplication is shown to consume more logic resources, but provide a higher maximum clock frequency.

关键词： Clocks Computer architecture Cyclones field programmable gate arrays Hardware Software tools Standards field programmable gate arrays Software Tools cyclones autogeneration Computer Architecture Timing devices Computer hardware Fast Fourier transform Computer chips Formal logic

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