检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,813 篇 会议
30 篇 期刊文献
5 册 图书

馆藏范围

1,848 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,203 篇 工学
- 1,020 篇 计算机科学与技术...
- 707 篇 软件工程
- 388 篇 电气工程
- 186 篇 电子科学与技术（可...
- 62 篇 信息与通信工程
- 60 篇 控制科学与工程
- 26 篇 机械工程
- 25 篇 动力工程及工程热...
- 24 篇 建筑学
- 23 篇 仪器科学与技术
- 16 篇 土木工程
- 14 篇 生物工程
- 11 篇 核科学与技术
- 10 篇 材料科学与工程（可...
- 9 篇 光学工程
- 8 篇 生物医学工程（可授...
- 8 篇 安全科学与工程
- 6 篇 化学工程与技术
- 6 篇 交通运输工程
146 篇 理学
- 97 篇 数学
- 33 篇 物理学
- 16 篇 生物学
- 14 篇 系统科学
- 10 篇 统计学（可授理学、...
- 6 篇 化学
52 篇 管理学
- 39 篇 管理科学与工程(可...
- 17 篇 工商管理
- 15 篇 图书情报与档案管...
14 篇 法学
- 12 篇 社会学
9 篇 经济学
- 9 篇 应用经济学
8 篇 医学
6 篇 农学
4 篇 军事学
2 篇 教育学

主题

817 篇 field programmab...
670 篇 field programmab...
271 篇 hardware
155 篇 computer archite...
119 篇 logic gates
111 篇 table lookup
94 篇 clocks
83 篇 throughput
78 篇 random access me...
72 篇 routing
71 篇 acceleration
71 篇 software
66 篇 optimization
63 篇 kernel
62 篇 delays
52 篇 registers
52 篇 logic
49 篇 switches
46 篇 algorithm design...
45 篇 computational mo...

机构

15 篇 univ toronto dep...
9 篇 department of co...
9 篇 imperial coll lo...
8 篇 ecole polytech f...
7 篇 univ british col...
7 篇 school of comput...
7 篇 brigham young un...
7 篇 imperial coll lo...
7 篇 tokyo inst techn...
6 篇 univ tsukuba tsu...
6 篇 university of ch...
6 篇 department of el...
6 篇 univ warwick sch...
6 篇 xilinx inc san j...
5 篇 univ manchester ...
5 篇 department of el...
5 篇 univ toronto dep...
5 篇 swiss fed inst t...
5 篇 xilinx inc 2100 ...
5 篇 altera corp san ...

作者

33 篇 luk wayne
21 篇 maruyama tsutomu
16 篇 wayne luk
16 篇 koch dirk
12 篇 wilton steven j....
12 篇 betz vaughn
12 篇 ienne paolo
11 篇 fahmy suhaib a.
11 篇 cheung peter y. ...
10 篇 vaughn betz
9 篇 constantinides g...
8 篇 suhaib a. fahmy
8 篇 prasanna viktor ...
8 篇 chow paul
8 篇 glesner manfred
8 篇 amano hideharu
8 篇 akash kumar
7 篇 kapre nachiket
7 篇 alonso gustavo
7 篇 hutchings brad

语言

1,823 篇 英文
25 篇 其他
1 篇 中文

检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

共 1848 条记录，以下是821-830 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Pattern-based FPGA logic block and clustering algorithm 24

Pattern-based FPGA logic block and clustering algorithm

引用

24th international conference on field programmable logic and applications, FPL 2014

作者： Tang, Xifan Gaillardon, Pierre-Emmanuel De Micheli, Giovanni Switzerland

ISBN: (纸本)9783000446450

In classical FPGA, LUTs and DFFs are pre-packed into BLEs and then BLEs are grouped into logic blocks. We propose a novel logic block architecture with fast combinational paths between LUTs, called pattern-based logic blocks. A new clustering algorithm is developed to release the potential of pattern-based logic blocks. Experimental results show that the novel architecture and the associated clustering algorithm lead to a 14% performance gain and a 8% wirelength reduction with a 3% area overhead compared to conventional architecture in large control-instensive benchmarks. © 2014 Technical University of Munich (TUM).

关键词： Clustering algorithms

来源：评论

学校读者我要写书评

暂无评论

Portable module relocation and bitstream compression for Xilinx FPGAs 24

Portable module relocation and bitstream compression for Xil...

引用

24th international conference on field programmable logic and applications, FPL 2014

作者： Beckhoff, Christian Koch, Dirk Torresen, Jim University of Oslo Norway University of Manchester United Kingdom

ISBN: (纸本)9783000446450

this paper presents a novel methodology for generating and compressing configuration bitstreams for modules that can be executed at different positions of an FPGA. the presented methodology for bitstream generation and compression does not need deep knowledge of the bitstream format and it is independent of the target (Xilinx) FPGA family. the approach consists of a design phase where partial bitstreams are decomposed into sequences of module dependent and module independent pieces of configuration data. At run-time, this data can then be recomposed for the individual placement positions by a special DMA configuration controller as one atomic operation without any further software interaction. Our experiments demonstrate that module relocation and fast partial reconfiguration can be implemented at low logic cost. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Ready PCIe data streaming solutions for FPGAs 24

Ready PCIe data streaming solutions for FPGAs

引用

24th international conference on field programmable logic and applications, FPL 2014

作者： Preußer, thomas B. Spallek, Rainer G. Technische Universität Dresden Germany

ISBN: (纸本)9783000446450

the PCIe attachment of FPGA accelerators within host workstations is convenient and offers a high-performance direct integration. FPGA-boards designed and equipped as PCIe extension cards are available off-the-shelf. this paper gives an overview on options to provide data streaming abstractions in user applications using PCIe technology. RIFFA and Xillybus are straightforward implementations, which aim at providing ready solutions at this level. this paper will describe these platforms and evaluate them in terms of their ease of use, their perceived maturity and the performance metrics bandwidth and latency. It concludes with providing a brief guideline on how to select the proper platform depending on the usage context. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory 24

A logic cell architecture exploiting the shannon expansion f...

引用

24th international conference on field programmable logic and applications, FPL 2014

作者： Zhao, Qian Yanagida, Kyosei Amagasaki, Motoki Iida, Masahiro Kuga, Morihiro Sueyoshi, Toshinori Graduate School of Science and Technology Kumamoto University Japan

ISBN: (纸本)9783000446450

Most modern field-programmable gate arrays (FPGAs) employ a look-up table (LUT) as their basic logic cell. Although a k-input LUT can implement any k-input logic, its functionality relies on a large amount of configuration memory. As FPGA scales improve, the increased quantity of configuration memory cells required for FPGAs will require a larger area and consume more power. Moreover, the soft-error rate per device will also increase as more configuration memory cells are embedded. We propose scalable logic modules (SLMs), logic cells requiring less configuration memory, reducing configuration memory by making use of partial functions of Shannon expansion for frequently appearing logics. Experimental results show that SLM-based FPGAs use much less configuration memory and have smaller area than conventional LUT-based FPGAs. © 2014 Technical University of Munich (TUM).

关键词： Table lookup

来源：评论

学校读者我要写书评

暂无评论

Biomedical image processing and reconstruction with dataflow computing on FPGAs 24

Biomedical image processing and reconstruction with dataflow...

引用

24th international conference on field programmable logic and applications, FPL 2014

作者： Grull, Frederik Kebschull, Udo IRI Goethe University Frankfurt Frankfurt am Main Germany

ISBN: (纸本)9783000446450

Increasing chip sizes and better programming tools have made it possible to increase the boundaries of application acceleration with FPGAs. Two applications, localization microscopy and electron tomography, are presented in the author's PhD thesis and summarized in this paper. Both have been ported from imperative languages to the dataflow paradigm that maps well onto long processing pipelines in custom hardware. the results show that an acceleration of 200 compared to an Intel i5 450 CPU for localization microscopy, and an acceleration of 5 over an Nvidia Tesla C1060 for electron tomography while maintaining full accuracy. the main challenge arose from the need to fully understand and re-write most of the imperative source in a form suitable for dataflow computing. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

RAM-based hardware accelerator for network data anonymization 24

RAM-based hardware accelerator for network data anonymizatio...

引用

24th international conference on field programmable logic and applications, FPL 2014

作者： Yamaguchi, Fumito Matsui, Kanae Nishi, Hiroaki Graduate School of Science and Technology Keio University Yokohama Japan

ISBN: (纸本)9783000446450

Many network services including intrusion detection and recommendation provide their services by analyzing information acquired from network transactions. A careful analysis of these data can reveal valuable information when deep packet inspection is performed. Since these packet analyses generate sensitive information from enormous volumes of transmitted data, the requirement for data anonymization has been discussed. there have been many studies of anonymization techniques and their implementation in software applications. However, limited research has been undertaken regarding hardware-based anonymizers. this paper proposes and evaluates a RAM-based anonymization architecture that maintains both high throughput and a low information-loss ratio. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

An FPGA-optimized architecture of horn and schunck optical flow algorithm for real-time applications 24

An FPGA-optimized architecture of horn and schunck optical f...

引用

24th international conference on field programmable logic and applications, FPL 2014

作者： Kunz, Michael Ostrowski, Alexander Zipf, Peter Digital Technology Group University of Kassel Kassel34121 Germany

ISBN: (纸本)9783000446450

Optical flow estimation of image sequences is one of the key elements for motion detection. However, processing the optical flow in real-time is still an open task due to its computationally expensive nature. In this paper we present an FPGA-optimized architecture for optical flow estimation based on the algorithm of Horn and Schunck. While existing FPGA-realizations are only partly real-time capable, on a Stratix IV our architecture enables the computation of the optical flow for each pixel of a frame with 640 × 512 pixels at a framerate of 30 fps in iterative and up to 4k resolution (4,096 × 2,304 pixels) at a framerate of 20 fps in full-pipelined form. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Analyzing the energy-efficiency of dense linear algebra kernels by power-profiling a hybrid CPU/FPGA system

Analyzing the energy-efficiency of dense linear algebra kern...

引用

IEEE 25th international conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Giefers, Heiner Polig, Raphael Hagleitner, Christoph IBM Res Zurich Zurich Switzerland

ISBN: (纸本)9781479936090

It has been shown that FPGA accelerators can outperform pure CPU systems for highly parallel applications and they are considered as a power-efficient alternative to software programmable processors. However, when using FPGA accelerator cards in a server environment multiple sources of power consumption have to get taken into account in order to rate the systems energy-efficiency. In this paper we study the energy-efficiency of a hybrid CPU/FPGA system for a dense linear algebra kernel. We present an FPGA GEMM accelerator architecture that can be tailored to various data types. the performance and energy consumption is compared against tuned, multi-threaded GEMM functions running on the host CPU. We measure the power consumption with internal current/voltage sensors and break down the power draw to the systems components in order to classify the energy consumed by the processor cores, the memory, the I/O bus system and the FPGA card. Our experimental results show that the FPGA-accelerated DGEMM is less energy-efficient than a multi-threaded software implementation with respect to the full systems power consumption, but the most efficient choice when only the dynamic parts of the power are factored in.

关键词： Energy efficiency Linear algebra Power consumption field programmable gate arrays system component Energy sources software implementation data types Seeds

来源：评论

学校读者我要写书评

暂无评论

Adaptive linear predictor FIR filter based on the Cyclone V FPGA with HPS to reduce narrow band RFI in AERA radio detection of cosmic rays

Adaptive linear predictor FIR filter based on the Cyclone V ...

引用

international conference on Advancements in Nuclear Instrumentation Measurement Methods and their applications (ANIMMA)

作者： Zbigniew Szadkowski D. Glas Department of Physics and Applied Informatics University of Łódź Łódź Poland For the Pierre Auger Collaboration University of Łódź Łódź Poland

ISBN: (纸本)9781479999194

We present the new approach to a filtering of radio frequency interferences (RFI) in the Auger Engineering Radio Array (AERA) which study the electromagnetic part of the Extensive Air Showers. the radio stations can observe radio signals caused by coherent emissions due to geomagnetic radiation and charge excess processes. AERA observes frequency band from 30 to 80 MHz. this range is highly contaminated by human-made RFI. In order to improve the signal to noise ratio RFI filters are used in AERA to suppress this contamination. the filter has been already tested in the real AERA radio stations on Argentinean pampas with a very successful results. the linear equations were solved either in the virtual soft-core NIOS® processor (implemented in the FPGA chip as a net of logic elements) or in the external Voipac PXA270M ARM processor. the NIOS®R processor is relatively slow (50 MHz internal clock), calculations performed in an external processor consume a significant amount of time for data exchange between the FPGA and the processor. Test showed a very good efficiency of the RFI suppression for stationary (long-term) contaminations. However, we observed a short-time contaminations, which could not be suppressed either by the IIR-notch filter or by the FIR filter based on the linear predictions. For the LP FIR filter the refreshment time of the filter coefficients was to long and filter did not keep up with the changes of a contamination structure, mainly due to a long calculation time in a slow processors. We propose to use the Cyclone®R V SE chip with embedded micro-controller operating with 925 MHz internal clock to significantly reduce a refreshment time of the FIR coefficients. the lab results are promising.

关键词： Contamination Finite impulse response filters Cyclones field programmable gate arrays Cosmic rays Detectors Mathematical model

来源：评论

学校读者我要写书评

暂无评论

Low-cost multiplier-based FPU for embedded processing on FPGA 24

Low-cost multiplier-based FPU for embedded processing on FPG...

引用

24th international conference on field programmable logic and applications, FPL 2014

作者： Pasca, Bogdan Altera European Technology Centre United Kingdom

ISBN: (纸本)9783000446450

Industrial applications often require processing data with large dynamic ranges at low sample rates. As algorithms become more complex, handling the data range of variables required for fixed-point implementations becomes time consuming, and can also lead to inefficient designs. Floating-point solutions leverage these limitations trading automatic data range handling for a usually higher implementation cost. the adoption of floating-point solutions for this class of applications is conditioned by area and performance requirements. In this paper we present a low-cost floating-point unit which can either be used standalone, or can be attached to a RISC microprocessor. the proposed unit targets modern, multiplier-based FPGAs, computes efficiently costly operations: ×, ÷, 1/x, √x and 1√x, requires less than 700LE and 4-9bit multipliers on a CycloneIV and runs close to 150MHz. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共185页 << < 79 80 81 82 83 84 85 86 87 88 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：