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Remote FPGA Lab applications, interactive timing diagrams and assessment 25

Remote FPGA Lab applications, interactive timing diagrams an...

引用

25th IET Irish Signals and Systems conference, ISSC 2014 and China-Ireland international conference on Information and Communications Technologies, CIICT 2014

作者： Morgan, Fearghal Cawley, Seamus Kane, Maire Coffey, Aedan Callaly, Frank Department of Electrical and Electronic Engineering NUI Galway Galway Ireland

ISBN: (纸本)9781849199247

the Remote FPGA Lab (RFL) provides interactive web-based visual control and probing of reconfigurable logic hardware in the Cloud in real time, and supports a learn-by-doing approach to digital system education. the authors have previously reported the RFL architecture, and RFL usage and survey data which highlights its effectiveness for enhanced learning, achievement and engagement. this paper illustrates an RFL counter example use case. A range of animated interactive web page console views are presented, from top level block diagram to FPGA Lookup Table and D Flip Flop hardware implementation views, and Finite State Machine animation. the paper illustrates the additional interactive real-time timing diagram functionality and proposes an automatic online assessment strategy using the RFL.

关键词： field programmable gate arrays (FPGA)

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An enhanced and embedded GNU radio flow 24

An enhanced and embedded GNU radio flow

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24th international conference on field programmable logic and applications, FPL 2014

作者： Marlow, Ryan Dobson, Chris Athanas, Peter Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University BlacksburgVA United States

ISBN: (纸本)9783000446450

this paper presents a Zynq capable version of GNU Radio - an open-source rapid radio deployment tool - with an enhanced flow that utilizes the processing capability of FPGAs. this work features TFlow - an FPGA back-end compilation accelerator for instant FPGA assembly. the Xilinx Zynq FPGA architecture integrates the FPGA fabric and CPU onto a single chip, which eliminates the need for a controlling host computer;thus, providing a single, portable, low-power, embedded platform. By exploiting the computational advantages of FPGAs in the GNU Radio flow, a larger class of software defined radios can be implemented. Once the FPGA is programmed with a design, modules can be parameterized to realize an even larger class of applications and further solidify the concept of rapid assembly of software defined radios. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Educating hardware design - From primary school children to postgraduate engineers 24

Educating hardware design - From primary school children to ...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Knodel, Oliver Zabel, Martin Lehmann, Patrick Spallek, Rainer G. Department of Computer Science Technische Universität Dresden Germany

ISBN: (纸本)9783000446450

the future of hardware development lies in massively parallel hardware architectures as used in embedded as well as high-performance systems, for instance streaming-based, real-time and database applications. Especially field-programmable gate arrays provide a platform for the rapid development of integrated circuits and the accompanied software. For reasons of energy efficiency, it is increasingly important to tailor hardware directly to the application. As such systems are very complex, the training of engineers has to start early. Furthermore, the usual curricula in computer science and electrical engineering teach only basic skills. Our approach does not start with specialized courses in master or diploma programs, but already with the motivation of primary school children for technical disciplines. Girls and boys are addressed equally. In school, children are made familiar with programmable circuits and thus motivated to study computer science with a specialization in computer engineering. In this paper we present our lectures and practical courses for bachelor and master students. With examples from final bachelor and master projects we demonstrate the quality of our education and its integration into current research. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Hierarchical reconfiguration of FPGAs 24

Hierarchical reconfiguration of FPGAs

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24th international conference on field programmable logic and applications, FPL 2014

作者： Koch, Dirk Beckhoff, Christian University of Manchester United Kingdom University of Oslo Norway

ISBN: (纸本)9783000446450

Partial reconfiguration allows some applications to substantially save FPGA area by time sharing resources among multiple modules. In this paper, we push this approach further by introducing hierarchical reconfiguration where reconfigurable modules can have reconfigurable submodules. this is useful for complex systems where many modules have common parts or where modules can share components. For such systems, we show that the number of bitstreams and the bitstream storage requirements can be scaled down from a multiplicative to an additive behavior with respect to the number of modules and submodules. A case study consisting of different reconfigurable softcore CPUs and hierarchically reconfigurable custom instruction set extensions demonstrates a 18.7× lower bitstream storage requirement and up to 10× faster reconfiguration speed when using hierarchical reconfiguration instead of using conventional single-level module-based reconfiguration. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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A survey of open source processors for FPGAs 24

A survey of open source processors for FPGAs

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24th international conference on field programmable logic and applications, FPL 2014

作者： Jia, Rui Lin, Colin Yu Guo, Zhenhong Chen, Rui Wang, Fei Gao, Tongqiang Yang, Haigang System on Programmable Chip Research Department Institute of Electronics Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9783000446450

FPGA-based SoCs have been gaining great favors among traditional applications and expanding the application domains to some new areas. Reusing and sharing components is an attractive and pratical methodology for system designers to reduce the design complexity of the SoC architectures. Open source hardware has become an effective method of improving the design productivity. As the core functional component, processors affects the performance of SoC systems. this paper investigates existing open source processors, and gives an overview. From the points of usability and stability, the main features of open source processors are summarized. Following these features, some open source processors with high usability and stability are selected. these open source processors and existing vendor-provided soft processors are implemented on Stratix V and Virtex-7 FPGAs using corresponding EDA tools, Quart us n and ISE. the implementation results are compared and discussed. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Using high-level knowledge to enhance data channels in FPGA streaming systems 24

Using high-level knowledge to enhance data channels in FPGA ...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Wijeyasinghe, Marlon thomas, David Department of Electrical and Electronic Engineering Imperial College London United Kingdom

ISBN: (纸本)9783000446450

FPGAs are commonly used in high performance computing applications, often in the form of streaming systems which exploit parallelism of algorithms along pipelined kernels. While such applications have traditionally been designed at the Register Transfer Level (RTL), the increasing complexity in terms of FPGA resource usage, arithmetic logic and dataflow is causing the time taken for RTL programming to be prohibitive. this necessitates using high-level programming tools to transpar-ently handle low-level aspects - thus simplifying the design pro-cess. Examples of high-level tools for building streaming systems include MaxCompiler by Maxeler Technologies and DSP Builder by Altera. We propose an interception layer which when inserted into communication channels, transparently enhances their per-formance and capabilities without needing to modify the stream-ing kernels or host code. We discuss specific channel enhance-ments: lossless compression to improve effective bandwidth;error correction and fault tolerance to improve reliability. the interception layer is intended to add complex behaviour while maintaining the simplicity of the high-level abstraction when transmitting data via a channel. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Improving FPGA accelerated tracking with multiple online trained classifiers 24

Improving FPGA accelerated tracking with multiple online tra...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Jacobsen, Matthew Sampangi, Siddarth Freund, Yoav Kastner, Ryan Computer Science and Engineering University of California San Diego United States

ISBN: (纸本)9783000446450

Robust real time tracking is a requirement for many emerging applications. Many of these applications must track objects even as their appearance changes. Training classifiers online has become an effective approach for dealing with variability in object appearance. Classifiers can learn and adapt to changes online at the cost of additional runtime computation. In this paper, we propose a FPGA accelerated design of an online boosting algorithm that uses multiple classifiers to track and recover objects in real time. Our algorithm uses a novel method for training and comparing pose-specific classifiers along with adaptive tracking classifiers. Our FPGA accelerated design is able to track at 60 frames per second while concurrently evaluating 11 classifiers. this represents a 30× speed up over a CPU based software implementation. It also demonstrates tracking accuracy at state of the art levels on a standard set of videos. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Aging effects in FPGAs: An experimental analysis 24

Aging effects in FPGAs: An experimental analysis

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24th international conference on field programmable logic and applications, FPL 2014

作者： Amouri, Abdulazim Bruguier, Florent Kiamehr, Saman Benoit, Pascal Torres, Lionel Tahoori, Mehdi Karlsruhe Germany LIRMM CNRS - University of Montpellier 2 161 rue Ada cedex 534095 France

ISBN: (纸本)9783000446450

Modern field programmable Gate Arrays (FPGAs) are built using the most advanced technology nodes to meet performance and power demands. this makes them susceptible to various reliability challenges at nano-scale, and in particular to transistor aging. In this paper, an experimental analysis is made to identify the main parameters and phenomena influencing the performance degradation of FPGAs. For that purpose, a set of controlled ring-oscillator-based sensors with different frequencies and tunable activity control are implemented on a Spartan-6 FPGA. thus, the internal switching activities (SAs) and signal probabilities (SPs) of the sensors can be varied. We performed accelerated-lifetime conditions using elevated temperatures and voltages in a controlled setting to stress the FPGA. A novel monitoring method based on measuring the electromagnetic emissions of the FPGA is used to accurately monitor the performance of the sensors before and after the stress. the experiments reveal the extent of performance degradations, the impact of SPs and SAs, and the relative impacts of BTI and HCI aging factors. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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A bit-interleaved embedded hamming scheme to correct single-bit and multi-bit upsets for SRAM-based FPGAs 24

A bit-interleaved embedded hamming scheme to correct single-...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Venkataraman, Shyamsundar Santos, Rui Das, Anup Kumar, Akash Department of Electrical and Computer Engineering National University of Singapore Singapore Singapore

ISBN: (纸本)9783000446450

Single Event Upsets (SEUs) inadvertently change the configuration bits of Static-RAM (SRAM)-based field programmable Gate Arrays (FPGAs), leading to erroneous output until the error has been corrected. Scrubbing using an Error Correction Code (ECC) such as hamming is a popular method to correct such faults. However, current works either require a large external memory to store the ECCs or can at most correct only one error in a frame. this paper proposes a novel bit-interleaved embedded hamming scheme along with scrubbing, to correct single (SBUs) and multi-bit upsets (MBUs) in SRAM-based FPGAs. this scheme does not require an external memory to store the ECCs, as they are embedded within the configuration memory itself. Experiments conducted on various benchmarks show that the proposed scheme can handle multiple errors per frame very well, with an embedding efficiency of over 99.3%. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Interconnect for commodity FPGA clusters: Standardized or customized? 24

Interconnect for commodity FPGA clusters: Standardized or cu...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Markettos, A. theodore Fox, Paul J. Moore, Simon W. Moore, Andrew W. Computer Laboratory University of Cambridge United Kingdom

ISBN: (纸本)9783000446450

We demonstrate that a small library of customizable interconnect components permits low-area, high-performance, reliable communication tuned to an application, by analogy with the way designers customize their compute. Whilst soft cores for standard protocols (Ethernet, RapidIO, Infiniband, Interlaken) are a boon for FPGA-to-other-system interconnect, we argue that they are inefficient and unnecessary for FPGA-to-FPGA interconnect. Using the example of BlueLink, our lightweight pluggable interconnect library, we describe how to construct reliable FPGA clusters from hundreds of lower-cost commodity FPGA boards. Utilizing the increasing number of serial links on FPGAs demands efficient use of soft-logic, making domain-optimized custom interconnect attractive for some time to come. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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