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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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Interconnect for commodity FPGA clusters: Standardized or customized? 24

Interconnect for commodity FPGA clusters: Standardized or cu...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Markettos, A. theodore Fox, Paul J. Moore, Simon W. Moore, Andrew W. Computer Laboratory University of Cambridge United Kingdom

ISBN: (纸本)9783000446450

We demonstrate that a small library of customizable interconnect components permits low-area, high-performance, reliable communication tuned to an application, by analogy with the way designers customize their compute. Whilst soft cores for standard protocols (Ethernet, RapidIO, Infiniband, Interlaken) are a boon for FPGA-to-other-system interconnect, we argue that they are inefficient and unnecessary for FPGA-to-FPGA interconnect. Using the example of BlueLink, our lightweight pluggable interconnect library, we describe how to construct reliable FPGA clusters from hundreds of lower-cost commodity FPGA boards. Utilizing the increasing number of serial links on FPGAs demands efficient use of soft-logic, making domain-optimized custom interconnect attractive for some time to come. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Area implications of memory partitioning for high-level synthesis on FPGAs 24

Area implications of memory partitioning for high-level synt...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Gallo, Luca Cilardo, Alessandro thomas, David Bayliss, Samuel Constantinides, George A. University of Naples Federico II Via Claudio 21 Napoli80125 Italy Imperial College London LondonSW7 2BT United Kingdom

ISBN: (纸本)9783000446450

FPGAs normally have numerous independent memory banks that can be accessed simultaneously, potentially offering a very large memory bandwidth. Adopting a suitable application-based memory partitioning strategy is thus vital to take full advantage of the memory architecture. In addition to improving the potential memory bandwidth, partitioning also affects the area complexity of the generated system because the required steering logic depends on the partitioning scheme. this work describes the area implications of a lattice-based memory partitioning technique in the context of high-level synthesis for FPGAs. Experimental results with a commercial HLS tool show that the proposed partitioning technique improves area efficiency compared to alternative approaches. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs 24

High-level synthesis-based design methodology for Dynamic Po...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Ahmed, Rehan Bsoul, Assem A. M. Wilton, Steven J. E. Hallschmid, Peter Klukas, Richard University of British Columbia Canada Blackcomb Design Automation Canada

ISBN: (纸本)9783000446450

Static leakage power consumption is critical in modern FPGAs for many applications. Dynamic Power-Gating (DPG), in which parts of the FPGA in-use logic blocks are powered-down at run-time, is a promising technique to reduce the static power. Adoption of such emerging DPG enabled FPGA architectures remains challenging as the current tool-chains to program the FPGA does not support this type of power-gating. Moreover, manually identifying profitable power-gating opportunities in an application requires significant design expertise and is time consuming. In this paper, we propose a high-level synthesis-based design framework that exploits the dynamic power-gating feature of the FPGAs to minimize the static power dissipation. We use this framework on a set of CHStone benchmark suite and demonstrate that power-gating opportunities for hardware accelerators can be identified in an automatic way. Results show that up to 96% reduction in static energy is achieved for individual accelerators using dynamic power-gating technique. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Asynchronously assisted FPGA for variability 24

Asynchronously assisted FPGA for variability

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24th international conference on field programmable logic and applications, FPL 2014

作者： Low, Hock S. Shang, Delong Xia, Fei Yakovlev, Alex Systems Design Group Newcastle University Newcastle upon Tyne United Kingdom

ISBN: (纸本)9783000446450

the effect of variability has become increasingly significant as a result of technology geometry scaling. this paper describes Asynchronous Assisting logic (AAL) blocks and the method of introducing them into modern FPGA architecture, in order to increase tolerance of the wide range latency variations caused by parametric variation, and temperature and supply voltage fluctuations. the proposed method leverages the availability of variation maps and suggests deploying configurable AAL blocks only into the variation critical paths - reinforcing rather rerouting/remapping. this method reduces the size overhead significantly which normally will be incurred by fully asynchronous designs. the proposed technique maintains the existing FPGA architecture allowing potential reuse of design flow. Simulations show correct functionality given regularly variable, randomly variable and capacitor switching energy harvester voltage supplies. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Achieving portability and efficiency over chip heterogeneous multiprocessor systems 24

Achieving portability and efficiency over chip heterogeneous...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Cartwright, E. Sadeghian, Alborz Ma, Sen Andrews, David Dept. of Computer Science and Computer Engineering University of Arkansas Fayetteville United States

ISBN: (纸本)9783000446450

Emerging programming models for chip heterogeneous multiprocessor (CHMP) systems elevate architecture details up into the source code. this eliminates portability and requires designers to navigate a multidimensional search space when trying to optimize designs. In this paper, we present an approach that reinstates portability through a combination of polymorphic functions and an adaptive runtime system. Together they enable runtime profiling and dynamic scheduling of unaltered source code across systems with different combinations of heterogeneous resources. Our results verify the ability of our programming model and runtime system to re-enable the notion of writing code once and run anywhere. Runtime results show how runtime tuning can increase resource utilization and provide performance increases as the number and heterogeneity of computing resources increases. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Towards dark silicon era in FPGAs using complementary hard logic design 24

Towards dark silicon era in FPGAs using complementary hard l...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Ahari, Ali Khaleghi, Behnam Ebrahimi, Zahra Asadi, Hossein Tahoori, Mehdi B. Department of Computer Engineering Sharif University of Technology Tehran Iran Dependable Nano Computing Karlsruhe Institute of Technology Karlsruhe Germany

ISBN: (纸本)9783000446450

While the transistor density continues to grow exponentially in field-programmable Gate Arrays (FPGAs), the increased leakage current of CMOS transistors act as a power wall for the aggressive integration of transistors in a single die. One recently trend to alleviate the power wall in FPGAs is to turn off inactive regions of the silicon die, referred to as dark silicon. this paper presents a reconfigurable architecture to enable effective fine-grained power gating of unused logic Blocks (LBs) in FPGAs. In the proposed architecture, the traditional soft logic is replaced with Mega Cells (MCs), each consists of a set of complementary Generic Reconfigurable Hard logic (GRHL) and a conventional Look-Up Table (LUT). Both GRHL cells and LUTs can be power gated and turned off by controlling configuration bits. In the proposed MC, only one cell is active and the others are turned off. Experimental results on MCNC benchmark suite reveal that the proposed architecture reduces the critical path delay, power, and Power Delay Product (PDP) of LBs up to 5.3%, 30.4%, and 28.8% as compared to the equivalent LUT-based architecture. © 2014 Technical University of Munich (TUM).

关键词： Reconfigurable architectures

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Pipelined compressor tree optimization using integer linear programming 24

Pipelined compressor tree optimization using integer linear ...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Kumm, Martin Zipf, Peter University of Kassel Digital Technology Group Germany

ISBN: (纸本)9783000446450

Compressor trees offer an effective realization of the multiple input addition needed by many arithmetic operations. However, mapping the commonly used carry save adders (CSA) of classical compressor trees to FPGAs suffers from a poor resource utilization. this can be enhanced by using generalized performance counters (GPCs). Prior work has shown that high efficient GPCs can be constructed by exploiting the low-level structure of the FPGA. However, due to their irregular shape, the selection of those is not straight forward. Furthermore, the compressor tree has to be pipelined to achieve the potential FPGA performance. then, a selection between registered GPCs or flip-flops has to be done to balance the pipeline. this work defines the pipelined compressor tree synthesis as an optimization problem and proposes a (resource) optimal method using integer linear programming (ILP). Besides that, two new GPC mappings with high efficiency are proposed for Xilinx FPGAs. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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A Scalable and Compact Systolic Architecture for Linear Solvers

A Scalable and Compact Systolic Architecture for Linear Solv...

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IEEE 25th international conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Ong, Kevin S. H. Fahmy, Suhaib A. Ling, Keck-Voon Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore

ISBN: (纸本)9781479936090

We present a scalable design for accelerating the problem of solving a dense linear system of equations using LU Decomposition. A novel systolic array architecture that can be used as a building block in scientific applications is described and prototyped on a Xilinx Virtex 6 FPGA. this solver has a throughput of around 3.2 million linear systems per second for matrices of size N= 4 and around 80 thousand linear systems per second for matrices of size N= 16. In comparison with similar work, our design offers up to a 12-fold improvement in speed whilst requiring up to 50% less hardware resources. As a result, a linear system of size N= 64 can be implemented on a single FPGA, whereas previous work was limited to a size of N= 12 and resorted to complex multi-FPGA architectures to scale. Finally, the scalable design can be adapted to different sized problems with minimum effort.

关键词： Linear system Scalability matrices Solvers ARCHITECTURE Linear system of equations Building construction field programmable gate arrays throughput array structure

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An FPGA sliding window-based architecture Harris corner detector 24

An FPGA sliding window-based architecture Harris corner dete...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Amaricai, Alexandru Gavriliu, Constantina-Elena Boncalo, Oana University Politehnica Timisoara Computer Engineering Department Timisoara Romania

ISBN: (纸本)9783000446450

this paper proposes a FPGA implementation based on sliding processing window for Harris corner algorithm. It represents one of the most frequently used pre-processing method, for a wide variety of image processing algorithms, such as feature detection, motion tracking, image registration, etc It relies on a series of sequential steps, each processing an image outputted by the previous step. the purpose of the sliding window is to avoid storing intermediate results of processing stages in the external FPGA memory or to avoid utilize large line buffers typically implemented with BRAM blocks. therefore, the entire processing pipeline benefits from data locality. Implementation results for Virtex5 and Spartan-6 devices show that the proposed solution has very good performance (more than 130 fps for 1280×720 images in Xilinx Spartan-6) with significant less BRAM usage with respect to other approaches. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Incremental distributed trigger insertion for efficient FPGA debug 24

Incremental distributed trigger insertion for efficient FPGA...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Eslami, Fatemeh Wilton, Steven J.E. Department of Electrical and Computer Engineering University of British Columbia Vancouver Canada

ISBN: (纸本)9783000446450

FPGA-based prototyping enables evaluating complex designs directly in hardware, at speeds orders of magnitude faster than simulation. However, this approach suffers from the lack of observability during debugging. To enhance observability, designers insert debug instrumentation;trace buffers are used to record a small subset of data. Since these buffers have limited capacity, trigger circuits are required to start and/or stop recording based on the values of selected signals in the circuit. Although it is possible to insert trigger circuits at compile time, changing the trigger behaviour requires re-compiling the design, increasing the cost of each debug iteration. In this paper, we propose inserting trigger circuits at run-time by distributing trigger logic over spare resources of a fully placed-and-routed design such that its mapping is completely preserved. We also propose CAD optimizations which improve routability of the trigger circuitry, and minimize the impact on circuit delay. We find that using our techniques to implement the trigger logic can be an order of magnitude faster than a full recompilation. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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