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Accurate power control and monitoring in ZYNQ boards 24

Accurate power control and monitoring in ZYNQ boards

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24th international conference on field programmable logic and applications, FPL 2014

作者： Beldachi, Arash Farhadi Nunez-Yanez, Jose L. Department of Electronic Engineering University of Bristol Bristol United Kingdom

ISBN: (纸本)9783000446450

ZYNQ devices combine a dual-core ARM Cortex A9 processor and a FPGA fabric in the same die and in different power domains. In this paper we investigate the run-time power scaling capabilities of these devices using of-the-shelf boards and proposed accurate and fine-grained power control and monitoring techniques. the experimental results show that both software and hardware methods are possible and the right selection can yield different results in terms of control and monitoring speeds, accuracy of measurement, power consumption, and area overhead. the results also demonstrate that significant power margins are available in the FPGA device with different voltage configurations possible. this can be used to complement traditional voltage scaling techniques applied to the processor domain to obtain hybrid energy proportional computing platforms. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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A semi-supervised modeling approach for performance characterization of FPGA architectures 24

A semi-supervised modeling approach for performance characte...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Yang, Liqun Yang, Haigang Li, Wei Li, Zhihua Huang, Zhihong Lin, Colin Yu University of Chinese Academy of Sciences China System on Programmable Chip Research Department Institute of Electronics Chinese Academy of Sciences China

ISBN: (纸本)9783000446450

An approach to estimate the performance of FPGA architectures is proposed based on semi-supervised model tree algorithm. the proposed approach avoids synthesizing, mapping, packing, placing and routing, which are essential steps in a traditional flow to obtain the performance of FPGA. thus it is time efficient while the performance predicted maintains quite close to the result obtained through the traditional method (a tool flow called VTR). this can be utilized effectively during the early FPGA design stage to choose an optimal architecture under a certain metric. Comparisons are made between the performance obtained by the proposed approach and by VTR on a commercial 40nm technology. Results show that the proposed approach has MRE below 7.62% compared to VTR, and improves the time cost by thousands of times when utilized in architecture design space exploration. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Function-Level Processor (FLP): Raising Efficiency by Operating at Function Granularity for Market-Oriented MPSoC

Function-Level Processor (FLP): Raising Efficiency by Operat...

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IEEE 25th international conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Tabkhi, Hamed Bushey, Robert Schirner, Gunar Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA Analog Devices Inc ADI Embedded Syst Prod & Technol Norwood MA USA

ISBN: (纸本)9781479936090

the exponential growth in computation demand drives chip vendors to heterogeneous architectures combining Instruction-Level Processors (ILPs) and custom HW Accelerators (HWACCs) in an attempt to provide the needed processing capabilities while meeting power/energy requirements. ILPs, on one hand, are highly flexible, but power inefficient. Custom HWACCs, on the other hand, are inflexible (focusing on dedicated kernels), but highly power efficient. Since, designing HWACCs for every application is cost prohibitive, large portions of applications still run inefficiently on ILPs. New processing architectures are needed that combine the power efficiency of HWACCs while still retaining sufficient flexibility to realize applications across targeted market segments. this paper introduces Function-Level Processors (FLPs) to fill the gap between ILPs and dedicated HWACCs. FLPs are comprised of configurable Function Blocks (FBs) implementing selected functions which are then interconnected via programmable point-to-point connections constructing an extensible/configurable macro data-path. An FLP raises programming abstraction to a Function-Set Architecture (FSA) controlling FBs allocation, configuration and scheduling. We demonstrate FLP benefits with an industry example of the Pipeline-Vision Processor (PVP). We highlight the gained flexibility by mapping 10 embedded vision applications entirely to the FLP-PVP offering up to 22.4 GOPs/s with average power of 120 mW. the results also demonstrate that our FLP-PVP solution consumes 14x-18x less power than an ILP and 5x less power than a hybrid ILP+ HWACCs solution.

关键词： fault-location problem PROCESSOR inductive logic programming dynamic efficiency Exponential Growth average power ARCHITECTURE Power (Psychology) Energy sources macro data Target marketing Connection points

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Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security 24

Balancing WDDL dual-rail logic in a tree-based FPGA to enhan...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Amouri, Emna Bhasin, Shivam Mathieu, Yves Graba, Tarik Danger, Jean-Luc Mehrez, Habib Departement COMELEC 46 rue Barrault Paris France LIP6 Universite Pierre et Marie Curie 4 Place Jussieu Paris France

ISBN: (纸本)9783000446450

the Tree-based FPGA offers better density and timing determinism than traditional mesh-based FPGA. Moreover, thanks to its multilevel structure, it offers greater easiness to balance dual signals in terms of routing resources number. In this paper, we study the use of the Wave Dynamic Differential logic (WDDL) on a custom tree-based FPGA of 2048 cells. the WDDL technique offers an effective way to withstand Differential Power Attacks (DPA). However, the effectiveness of this countermeasure is guaranteed provided a symmetry is maintained between the routing of both the direct and complementary paths, which is very hard to achieve in FPGA. thus, balancing aware Computer-Aided Design (CAD) tools must be developed. In this work, we propose first adjacent placement and balancing-aware routing techniques for tree-based FPGA to counter the routing unbalance. then side channel analyses are performed on FPGA circuit implementing PRESENT crypto-processor. Experimental results show that the balancing methods enhance the design security against side channel attacks. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Transparent insertion of latency-oblivious logic onto FPGAs 24

Transparent insertion of latency-oblivious logic onto FPGAs

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24th international conference on field programmable logic and applications, FPL 2014

作者： Hung, Eddie Todman, Tim Luk, Wayne Department of Computing Imperial College London United Kingdom

ISBN: (纸本)9783000446450

We present an approach for inserting latency-oblivious functionality into pre-existing FPGA circuits transparently. To ensure transparency - that such modifications do not affect the design's maximum clock frequency - we insert any additional logic post place-and-route, using only the spare resources that were not consumed by the pre-existing circuit. the typical challenge with adding new functionality into existing circuits incrementally is that spare FPGA resources to host this functionality must be located close to the input signals that it requires, in order to minimise the impact of routing delays. In congested designs, however, such co-location is often not possible. We overcome this challenge by using flow techniques to pipeline and route signals from where they originate, potentially in a region of high resource congestion, into a region of low congestion capable of hosting new circuitry, at the expense of latency. We demonstrate and evaluate our approach by augmenting realistic designs with self-monitoring circuitry, which is not sensitive to latency. We report results on circuits operating over 200MHz and show that our insertions have no impact on timing, are 2-4 times faster than compile-time insertion, and incur only a small power overhead. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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An FPGA hardware acceleration of the indirect calculation of tree lengths method for phylogenetic tree reconstruction 24

An FPGA hardware acceleration of the indirect calculation of...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Block, Henry Maruyama, Tsutomu Systems and Information Engineering University of Tsukuba 1-1-1 Ten-ou-dai Tsukuba305-8573 Japan

ISBN: (纸本)9783000446450

In this work, we present an FPGA hardware implementation for a phylogenetic tree reconstruction with maximum parsimony algorithm. We base our approach on a particular stochastic local search algorithm that uses the Indirect Calculation of Tree Lengths method and the Progressive Neighborhood. In our implementation, we define a tree structure, and accelerate the search by parallel and pipeline processing. We show results for six real-world biological datasets. We compare execution times against our previous hardware approach, and TNT, the fastest available parsimony program. Acceleration rates between 34 to 45 per rearrangement, and 2 to 6, for the whole search, are obtained against our previous approach. Acceleration rates between 2 to 4 per rearrangement, and 18 to 112, for the whole search, are obtained against TNT. We estimate that these acceleration rates could increase for even larger datasets. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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FPGA acceleration of short read mapping based on sort and parallel comparison 24

FPGA acceleration of short read mapping based on sort and pa...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Sogabe, Youkou Maruyama, Tsutomu Systems and Information Engineering University of Tsukuba 1-1-1 Ten-ou-dai Ibaraki305-8573 Japan

ISBN: (纸本)9783000446450

Short read mapping is a process to align the short reads, which are fixed-length fragments of the target genome, to a given reference genome to identify the mutations in the target genome. Because of the rapid development of Next Generation Sequencing (NGS) technologies, faster short read mapping is required. In this paper, we propose an FPGA system for the short read mapping based on sort and parallel comparison of seeds. Seeds are fixed-length sub-strings in the short reads used to map the short read to the reference genome efficiently. In our system, (1) seeds are sorted using bucket sort, and the seeds in a bucket are compared in parallel with the candidate locations on the reference genome, (2) in this comparison, one nucleotide substitution, insertion, and deletion are allowed to achieve higher mapping rate, and (3) two stage search by reconfiguration is used to achieve higher performance. the mapping rate and search time by this approach outperforms existing systems. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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A high performance alternating projections image demosaicing hardware 24

A high performance alternating projections image demosaicing...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Azgin, Hasan Yaliman, Serkan Hamzaoglu, Ilker Faculty of Engineering and Natural Sciences Sabanci University Tuzla Istanbul34956 Turkey

ISBN: (纸本)9783000446450

Since capturing three color channels (red, green, and blue) per pixel increases the cost of digital cameras, most digital cameras capture only one color channel per pixel using a single image sensor. the images pass through a color filter array before being captured by the image sensor. Demosaicing is the process of reconstructing the missing color channels of the pixels in the color filtered image using their available neighboring pixels. Alternating Projections (AP) is one of the highest quality image demosaicing algorithms, and it has very high computational complexity. therefore, in this paper, a high performance AP image demosaicing hardware is proposed. this is the first AP image demosaicing hardware in the literature. the proposed hardware is implemented using Verilog HDL. the Verilog RTL code is verified to work correctly in a Xilinx Virtex 6 FPGA. the FPGA implementation can process 31 full HD (1920×1080) images per second. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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High-precision self-characterization for the LUT burn-in information leakage threat 24

High-precision self-characterization for the LUT burn-in inf...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Zick, Kenneth M. Li, Sen French, Matthew ArlingtonVA United States

ISBN: (纸本)9783000446450

Information security in FPGAs is at risk;during system operation, data and usage patterns can potentially get imprinted into a chip's physical characteristics, allowing an attacker to later recover intellectual property or cryptographic secrets. Can 'data burn-in' vulnerabilities in FPGAs be characterized at low cost? Specifically, can slight shifts in path delays due to burn-in be measured with enough precision? this paper contributes methods for self-characterization of delay changes using novel isolation of key FPGA transistors, improved clock sweeping, and enhanced estimation from launch-andcapture data. Hardware experiments on 2048 Xilinx Kintex-7 paths demonstrate measurement precision of 30-60 femtoseconds, which is more than 10× finer than previous self-characterization results. Further, results show that unintentional burn-in of FPGA LUT contents does indeed occur and can in some cases be detected within a single week, highlighting the need to deploy countermeasures. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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the LEAP FPGA operating system 24

The LEAP FPGA operating system

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24th international conference on field programmable logic and applications, FPL 2014

作者： Fleming, Kermin Yang, Hsin-Jung Adler, Michael Emer, Joel VSSAD Group Intel Corporation United States Computer Science and A.I. Laboratory Massachusetts Institute of Technology United States

ISBN: (纸本)9783000446450

FPGAs offer attractive power and performance for many applications, especially relative to traditional sequential architectures. In spite of these advantages, FPGAs have been deployed in only a few, niche *** argue that the difficulty of programming FPGAs all but precludes their use in more general systems: FPGA programmers are currently exposed to all the gory system details that software operating systems long ago abstracted away. In this work, we present the Latency-insensitive Environment for Application Programming (LEAP), an FPGA operating system built around latency-insensitive communications channels. LEAP alleviates the FPGA programming problem by providing a rich set of portable latency-insensitive abstraction layers for program development. Unlike software operating systems services, which are generally dynamic, the nature of FPGAs requires that many configuration decisions be made at compile time. We present an extensible interface for compile-time management of resources. We demonstrate that LEAP provides design portability, while consuming as little as 3% of FPGA area, by mapping several designs on to various FPGA platforms. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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