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Run-time power gating in hybrid ARM-FPGA devices 24

Run-time power gating in hybrid ARM-FPGA devices

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24th international conference on field programmable logic and applications, FPL 2014

作者： Hosseinabady, Mohammad Nunez-Yanez, Jose Luis Department of Electrical and Electronic Engineering University of Bristol United Kingdom

ISBN: (纸本)9783000446450

Energy proportional computing (EPC) enables the allocation of energy to tasks depending on computational demands. Computing at full speed and then dynamically turning off modules when they are not required for a period of time can be used to obtain EPC and it is an alternative to voltage scaling techniques in which the computation is slowed down. this paper investigates the viability of physical power gating FPGA devices that incorporate a hardened processor in a different power domain. the run-time power gating approach is applied to Xilinx ZYNQ devices that incorporate a hardened Cortex A9 multi-processor. the paper demonstrates that power down followed by a full reconfiguration can be controlled by the embedded processor autonomously. the results show that the minimum time that the FPGA fabric must remain in power-off state for the technique to be energy efficient is in the order of milliseconds and up to 96% power reduction occurs when the fabric voltage is lowered below critical level. these results take into account the overheads of controlling the programmable voltage regulators interfaced to the FPGA and the overhead of the reconfiguration needed when the device must be returned to the active state. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Low Latency FPGA Acceleration of Market Data Feed Arbitration

Low Latency FPGA Acceleration of Market Data Feed Arbitratio...

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IEEE 25th international conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Denholm, Stewart Inoue, Hiroaki Takenaka, Takashi Becker, Tobias Luk, Wayne Univ London Imperial Coll Sci Technol & Med Dept Comp London England NEC Corp Ltd Kawasaki Kanagawa Japan

ISBN: (纸本)9781479936090

A critical source of information in automated trading is provided by market data feeds from financial exchanges. Two identical feeds, known as the A and B feeds, are used in reducing message loss. this paper presents a reconfigurable acceleration approach to A/B arbitration, operating at the network level, and supporting any messaging protocol. the key challenges are: providing efficient, low latency operations;supporting any market data protocol;and meeting the requirements of downstream applications. To facilitate a range of downstream applications, one windowing mode prioritising low latency, and three dynamically configurable windowing methods prioritising high reliability are provided. We implement a new low latency, high throughput architecture and compare the performance of the NASDAQ TotalView-ITCH, OPRA and ARCA market data feed protocols using a Xilinx Virtex-6 FPGA. the most resource intensive protocol, TotalView-ITCH, is also implemented in a Xilinx Virtex-5 FPGA within a network interface card. We offer latencies 10 times lower than an FPGA-based commercial design and 4.1 times lower than the hardware-accelerated IBM PowerEN processor, with throughputs more than double the required 10Gbps line rate.

关键词： Arbitrating Network interface cards Information source network level Latency FEEDS Fodder field programmable gate arrays protocols Telemarketing multiprogramming acceleration configurability

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the hardware implementation of a quantum computation system emulator 19

The hardware implementation of a quantum computation system ...

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19th international conference on Applied Electronics (AE)

作者： Ionescu, Laurentiu-Mihai Mazare, Alin Anton, Constantin Stoian, Catalin Univ Pitesti Dept Elect Comp & Elect Engn Pitesti Romania Tech Coll Dimitrie Dima Pitesti Romania

ISBN: (纸本)9788026102762

the quantum computing represents a new field, which is still being researched, that may have numerous applications in the computer arithmetic, in the encryption - decryption systems, rapid search algorithms and physical systems' emulations. the hardware device that can make this type of calculations is still expensive nowadays and the number of the manufacturers is reduced. On the other hand, the simulation of a quantum computer using the devices currently available on the market - like the FPGA digital circuits - helps in getting an overview of the possibilities that the quantum calculations can provide and it can also be used when simulating physical processes in general. the aim of this article is to present our own solution of an emulator for the quantum calculations using the digital modules implemented in FPGA.

关键词： field programmable gate arrays quantum computing FPGA digital circuits quantum computation system emulator Computational modeling Computers Decoding field programmable gate arrays Integrated circuit modeling logic gates Quantum computing quantum computing field programmable gate arrays integrated circuit modelling logic gates Computational modeling Computers DECODING Emulators Quantum computers

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FPGA architecture support for heterogeneous, relocatable partial bitstreams 24

FPGA architecture support for heterogeneous, relocatable par...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Huriaux, Christophe Sentieys, Olivier Tessier, Russell University of Rennes 1 IRISA Lannion France Inria IRISA Lannion France Department of Electrical and Computer Engineering University of Massachusetts AmherstMA01003 United States

ISBN: (纸本)9783000446450

the use of partial dynamic reconfiguration in FPGA-based systems has grown in recent years as the spectrum of applications which use this feature has increased. For these systems, it is desirable to create a series of partial bitstreams which represent tasks which can be located in multiple regions in the FPGA fabric. While the transferal of homogeneous collections of lookup-table based logic blocks from region to region has been shown to be relatively straightforward, it is more difficult to transfer partial bitstreams which contain fixed-function resources, such as block RAMs and DSP blocks. In this paper we consider FPGA architecture enhancements which allow for the migration of partial bitstreams including fixed-function resources from region to region even if these resources are not located in the same position in each region. Our approach does not require significant, time-consuming place-and-route during the migration process. We quantify the cost of inserting additional routing resources into the FPGA architecture to allow for easy migration of heterogeneous, fixed-function resources. Our experiments show that this flexibility can be added for a relatively low overhead and performance penalty. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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PR-HMPSoC: A versatile partially reconfigurable heterogeneous Multiprocessor System-on-Chip for dynamic FPGA-based embedded systems 24

PR-HMPSoC: A versatile partially reconfigurable heterogeneou...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Nguyen, Tuan D. A. Kumar, Akash Department of Electrical and Computer Engineering National University of Singapore 4 Engineering Drive 3 Singapore117583 Singapore

ISBN: (纸本)9783000446450

FPGA-based heterogeneous Multiprocessor Systems-on-Chip (HMPSoCs) are becoming quite popular for high performance embedded systems because of their powerful computational ability and relatively flexible architecture to adapt to unexpected system requirement changes. However, with the insatiable demands of supporting an extensive range of applications beyond the limited resources of FPGA chip and shorter time-to-market, many research works on partially reconfigurable (PR) FPGA architectures have been conducted to fulfill the needs. those have yet to fully provide a versatile framework to exploit the flexibility of PR such as hardware/software task migration and bitstream relocation;more importantly, the on-chip debug features to access all processors currently loaded in the system are compromised because of the lack of native-support from vendor tools. In this paper, a novel PR-HMPSoC architecture for dynamic FPGA-based embedded system is proposed to provide solutions for all of the above issues. the results from the experimental system consisting of one static Microblaze and three PR Microblaze/hardware accelerators connected by a Network-on-Chip show that the architecture is very promising with just 8% reduction in operating frequency. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Multi-FPGA reconfigurable system for accelerating MATLAB simulations 24

Multi-FPGA reconfigurable system for accelerating MATLAB sim...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Al Kadi, Muhammed Ferger, Max Stegemann, Volker Hubner, Michael Ruhr-University Bochum Bochum Germany

ISBN: (纸本)9783000446450

the use of reconfigurable FPGA devices to support the execution of computationally intensive software tasks is discussed in this paper. A system architecture consisting of multiple serially-connected FPGAs is developed, where each FPGA holds a pool of reconfigurable regions. An accelerator can be reconfigured into a region, replaced or discarded at runtime. Configurable connection blocks are responsible of directing data between any two accelerators. the whole system is connected via PCIe-interface to a host PC, where a middleware layer hides all hardware management operations, e.g. routing the data sent among the accelerators, and provides the end-user with an API to use the whole system. Recently, the very fast interfaces for reconfiguring parts of the used FPGAs minimize the overhead caused for hardware modifications. In addition, a manual design of hardware accelerators is not more needed with the continuously improving quality of high-level synthesis tools. In this paper, we considered the case where our system is used within MATLAB. We build a small library to compare and improve upon the execution times of some often used functions. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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An efficient FPGA-based hardware framework for natural feature extraction and related Computer Vision tasks 24

An efficient FPGA-based hardware framework for natural featu...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Pohl, Matthias Schaeferling, Michael Kiefer, Gundolf University of Applied Sciences Augsburg Dept. of Computer Science An der Hochschule 1 Augsburg86161 Germany

ISBN: (纸本)9783000446450

the paper presents an efficient and flexible framework for extensive image processing tasks. While most available frameworks concentrate on pixel-based modules and interfaces for image preprocessing tasks, our proposal also covers the seamless integration of higher-level algorithms. Window-oriented filter operations, such as noise filters, edge filters or natural feature detectors, are performed within an efficient 2D window pipeline. this structure is generated and optimized automatically based on a user-defined filter configuration. For complex, higher-level algorithms, an optimized array of independent, software-based processing units is generated. As an example application, we chose object recognition based on the well-known SURF algorithm ('Speeded Up Robust Features'), which performs natural feature detection and description. All involved image processing steps were successfully mapped to our architecture. thus, exploiting the FPGAs full potential regarding parallelism, we synthesized one of the most efficient SURF detectors and a complete object recognition system in a single mid-size FPGA. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Compiling text analytics queries to FPGAs 24

Compiling text analytics queries to FPGAs

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24th international conference on field programmable logic and applications, FPL 2014

作者： Polig, Raphael Atasu, Kubilay Giefers, Heiner Chiticariu, Laura IBM Research - Zurich Rueschlikon Switzerland IBM Research - Almaden San JoseCA United States

ISBN: (纸本)9783000446450

Extracting information from unstructured text data is a compute-intensive task. the performance of general-purpose processors cannot keep up with the rapid growth of textual data. therefore we discuss the use of FPGAs to perform large scale text analytics. We present a framework consisting of a compiler and an operator library capable of generating a Verilog processing pipeline from a text analytics query specified in the annotation query language AQL. the operator library comprises a set of configurable modules capable of performing relational and extraction tasks which can be assembled by the compiler to represent a full annotation operator graph. Leveraging the nature of text processing we show that most tasks can be performed in an efficient streaming fashion. We evaluate the performance, power consumption and hardware utilization of our approach for a set of different queries compiled to a Stratix IV FPGA. Measurements show an up to 79 times improvement of document-throughput over a 64 threaded software implementation on a POWER7 server. Moreover the accelerated system's energy efficiency is up to 85 times better. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Heterogeneous dataflow architectures for FPGA-based sparse LU factorization 24

Heterogeneous dataflow architectures for FPGA-based sparse L...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Siddhartha Kapre, Nachiket School of Computer Engineering Nanyang Technological University 50 Nanyang Avenue SingaporeS639798 Singapore

ISBN: (纸本)9783000446450

FPGA-based token dataflow architectures with heterogeneous computation and communication subsystems can accelerate hard-to-parallelize, irregular computations in sparse LU factorization. We combine software pre-processing and architecture customization to fully expose and exploit the underlying heterogeneity in the factorization algorithm. We perform a one-time pre-processing of the sparse matrices in software to generate dataflow graphs that capture raw parallelism in the computation through substitution and reassociation transformations. We customize the dataflow architecture by picking the right mixture of addition and multiplication processing elements to match the observed balance in the dataflow graphs. Additionally, we modify the network-onchip to route certain critical dependencies on a separate, faster communication channel while relegating less-critical traffic to the existing channels. Using our techniques, we show how to achieve speedups of up to 37% over existing state-of-the-art FPGA-based sparse LU factorization systems that can already run 3-4× faster than CPU-based sparse LU solvers using the same hardware constraints. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Patra: Parallel tree-reweighted message passing architecture 24

Patra: Parallel tree-reweighted message passing architecture

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24th international conference on field programmable logic and applications, FPL 2014

作者： Zhao, Wenlai Fu, Haohuan Yang, Guangwen Luk, Wayne Department of Computer Science and Technology Tsinghua University China Ministry of Education Key Laboratory for Earth System Modeling Center for Earth System Science Tsinghua University China China Department of Computing Imperial College London United Kingdom

ISBN: (纸本)9783000446450

Maximum a posteriori probability inference algorithms for Markov Random field are widely used in many applications, such as computer vision and machine learning. Sequential tree-reweighted message passing (TRW-S) is an inference algorithm which shows good quality in finding optimal solutions. However, the performance of TRW-S in software cannot meet the requirements of many real-time applications, due to the sequential scheme and the high memory, bandwidth and computational costs. this paper proposes Patra, a novel parallel tree-reweighted message passing architecture, which involves a fully pipelined design targeting FPGA technology. We build a hybrid CPU/FPGA system to test the performance of Patra for stereo matching. Experimental results show that Patra provides about 100 times faster than a software implementation of TRW-S, and 12 times faster than a GPU-based message passing algorithm. Compared with an existing design in four FPGAs, we can achieve 2 times speedup in a single FPGA. Moreover, Patra can work at video rate in many cases, such as a rate of 167 frame/sec for a standard stereo matching test case, which makes it promising for many real-time applications. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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