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First results of the silicon telescope using an ‘artificial retina’ for fast track finding

First results of the silicon telescope using an ‘artificial...

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international conference on Advancements in Nuclear Instrumentation Measurement Methods and their applications (ANIMMA)

作者： N. Neri A. Abba F. Bedeschi F. Caponio R. Cenci M. Citterio S. Coelli J. Fu A. Geraci M. Grizzuti N. Lusardi P. Marino M. Monti M. J. Morello D. Ninci M. Petruzzo A. Piucci G. Punzi L. Ristori F. Spinella S. Stracka D. Tonelli J. Walsh Sezione di Milano Istituto Nazionale di Fisica Nucleare (INFN) Milano Italy INFN Milano Politecnico di Milano Milano Italy INFN Pisa Pisa Italy INFN Pisa Scuola Normale Superiore di Pisa Pisa Italy INFN Milano Milano Italy INFN Pisa Universitá di Pisa Pisa Italy Fermilab Batavia Illinois USA CERN Geneva Switzerland

We present the first results of the prototype of a silicon tracker with trigger capabilities based on a novel approach for fast track finding. the working principle of the "artificial retina" is inspired by the processing of visual images by the brain and it is based on extensive parallelisation of data distribution and pattern recognition. the algorithm has been implemented in commercial FPGAs in three main logic modules: a switch for the routing of the detector hits, a pool of engines for the digital processing of the hits, and a block for the calculation of the track parameters. the architecture is fully pipelined and allows the reconstruction of real-time tracks with a latency less then 100 clock cycles, corresponding to 0.25 microsecond at 400 MHz clock. the silicon telescope consists of 8 layers of single-sided silicon strip detectors with 512 strips each. the detector size is about 10 cm × 10 cm and the strip pitch is 183 μm. the detectors are read out by the Beetle chip, a custom ASICs developed for LHCb, which provides the measurement of the hit position and pulse height of 128 channels. the "artificial retina" algorithm has been implemented on custom data acquisition boards based on FPGAs Xilinx Kintex 7 lx 160. the parameters of the tracks detected are finally transferred to host PC via USB 3.0. the boards manage the read-out ASICs and the sampling of the analog channels. the read-out is performed at 40 MHz on 4 channels for each ASIC that corresponds to a decoding of the telescope information at 1.1 MHz. We report on the first results of the fast tracking device and compare with simulations.

关键词： Retina Telescopes field programmable gate arrays Detectors Prototypes Switches Engines

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A soft-core processor for finite field arithmetic with a variable word size accelerator 24

A soft-core processor for finite field arithmetic with a var...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Iwasaki, Aiko Dohi, Keisuke Shibata, Yuichiro Oguri, Kiyoshi Harasawa, Ryuichi Graduate School of Engineering Nagasaki University 1-14 Bunkyo Japan

ISBN: (纸本)9783000446450

this paper presents implementation and evaluation of an accelerator architecture for soft-cores to speed up reduction process for the arithmetic on GF(2m) used in Elliptic Curve Cryptography (ECC) systems. In this architecture, the word size of the accelerator can be customized when the architecture is configured on an FPGA. Focusing on the fact that the number of the reduction processing operations on GF(2m) is affected by the irreducible polynomial and the word size, we propose to employ an unconventional word size for the accelerator depending on a given irreducible polynomial and implement a MIPS-based soft-core processor coupled with a variable-word size accelerator. As a result of evaluation with several polynomials, it was shown that the performance improvement of up to 10.2 times was obtained compared to the 32-bit word size, even taking into account the maximum frequency degradation of 20.4% caused by changing the word size. the advantage of using unconventional word sizes was also shown, suggesting the promise of this approach for low-power ECC systems. © 2014 Technical University of Munich (TUM).

关键词： Architecture

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A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems 24

A dynamically adaptable bus architecture for trading-off amo...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Valverde, J. Rodriguez, A. Camarero, J. Otero, A. Portilla, J. De La Torre, E. Riesgo, T. Centro de Electrónica Industrial - CEI Universidad Politécnica de Madrid Madrid Spain

ISBN: (纸本)9783000446450

Cyber-Physical Systems need to handle increasingly complex tasks, which additionally, may have variable operating conditions over time. therefore, dynamic resource management to adapt the system to different needs is required. In this paper, a new bus-based architecture, called ARTICo3, which by means of Dynamic Partial Reconfiguration, allows the replication of hardware tasks to support module redundancy, multi-thread operation or dual-rail solutions for enhanced side-channel attack protection is presented. A configuration-aware data transaction unit permits data dispatching to more than one module in parallel, or provide coalesced data dispatching among different units to maximize the advantages of burst transactions. the selection of a given configuration is application independent but context-aware, which may be achieved by the combination of a multi-thread model similar to the CUDA kernel model specification, combined with a dynamic thread/task/kernel scheduler. A multi-kernel application for face recognition is used as an application example to show one scenario of the ARTICo3 architecture. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays 24

Tile-based bottom-up compilation of custom mesh-of-functiona...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Correction Capalija, Davor Abdelrahman, Tarek S. Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto TorontoON Canada

ISBN: (纸本)9783000446450

Mesh-of-functional-units (mesh-of-FUs) overlays can deliver high-performance because they expose the massively parallel FPGA fabric and have the ability to be customized for different applications. However, a key challenge is how to quickly compile a number of custom mesh-of-FUs overlays to FPGA fabric such that they achieve high fMAXand scale to large mesh sizes. We propose a tile-based bottom-up CAD flow that utilizes the hierarchical physical design techniques of partitioning and floorplanning. Our flow partitions the overlay circuit into tiles, groups of adjacent overlay cells, and then compiles the tiles to a rectangular coarse-grain floorplan. Independent compilation of tiles is made possible by inserting complementary elastic buffers on inter-tile paths to ensure that these paths are not a bottleneck for fMAX. As a result, an overlay can be formed by only 'stitching' a set of pre-compiled *** show that compared to the flat flow, our bottom-up flow results in higher fMAXthat degrades little with increasing overlay size. Further, our flow can generate a library of pre-compiled tiles that can be reused - it can stitch a set of library tiles into a new overlay in only 35 minutes. It also allows a divide-and-conquer overlay compilation flow by compiling its tiles in parallel on multiple machines. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Adaptive Dynamic On-chip Memory Management for FPGA-based reconfigurable architectures 24

Adaptive Dynamic On-chip Memory Management for FPGA-based re...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Dessouky, Ghada Klaiber, Michael J. Bailey, Donald G. Simon, Sven Institute for Parallel and Distributed Systems University of Stuttgart Germany School of Engineering and Advanced Technology Massey University Palmerston North New Zealand

ISBN: (纸本)9783000446450

In this paper, an adaptive architecture for dynamic management and allocation of on-chip FPGA Block Random Access Memory (BRAM) resources is presented. this facilitates the dynamic sharing of valuable and scarce on-chip memory among several processing elements (PEs), according to their dynamic run-time memory requirements. Different real-time applications are becoming increasingly dynamic which leads to unexpected and variable memory footprints, and static allocation of the worst-case memory requirements would result in costly overheads and inefficient memory utilization. the proposed scalable BRAM memory management architecture adaptively manages these dynamic memory requirements and balances the buffer memory over several PEs to reduce the total memory required, compared to the worst-case memory footprint for all PEs. the run-time adaptive system allocates BRAM to each PE sufficiently fast enough as required and utilized. In a case study, a significant improvement in BRAM utilization with limited overhead has been achieved due to the adaptive memory management architecture. the proposed system supports different BRAM types and configurations, and automated dynamic allocation and deallocation of BRAM resources, and is therefore well suited for the dynamic memory footprints of FPGA-based reconfigurable architectures. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Power-efficient re-gridding architecture for accelerating Non-uniform Fast Fourier Transform 24

Power-efficient re-gridding architecture for accelerating No...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Cheema, Umer I. Nash, Gregory Ansari, Rashid Khokhar, Ashfaq A. Department of Electrical and Computer Engineering University of Illinois at Chicago Chicago United States Department of Electrical and Computer Engineering Illinois Institute of Technology Chicago United States

ISBN: (纸本)9783000446450

this paper proposes a novel FPGA-based accelerator for the memory and compute-intense re-gridding process used in computation of Non-uniform Fast Fourier Transform (NuFFT). the re-gridding process interpolates arbitrary sampled data onto a uniform grid using an interpolation kernel function. this regridding step is considered one of the most time consuming step in entire NuFFT computation. We propose a memory-efficient technique based on the novel use of customizable hardware components such as FPGA block memory in First-In-First-Out (FIFO) configuration, fill-rate based arbiter, distributed RAM and an array of pipelined single precision floating point multipliers and adders. the proposed architecture exhibits high performance over a wide range of configurations and data-sizes. A speed-up of over 9.6 was achieved when compared with existing FPGA-based technique at a 7 times higher MFLOPS per watt. Compared to GPU based technique, over 6 times higher MFLOPS per watts were achieved. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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An efficient and flexible host-FPGA PCIe communication library 24

An efficient and flexible host-FPGA PCIe communication libra...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Gong, Jian Wang, Tao Chen, Jiahua Wu, Haoyang Ye, Fan Lu, Songwu Cong, Jason Center for Energy-Efficient Computing and Applications School of EECS Peking University Beijing China UCLA Computer Science Department Los AngelesCA United States PKU-UCLA Joint Research Institute in Science and Engineering United States

ISBN: (纸本)9783000446450

A high-performance interconnection between a host processor and FPGA accelerators is in much demand. Among various interconnection methods, a PCIe bus is an attractive choice for loosely coupled accelerators. Because there is no standard host-FPGA communication library, FPGA developers have to write significant amounts of PCIe related code at both the FPGA side and the host processor side. A high-performance host-FPGA PCIe communication library holds the key to broadening the use of FPGA accelerators. In this paper we target efficiency and flexibility as two important features in such a library. We discuss the challenges in providing these features, and present our solution to these challenges. We propose EPEE, an efficient and flexible host-FPGA PCIe communication library and describe its design. We implemented EPEE in various generations of Xilinx FPGAs with up to 26.24 Gbps half-duplex and 43.02 Gbps full-duplex aggregate throughput in the PCIe Gen2 X8 mode;these are at the best utilization levels that a host-FPGA PCIe library can achieve. the EPEE library has been integrated into four different FPGA applications with different data usage patterns in various institutes. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Exploring architecture parameters for dual-output LUT based FPGAs 24

Exploring architecture parameters for dual-output LUT based ...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Jiang, Zhenghong Lin, Colin Yu Yang, Liqun Wang, Fei Yang, Haigang System on Programmable Chip Research Department Institute of Electronics Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9783000446450

Dual-output lookup tables (LUTs) are mainstream in the design of commercial FPGA products. A detailed exploration of architectural parameters of FPGAs based on dualoutput LUTs is presented. Different from traditional single-output LUT based architecture, 'shared inputs' between the sub-LUTs is a new parameter specific to dual-output architecture. In this paper, we focus on the effect of ratio of shared inputs on the performance and area-efficiency. First, we study the required cluster inputs and derive a relationship between cluster inputs, LUT size and cluster size under different ratios of shared inputs. Secondly, our evaluation results show that a FPGA with 4-LUTs and a shared input ratio of two thirds is preferred for area-efficiency, while a large LUT size of 9 with no shared inputs achieves best performance. Finally, we determine that a LUT size of 4, a cluster size from 3 to 8, and a shared input ratio between 1/3 and 2/3, provide the best area-delay product for dual-output LUT based FPGAs. © 2014 Technical University of Munich (TUM).

关键词： Table lookup

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Ultrasmall: the smallest MIPS soft processor 24

Ultrasmall: The smallest MIPS soft processor

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24th international conference on field programmable logic and applications, FPL 2014

作者： Nakatsuka, Hiroshi Tanaka, Yuichiro Chu, thiem Van Takamaeda-Yamazaki, Shinya Kise, Kenji Tokyo Institute of Technology Tokyo Japan Nara Institute of Science and Technology Nara Japan

ISBN: (纸本)9783000446450

Soft processors have been commonly used in FPGAbased designs to perform various useful functions. Some of these functions are not performance-critical and required to be implemented using very few FPGA resources. For such cases, it is desired to reduce circuit area of the soft processor as much as possible. this paper proposes Ultrasmall, a small soft processor for FPGAs. Ultrasmall supports a subset of the MIPS-I ISA and is designed for microcontrollers in FPGA-based SoCs. Ultrasmall employs an area efficient architecture to minimize the use of FPGA resources. While supporting the 32-bit ISA, Ultrasmall adopts the 2-bit wide serial ALU architecture. this approach significantly reduces the amount of FPGA resource usage. In addition to the device-independent optimizations for any FPGAs, we apply primitives-based optimizations for the Xilinx Spartan-3E FPGA series with 4-input LUTs, thereby further reducing the total number of occupied slices. the evaluation result shows that, on the Xilinx Spartan-3E XC3S500E FPGA, Ultrasmall occupies only 137 slices which is 84% of the number of occupied slices of Supersmall, a very small soft processor with the same design concept as Ultrasmall. On the other hand, in term of performance, Ultrasmall is 2.9× faster than Supersmall. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Hardware accelerated novel optical de novo assembly for large-scale genomes 24

Hardware accelerated novel optical de novo assembly for larg...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Meng, Pingfan Jacobsen, Matthew Kimura, Motoki Dergachev, Vladimir Anantharaman, thomas Requa, Michael Kastner, Ryan University of California 9500 Gilman Dr. San DiegoCA92093 United States BioNano Genomics 9640 Towne Centre Dr. #100 San DiegoCA92121 United States

ISBN: (纸本)9783000446450

De novo assembly is a widely used methodology in bioinformatics. However, the conventional short-read based de novo assembly is incapable of reliably reconstructing the large-scale structures of human genomes. Recently, a novel optical label based technology has enabled reliable large-scale de novo assembly. Despite its advantage in large-scale genome analysis, this new technology requires a more computationally intensive alignment algorithm than its conventional counterpart. For example, the run-time of reconstructing a human genome is on the order of 10;000 hours on a sequential CPU. therefore, in order to practically apply this new technology in genome research, accelerated approaches are desirable. In this paper, we present three different accelerated approaches, multi-core CPU, GPU and FPGA. Against the sequential software baseline, our multi-core CPU design achieved a 8.4× speedup while the GPU and FPGA designs achieved 13.6× and 115× speedups respectively. We also reveal the insights of the design space exploration of this new assembly algorithm on these three different devices by comparing the results. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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