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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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A fast and scalable FPGA damage diagnostic service for R3TOS using BIST cloning technique 24

A fast and scalable FPGA damage diagnostic service for R3TOS...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Ebrahim, Ali Arslan, Tughrul Iturbe, Xabier School of Engineering University of Edinburgh EH9 3JL United Kingdom Embedded System-on-Chip Group IKERLAN-IK4 Research Basque Country Spain

ISBN: (纸本)9783000446450

this paper presents a new technique to be used in the context of reconfigurable computing to accelerate the online diagnosis of permanent damage on Xilinx FPGAs using Built-In Self Tests (BISTs). Detecting and locating permanently damaged resources with precision is central to keep the system implemented on the FPGA flawless at all times;i.e. upcoming hardware tasks are mapped to available functional resources, circumventing the use of the damaged ones. the proposed diagnostic technique exploits the Multiple Frame Write (MFW) feature available in Xilinx FPGAs to 'clone' (i.e. replicate) a single basic BIST circuit along arbitrarily sized and shaped areas on the FPGA without incurring large time overheads. Hence, the proposed technique allows for creating at runtime on-demand tailored BIST circuits to satisfy any diagnosis requirements that may rise up. Moreover, the proposed solution allows for saving memory in the system as it only requires storing basic BIST circuits. Finally, the paper presents a diagnostic service for a Reliable Reconfigurable Real-Time Operating System (R3TOS) that is based on the BIST cloning technique and works in cooperation with the R3TOS fault-handling and recovery mechanisms. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Dataflow acceleration of Krylov subspace sparse banded problems 24

Dataflow acceleration of Krylov subspace sparse banded probl...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Burovskiy, Pavel Girdlestone, Stephen Davies, Craig Sherwin, Spencer Luk, Wayne Department of Computing Imperial College London United Kingdom Department of Aeronautics Imperial College London United Kingdom Maxeler Technologies United Kingdom

ISBN: (纸本)9783000446450

Most of the efforts in the FPGA community related to sparse linear algebra focus on increasing the degree of internal parallelism in matrix-vector multiply kernels. We propose a parametrisable dataflow architecture presenting an alternative and complementary approach to support acceleration of banded sparse linear algebra problems which benefit from building a Krylov subspace. We use banded structure of a matrix A to overlap the computations Ax, A2x,..., Akx by building a pipeline of matrix-vector multiplication processing elements (PEs) each performing Aix. Due to on-chip data locality, FLOPS rate sustainable by such pipeline scales linearly with k. Our approach enables trade-off between the number k of overlapped matrix power actions and the level of parallelism in a PE. We illustrate our approach for Google PageRank computation by power iteration for large banded single precision sparse matrices. Our design scales up to 32 sequential PEs with floating point accumulation and 80 PEs with fixed point accumulation on Stratix V D8 FPGA. With 80 single-pipe fixed point PEs clocked at 160Mhz, our design sustains 12.7 GFLOPS. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring 24

Trade-offs and progressive adoption of FPGA acceleration in ...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Kekely, Lukáš Pus, Viktor Benacek, Pavel Kořenek, Jan CESNET A. L. E. Zikova 4 Prague160 00 Czech Republic IT4Innovations Centre of Excellence Faculty of Information Technology Brno University of Technology Božetěchova 2 612 66 Czech Republic

ISBN: (纸本)9783000446450

Current hardware acceleration cores for network traffic processing are often well optimized for one particular task and therefore provide high level of hardware acceleration. But for many applications, such as network traffic monitoring and security, it is also necessary to achieve rapid development cycle to provide fast response to security *** propose and evaluate a new concept of hardware acceleration for flexible flow-based network traffic monitoring with support of application protocol analysis. the concept is called Software Defined Monitoring (SDM) and it relies on a configurable hardware accelerator implemented in FPGA, coupled with smart monitoring tasks running as software on general CPU. the monitoring tasks in the software control the level of detail and type of information retained during the hardware processing. this arrangement allows rapid application prototyping in the software, followed by further shifting of the timing critical parts of the processing to the hardware accelerator. the concept is proposed with the scalability in mind, therefore it is suitable for different FPGA based platforms ranging from embedded single-chip solutions (such as Zynq or CycloneV) to high-speed backbone network monitoring boxes. Our pilot high-speed implementation using FPGA acceleration board in a commodity server performs a 100Gb/s flow traffic measurement augmented by a selected application protocol analysis. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Caching memcached at reconfigurable network interface 24

Caching memcached at reconfigurable network interface

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24th international conference on field programmable logic and applications, FPL 2014

作者： Fukuda, Eric S. Inoue, Hiroaki Takenaka, Takashi Kim, Dahoo Sadahisa, Tsunaki Asai, Tetsuya Motomura, Masato Graduate School of Information Science and Technology Hokkaido University Sapporo Hokkaido060-0814 Japan NEC Corporation 1753 Shimonumabe Nakahara-ku Kawasaki Kanagawa211-8666 Japan

ISBN: (纸本)9783000446450

Memcached is a technology that improves response speed of web servers by caching data on DRAMs in distributed servers. In order to achieve higher performance, memcached has been evaluated on various platforms. Among them, FPGA seems to be the most efficient platform to run memcached, and several research groups are trying to achieve higher throughput with it. However, it is difficult to utilize a large amount of memory (several dozen gigabytes) with an FPGA. Some groups are trying to solve this problem by using an embedded CPU for memory allocation and another group is employing an SSD. Unlike other approaches that try to replace memcached itself on FPGAs, our approach augments the software memcached running on the host CPU by caching its data and some operations at the FPGA-equipped network interface card (NIC) mounted on the server. the locality of memcached data enables the FPGA NIC to have a fairly high hit rate with a smaller memory. We first explore the cache parameters by software simulations and estimate the effectiveness of our approach, and then prototype a system to prove its effectiveness. through our evaluation with YCSB, a standard key-value store (KVS) benchmarking tool, we estimate that the latency improved by an order of magnitude over software memcached running on a high performance CPU. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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High level programming framework for FPGAs in the data center 24

High level programming framework for FPGAs in the data cente...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Segal, Oren Margala, Martin Chalamalasetti, Sai Rahul Wright, Mitch Department of Electrical and Computer Engineering University of Massachusetts Lowell LowellMA United States Silicon Design Lab HP Servers HoustonTX United States

ISBN: (纸本)9783000446450

Heterogeneous computing offers a promising solution for energy efficient computing in the data center. FPGA based heterogeneous computing is an especially promising direction since it allows for the creation of custom hardware solutions for data centric parallel applications. One of the main issues delaying wide spread adoption of FPGAs as main stream high performance computing devices is the difficulty in programming them. OpenCL was meant to address the difficulties and the non-uniformity related to programming heterogeneous devices, unfortunately because of its complexity it sets the bar high for many software programmers, preventing them from directly benefiting from the computing power and energy efficiency that OpenCL and heterogeneous computing have to offer. this work presents an effort to bridge the gap by extending an existing Java programming framework (APARAPI), based on OpenCL, so that it can be used to program FPGAs at a high level of abstraction and increased ease of programmability. We run several real world algorithms to assess the performance of the APARAPI framework on both a low end and a high end system. On the low end and high and systems respectively we find up to 78-80 percent power reduction and 4.8X-5.3X speed increase running NBody simulation, as well as up to 65-80 percent power reduction and 6.2X-7X speed increase for a K-Means MapReduce algorithm running on top of the Hadoop framework and APARAPI (Abstract) © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Automated framework for FPGA-based parallel genetic algorithms 24

Automated framework for FPGA-based parallel genetic algorith...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Guo, Liucheng thomas, David B. Guo, Ce Luk, Wayne Dept. of EEE Imperial College London United Kingdom Dept. of Computing Imperial College London United Kingdom

ISBN: (纸本)9783000446450

Parallel genetic algorithms (pGAs) are a variant of genetic algorithms which can promise substantial gains in both efficiency of execution and quality of results. pGAs have attracted researchers to implement them in FPGAs, but the implementation always needs large human effort. To simplify the implementation process and make the hardware pGA designs accessible to potential non-expert users, this paper proposes a general-purpose framework, which takes in a high-level description of the optimisation target and automatically generates pGA designs for FPGAs. Our pGA system exploits the two levels of parallelism found in GA instances and genetic operations, allowing users to tailor the architecture for resource constraints at compile-time. the framework also enables users to tune a subset of parameters at run-time without time-consuming recompilation. Our pGA design is more flexible than previous ones, and has an average speedup of 26 times compared to the multi-core counterparts over five combinatorial and numerical optimisation problems. When compared with a GPU, it also shows a 6.8 times speedup over a combinatorial application. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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field programmable Gate Arrays Implementation of Dual Tree Complex Wavelet Transform

Field Programmable Gate Arrays Implementation of Dual Tree C...

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Annual international conference of the IEEE Engineering in Medicine and Biology Society

作者： Ferhat Canbay Vecdi Emre Levent Gorkem Serbes Sezer Goren Nizamettin Aydin the Computer Engineering Department Yildiz Technical University Istanbul Turkey the Department of Computer Science Ozyegin University Istanbul Turkey the Biomedical Engineering Department Yildiz Technical University Istanbul Turkey the Department of Computer Engineering Yeditepe University Istanbul Turkey

ISBN: (纸本)9781424492695

Due to the inherent time-varying characteristics of physiological systems, most biomedical signals (BSs) are expected to have non-stationary character. therefore, any appropriate analysis method for dealing with BSs should exhibit adjustable time-frequency (TF) resolution. the wavelet transform (WT) provides a TF representation of signals, which has good frequency resolution at low frequencies and good time resolution at high frequencies, resulting in an optimized TF resolution. Discrete wavelet transform (DWT), which is used in various medical signal processing applications such as denoising and feature extraction, is a fast and discretized algorithm for classical WT. However, the DWT has some very important drawbacks such as aliasing, lack of directionality, and shift-variance. To overcome these drawbacks, a new improved discrete transform named as Dual Tree Complex Wavelet Transform (DTCWT) can be used. Nowadays, with the improvements in embedded system technology, portable realtime medical devices are frequently used for rapid diagnosis in patients. In this study, in order to implement DTCWT algorithm in FPGAs, which can be used as real-time feature extraction or denoising operator for biomedical signals, a novel hardware architecture is proposed. In proposed architecture, DTCWT is implemented with only one adder and one multiplier. Additionally, considering the multi-channel outputs of biomedical data acquisition systems, this architecture is capable of running N channels in parallel.

关键词： TF WT FPGAs

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A Comparative Study on the Implementation of Reversible Binary Coded Decimal (BCD) Adder Performance on field programmable Gate Array (FPGA) 4

A Comparative Study on the Implementation of Reversible Bina...

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4th IEEE international conference on Control System Computing and Engineering (ICCSCE 2014)

作者： tham, Nyap Tet Clement Gopalai, Alpha Agape Gopal, Lenin Singh, Ashutosh K. Curtin Univ Sarawak Dept Elect & Comp Engn Miri Malaysia Monash Univ Malaysia Dept Mechatron Engn Bandar Sunway Selangor Malaysia NIT Urukshetra Dept Comp Applicat Kurukshetra Haryana India

ISBN: (纸本)9781479956869

In this paper, we present a performance comparison of Binary Coded Decimal (BCD) Adders on field programmable Gate logic (FPGA) for functional and behavioural verification. Although it does not prove that the circuit is reversible, implementation on FPGA serves as a platform for functional verification of circuits. BCD adders are one such circuit which has gain wide research emphasis where BCD adders can be implemented in a wide array of applications such as financial and commercial computations as most of the data stored and calculated are in decimal format. Hardware implementation of a BCD adder has been known to perform at least 100 times faster than its software counterparts. Current trends in reversible BCD adder consist of 4 major parts - 4-bit Adder, Correction and Detection Unit, and Modified 4-bit Adder. Designs were chosen based on overall design quantum cost, complexity, and estimated delays. the designs are then implemented on Altium Designer using Hardware Description Language(HDL) and verified on Xilinx Spartan 3AN and Altera Cyclone I FPGAs.

关键词： field programmable gate arrays reversible BCD Adder reversible logic delay Energy delay ratio EDR

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Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing 24

Cost-efficient FPGA layered LDPC decoder with serial AP-LLR ...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Boncalo, Oana Amaricai, Alexandru Hera, Andrei Savin, Valentin University Politehnica Timisoara Computer Engineering Department Timisoara Romania CEA-LETI MINATEC Campus Grenoble France

ISBN: (纸本)9783000446450

this paper proposes an FPGA based layered architecture for quasi-cyclic (QC) irregular LDPC decoder. Our approach is based on merging variable and check node processing into one single variable-check node (VCN) unit. Layer message computation is done using a parallel scheme of a number of VCNs equal to the expansion factor of the QC matrix. the proposed architecture is characterized by the serial processing of the a posteriori LLRs by an FPGA specific high frequency VCN unit implementation using ROM memories. In our approach data conversions as well as additions and comparators are replaced by look-up-tables implemented using distributed RAM. In addition to this, other techniques such as: efficient packaging of LLRs messages and check-node message compression as well as the configurable port width of the FPGA's BRAM are used to reduce BRAM block utilization. throughput increase is achieved by utilizing techniques such as pipelining, parallel processing of multiple VCNs, as well as relatively high working frequency. Implementation results for the WiMAX (1152, 2304) QC irregular LDPC code indicate that the proposed architecture has up to 3x less slices resource utilization and up to 1 order of magnitude less BRAM blocks with respect to other approaches, while maintaining a throughput of several hundreds of Mbps (800 Mbps coded bits). We achieved this without sacrificing flexibility;therefore we can easily adapt our design to accommodate different code rates. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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A highly-efficient and green data flow engine for solving Euler atmospheric equations 24

A highly-efficient and green data flow engine for solving Eu...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Gan, Lin Fu, Haohuan Yang, Chao Luk, Wayne Xue, Wei Mencer, Oskar Huang, Xiaomeng Yang, Guangwen Ministry of Education Key Laboratory for Earth System Modeling Center for Earth System Science Tsinghua University China Department of Computing Imperial College London United Kingdom China Institute of Software State Key Laboratory of Computer Science Chinese Academy of Sciences China Mexeler Technologies United Kingdom

ISBN: (纸本)9783000446450

Atmospheric modeling is an essential issue in the study of climate change. However, due to the complicated algorithmic and communication models, scientists and researchers are facing tough challenges in finding efficient solutions to solve the atmospheric equations. In this paper, we accelerate a solver for the three-dimensional Euler atmospheric equations through reconfigurable data flow engines. We first propose a hybrid design that achieves efficient resource allocation and data reuse. Furthermore, through algorithmic offsetting, fast memory table, and customizable-precision arithmetic, we map a complex Euler kernel into a single FPGA chip, which can perform 956 floating point operations per cycle. In a 1U-chassis, our CPU-DFE unit with 8 FPGA chips is 18.5 times faster and 8.3 times more power efficient than a multicore system based on two 12-core Intel E5-2697 (Ivy Bridge) CPUs, and is 6.2 times faster and 5.2 times more power efficient than a hybrid unit equipped with two 12-core Intel E5-2697 (Ivy Bridge) CPUs and three Intel Xeon Phi 5120d (MIC) cards. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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