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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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Asynchronously assisted FPGA for variability

Asynchronously assisted FPGA for variability

引用

international conference on field programmable logic and applications

作者： Hock S. Low Delong Shang Fei Xia Alex Yakovlev Systems Design Group Newcastle University Newcastle upon Tyne UK

the effect of variability has become increasingly significant as a result of technology geometry scaling. this paper describes Asynchronous Assisting logic (AAL) blocks and the method of introducing them into modern FPGA architecture, in order to increase tolerance of the wide range latency variations caused by parametric variation, and temperature and supply voltage fluctuations. the proposed method leverages the availability of variation maps and suggests deploying configurable AAL blocks only into the variation critical paths - reinforcing rather rerouting/remapping. this method reduces the size overhead significantly which normally will be incurred by fully asynchronous designs. the proposed technique maintains the existing FPGA architecture allowing potential reuse of design flow. Simulations show correct functionality given regularly variable, randomly variable and capacitor switching energy harvester voltage supplies.

关键词： field programmable gate arrays Switches Silicon Clocks logic gates

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A combination of multi-edge coding and independent coding lines for time-to-digital conversion

A combination of multi-edge coding and independent coding li...

引用

international conference on field programmable logic and applications

作者： Dominik Sondej Ryszard Szplet Military University of Technology Warsaw Poland

the paper describes a new method for time-to-digital conversion that allows achieving the conversion resolution far below the propagation time of the fastest delay buffer in integrated circuit (IC). the method is a combination of the multi-edge time coding and time digitization in independent coding lines. the implementation of such combination and assessment of its effectiveness are the main aims of this research. the article also describes the main design issues that were solved during the implementation of method in an FPGA device. they include: the generation of a pattern square signal with a certain amount of edges and possibly minimal delays between them, the elimination of bubble errors and reduction of internal interferences in IC.

关键词： Encoding field programmable gate arrays Delays Delay lines Signal resolution

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Multi-directional error correction schemes for SRAM-based FPGAs

Multi-directional error correction schemes for SRAM-based FP...

引用

international conference on field programmable logic and applications

作者： Shyamsundar Venkataraman Rui Santos Sidharth Maheshwari Akash Kumar Department of Electrical & Computer Engineering National University of Singapore

Readback scrubbing is considered as an effective mechanism to correct errors in Static-RAM (SRAM)-based field programmable Gate Arrays (FPGAs). However, current solutions have a low error correction percentage per unit area overhead. this paper proposes two new error detection/correction mechanisms that combine frame readback scrubbing with error correction codes (ECCs) that are applied in multiple directions, to achieve a high error correction percentage per unit area overhead. Experiments conducted show that the proposed schemes have an excellent error correction percentage (over 99%), especially for multi-bit upsets, while using up to 59.37% lesser area overhead compared with other state-of-the-art.

关键词： field programmable gate arrays Error correction Error correction codes Computer architecture Hardware Circuit faults Equations

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Ready PCIe data streaming solutions for FPGAs

Ready PCIe data streaming solutions for FPGAs

引用

international conference on field programmable logic and applications

作者： thomas B. Preußer Rainer G. Spallek Technische Universitat Dresden Dresden Sachsen DE Technische Universität Dresden Germany

the PCIe attachment of FPGA accelerators within host workstations is convenient and offers a high-performance direct integration. FPGA-boards designed and equipped as PCIe extension cards are available off-the-shelf. this paper gives an overview on options to provide data streaming abstractions in user applications using PCIe technology. RIFFA and Xillybus are straightforward implementations, which aim at providing ready solutions at this level. this paper will describe these platforms and evaluate them in terms of their ease of use, their perceived maturity and the performance metrics bandwidth and latency. It concludes with providing a brief guideline on how to select the proper platform depending on the usage context.

关键词： field programmable gate arrays throughput Bandwidth Libraries Linux Standards Performance evaluation

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RAM-based hardware accelerator for network data anonymization

RAM-based hardware accelerator for network data anonymizatio...

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international conference on field programmable logic and applications

作者： Fumito Yamaguchi Kanae Matsui Hiroaki Nishi Graduate School of Science and Technology Keio University Yokohama Japan

Many network services including intrusion detection and recommendation provide their services by analyzing information acquired from network transactions. A careful analysis of these data can reveal valuable information when deep packet inspection is performed. Since these packet analyses generate sensitive information from enormous volumes of transmitted data, the requirement for data anonymization has been discussed. there have been many studies of anonymization techniques and their implementation in software applications. However, limited research has been undertaken regarding hardware-based anonymizers. this paper proposes and evaluates a RAM-based anonymization architecture that maintains both high throughput and a low information-loss ratio.

关键词： Hardware Random access memory throughput Software field programmable gate arrays Table lookup

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Methods for implementation of feedback loops in high speed FPGA applications

Methods for implementation of feedback loops in high speed F...

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international conference on field programmable logic and applications

作者： Nima Safari Volker Mauer Shahin Gheitanchi Wireless SSE Altera Corporation High Wycombe UK

In many Digital Signal Processing (DSP) modules, increasing the number of pipelining stages to achieve higher throughput may break the module functionality if a feedback-loop exists in the algorithm. this paper addresses a novel algorithmic-level technique to modify implementation of feedback loops to allow deeper pipelining while sustaining the module functionality. An equivalent model for a first-order Infinite Impulse Response (IIR) filter can be obtained by a cascade model including a higher order repeated-pole IIR filter followed by a Finite Impulse Response (FIR) filter. the order of the repeated-pole IIR filters, and hence the number of pipelining stages can be chosen to meet the Fmax requirements. the model is further developed to include a class of mathematical recursive functions to cover many different DSP applications.

关键词： IIR filters Pipeline processing Feedback loop Digital signal processing Registers Finite impulse response filters field programmable gate arrays

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Area implications of memory partitioning for high-level synthesis on FPGAs

Area implications of memory partitioning for high-level synt...

引用

international conference on field programmable logic and applications

作者： Luca Gallo Alessandro Cilardo David thomas Samuel Bayliss George A. Constantinides University of Naples Federico II Napoli Imperial College London London U.K

FPGAs normally have numerous independent memory banks that can be accessed simultaneously, potentially offering a very large memory bandwidth. Adopting a suitable application-based memory partitioning strategy is thus vital to take full advantage of the memory architecture. In addition to improving the potential memory bandwidth, partitioning also affects the area complexity of the generated system because the required steering logic depends on the partitioning scheme. this work describes the area implications of a lattice-based memory partitioning technique in the context of high-level synthesis for FPGAs. Experimental results with a commercial HLS tool show that the proposed partitioning technique improves area efficiency compared to alternative approaches.

关键词： Lattices Switches Memory management field programmable gate arrays Table lookup Schedules Parallel processing

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Fast and accurate SEU-tolerance characterization method for Zynq SoCs

Fast and accurate SEU-tolerance characterization method for ...

引用

international conference on field programmable logic and applications

作者： Igor Villata Unai Bidarte Uli Kretzschmar Armando Astarloa Jesús Lázaro Department of Electronics and Telecommunications University of the Basque Country UPV/EHU Bilbao Spain

In this paper a new SEU (Single Event Upset) emulation method for testing fault tolerant systems in FPGAs is presented. It is implemented on a “Xilinx Zynq ® -7000 All programmable System on Chip (SoC)” device, which combines a hard microprocessor with programmable logic. An important new feature is that an internal hardware configuration interface controlled by this microprocessor is provided. this interface is used for injecting faults into the configuration bitstream in order to emulate radiation effects. Since both the processing system and the programmable logic are in the same chip, this method has the high speed characteristics of internal fault injection methods. As a hard internal configuration interface is provided, a configuration bit belonging to the internal interface port cannot be flipped and injection side effects are avoided. this method is especially suitable for testing complex real fault-tolerant FPGA designs because no substantial modifications need to be added to the original design. A universal verification system is proposed to avoid designing complex external application-dependent testbenches.

关键词： field programmable gate arrays Emulation Fault tolerant systems Circuit faults Process control System-on-chip Testing

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Interconnect for commodity FPGA clusters: Standardized or customized?

Interconnect for commodity FPGA clusters: Standardized or cu...

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international conference on field programmable logic and applications

作者： A. theodore Markettos Paul J. Fox Simon W. Moore Andrew W. Moore Computer Laboratory University of Cambridge UK

We demonstrate that a small library of customizable interconnect components permits low-area, high-performance, reliable communication tuned to an application, by analogy with the way designers customize their compute. Whilst soft cores for standard protocols (Ethernet, RapidIO, Infiniband, Interlaken) are a boon for FPGA-to-other-system interconnect, we argue that they are inefficient and unnecessary for FPGA-to-FPGA interconnect. Using the example of BlueLink, our lightweight pluggable interconnect library, we describe how to construct reliable FPGA clusters from hundreds of lower-cost commodity FPGA boards. Utilizing the increasing number of serial links on FPGAs demands efficient use of soft-logic, making domain-optimized custom interconnect attractive for some time to come.

关键词： field programmable gate arrays Reliability Protocols Transceivers Standards Cyclones Hardware

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Robust and flexible FPGA-based digital PUF

Robust and flexible FPGA-based digital PUF

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international conference on field programmable logic and applications

作者： Teng Xu Miodrag Potkonjak Computer Science Department University of California Los Angeles

We have developed the first FPGA-based digital physical unclonable function (PUF) by leveraging the reconfigurability of an FPGA and introducing a new way of using the standard analog delay PUF. the key observation is that for any analog delay PUF, there is a subset of challenge inputs for which the PUF output is stable regardless of operation and environmental conditions. We use only such stable inputs to initialize the look-up tables (LUTs) that are configured in such a way that the digital PUF is formed. We demonstrate the effectiveness of the new security primitive using extensive simulation and experimental results. For example, we show that the new PUF is resistant against a wide spectrum of security attacks and its output stream passes all the NIST randomness tests.

关键词： Delays Table lookup Security field programmable gate arrays thermal stability Temperature distribution Hardware

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