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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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A mixed integer linear programming approach for design space exploration in FPGA-based MPSoC

A mixed integer linear programming approach for design space...

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international conference on field programmable logic and applications

作者： Bouthaina Dammak Rachid Benmansour Smail Niar Mouna Baklouti Mohamed Abid LAMIH University of Valenciennes Valenciennes France National School of Engineers of Sfax Sfax Tunisia

Heterogeneous Multiprocessor System-on-Chip (Ht-MPSoC) architectures represent a promising approach as they allow a higher performance/energy consumption trade-off. In such systems, the processor instruction set is enhanced by application-specific custom instructions implemented on reconfigurable fabrics, namely FPGA. To increase area utilization and guarantee application constraint respect, we propose a new architecture where Ht-MPSoC hardware accelerators are shared among different processors in an intelligent manner. In this paper, a Mixed Integer Linear Programming (MILP) model is proposed to systematically explore the complex design space of the different configurations.

关键词： Hardware Computer architecture Space exploration Acceleration Mixed integer linear programming field programmable gate arrays Linear accelerators

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Leakage and performance aware resource management for 2D dynamically reconfigurable FPGA architectures

Leakage and performance aware resource management for 2D dyn...

引用

international conference on field programmable logic and applications

作者： Siqi Wang Nam Khanh Pham Amit Kumar Singh Akash Kumar Department of Electrical and Computer Engineering National University of Singapore Singapore

the variety of applications for field programmable gate arrays (FPGAs) is continuously growing, thus it is important to address power consumption issues during the operation. As technological node shrinks, leakage power becomes increasingly critical in overall power consumption of FPGA. the technique of configuration pre-fetching (loads configurations as soon as possible) adopted to achieve high performance is one of the major reasons of leakage waste since regions containing reconfiguration information cannot be powered down in between the time gap of reconfiguration and execution. In this work, we present a heuristic approach to minimize the leakage power consumption for two-dimensional reconfigurable FPGA architectures. the heuristic scheduler is based on list scheduling and exploits dynamic priority for sorting the tasks into schedule order and a cost function for cell allocation. Farthest placement scheme is adopted for anti-fragmentation purpose. the cost function provides control to compromise between leakage dissipation and schedule length.

关键词： field programmable gate arrays Schedules Power demand Transistors Power dissipation Computer architecture logic gates

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Trends of CPU, GPU and FPGA for high-performance computing

Trends of CPU, GPU and FPGA for high-performance computing

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international conference on field programmable logic and applications

作者： Mário Véstias Horácio Neto INESC-ID/ISEL/IPL Lisbon Portugal INESC-ID Universidade de Lisboa Portugal

Floating-point computing with more than one TFLOP of peak performance is already a reality in recent field-programmable Gate Arrays (FPGA). General-Purpose Graphics Processing Units (GPGPU) and recent many-core CPUs have also taken advantage of the recent technological innovations in integrated circuit (IC) design and had also dramatically improved their peak performances. In this paper, we compare the trends of these computing architectures for high-performance computing and survey these platforms in the execution of algorithms belonging to different scientific application domains. Trends in peak performance, power consumption and sustained performances, for particular applications, show that FPGAs are increasing the gap to GPUs and many-core CPUs moving them away from high-performance computing with intensive floating-point calculations. FPGAs become competitive for custom floating-point or fixed-point representations, for smaller input sizes of certain algorithms, for combinational logic problems and parallel map-reduce problems.

关键词： field programmable gate arrays Graphics processing units Performance evaluation Market research Table lookup Monte Carlo methods

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FPGA acceleration of SAT/Max-SAT solving using variable-way cache

FPGA acceleration of SAT/Max-SAT solving using variable-way ...

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international conference on field programmable logic and applications

作者： Kenji Kanazawa Tsutomu Maruyama University of Tsukuba Tsukuba Ibaraki Japan

WalkSAT (WSAT) is a stochastic local search algorithms for Boolean Satisfiability (SAT) and Maximum Boolean Satisfiability (MaxSAT) problems, and it is very suitable for hardware acceleration because of its high inherent parallelism. Formal verification is one of the most important applications of SAT and MaxSAT, however, the size of the formal verification problems is significantly larger than on-chip memory size, and most of the data have to be placed in off-chip DRAM. In this paper, we propose a method to hide the access delay by using on-chip memory banks as a variable-way associative cache memory. the size of data blocks that are frequently fetched from the DRAM considerably varies in the WSAT algorithm. this cache memory aims to hold whole block when it is small enough, and only the head portion when it is large, to hide the DRAM access delay. With this cache memory, up to 60% DRAM access delay can be hidden, and the performance can be improved up to 26%.

关键词： Random access memory Delays Cache memory field programmable gate arrays Parallel processing logic gates Clocks

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New approaches for in-system debug of behaviorally-synthesized FPGA circuits

New approaches for in-system debug of behaviorally-synthesiz...

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international conference on field programmable logic and applications

作者： Joshua S. Monson Brad Hutchings Brigham Young University Provo UT US

this paper present new approaches for in-system, trace-based debug of High-Level Synthesis-generated hardware. these approaches include the use of Event Observability Ports (EOP) that provide observability of source-level events in the final hardware. We also propose the use of small, independent trace buffers called Event Observability Buffers (EOB) for tracing events through EOPs. EOBs include a data storage enable signal that allows cycle-by-cycle storage decisions to be made on an EOB-by-EOB basis. this approach causes the timing relationships of events captured in different trace buffers to be lost. Two methods are presented for recovering these relationships. Finally, we present a case study that demonstrates the feasibility and effectiveness of an EOB trace strategy.

关键词： Instruments Hardware Clocks Debugging Software Table lookup field programmable gate arrays

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Hardware conversion of neural networks simulation models for neural processing accelerator implemented as FPGA-based SoC

Hardware conversion of neural networks simulation models for...

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international conference on field programmable logic and applications

作者： Marcin Pietras Computer Science and Information Technology West Pomeranian University of Technology ZUT Szczecin Poland

the transition from a neural network simulation model to its hardware representation is a complex process, which touches computations precision, performance and effective architecture implementation issues. Presented neural processing accelerator involves neural network sectioning, precision reduction and weight coefficients parsing (arrangements) in order to increase efficiency and maximize FPGA hardware resources utilization. Particular attention has been devoted on to ANN conversion methods designed for a system based on neural processing units and related with this process redundant calculations and empty neurons generation. In addition, this paper describes the FPGA-based Neural Processing Accelerator architecture benchmark for real example implementation of a pattern recognition neural network.

关键词： Biological neural networks Neurons Hardware Computational modeling Artificial neural networks field programmable gate arrays Computer architecture

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Experimental multi-FPGA GNSS receiver platform

Experimental multi-FPGA GNSS receiver platform

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international conference on field programmable logic and applications

作者： Fabio Garzia Alexander Rügamer Robert Koch Philipp Neumaier Ekaterina Serezhkina Matthias Overbeck Günther Rohmer Ekaterina Serezhkina Fraunhofer IIS Nuremberg Germany Fraunhofer IIS Nuremberg Germany

this paper describes the system architecture and implementation results of a robust and flexible dual-frequency 2×2 array processing GNSS receiver platform. A digital front-end FPGA pre-processes the incoming raw ADC data and implements interference mitigation methods in time and frequency domain. An optional second FPGA card can be used to realize more sophisticated and computational complex interference mitigation techniques. Finally, the data stream is processed on a baseband FPGA platform with spatial array processing techniques using a software assisted hardware GNSS receiver approach. the interconnection of the FPGAs is realized using gigabit transceivers handling a constant raw data rate of 16.8 Gbit/s.

关键词： Global Positioning System Receivers field programmable gate arrays Baseband Interference Correlators Hardware

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Accurate power control and monitoring in ZYNQ boards

Accurate power control and monitoring in ZYNQ boards

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international conference on field programmable logic and applications

作者： Arash Farhadi Beldachi Jose L. Nunez-Yanez Department of Electronic Engineering University of Bristol Bristol UK

ZYNQ devices combine a dual-core ARM Cortex A9 processor and a FPGA fabric in the same die and in different power domains. In this paper we investigate the run-time power scaling capabilities of these devices using of-the-shelf boards and proposed accurate and fine-grained power control and monitoring techniques. the experimental results show that both software and hardware methods are possible and the right selection can yield different results in terms of control and monitoring speeds, accuracy of measurement, power consumption, and area overhead. the results also demonstrate that significant power margins are available in the FPGA device with different voltage configurations possible. this can be used to complement traditional voltage scaling techniques applied to the processor domain to obtain hybrid energy proportional computing platforms.

关键词： Monitoring field programmable gate arrays Voltage control IP networks Software Process control Hardware

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Application specific multi-port memory customization in FPGAs

Application specific multi-port memory customization in FPGA...

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international conference on field programmable logic and applications

作者： Gorker Alp Malazgirt Hasan Erdem Yantir Arda Yurdakul Smail Niar Computer Engineering Bogazici University Bebek Istanbul LAMIH University of Valenciennes Valenciennes France

FPGA block RAMs (BRAMs) offer speed advantages compared to LUT-based memory designs but a BRAM has only one read and one write port. Designers need to use multiple BRAMs in order to create multi-port memory structures which are more difficult than designing with LUT-based multiport memories. Multi-port memory designs increase overall performance but comes with area cost. In this paper, we present a fully automated methodology that tailors our multi-port memory from a given application. We present our performance improvements and area tradeoffs on state-of-the-art string matching algorithms.

关键词： Parallel processing field programmable gate arrays Random access memory Program processors Pattern matching Registers Ports (Computers)

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Particle filtering-based Maximum Likelihood Estimation for financial parameter estimation

Particle filtering-based Maximum Likelihood Estimation for f...

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international conference on field programmable logic and applications

作者： Jinzhe Yang Binghuan Lin Wayne Luk Terence Nahar Imperial College SWIP London & Edinburgh UK Techila Technologies Ltd Tampere University of Technology Tampere Finland Imperial College London UK SWIP London UK

this paper presents a novel method for estimating parameters of financial models with jump diffusions. It is a Particle Filter based Maximum Likelihood Estimation process, which uses particle streams to enable efficient evaluation of constraints and weights. We also provide a CPU-FPGA collaborative design for parameter estimation of Stochastic Volatility with Correlated and Contemporaneous Jumps model as a case study. the result is evaluated by comparing with a CPU and a cloud computing platform. We show 14 times speed up for the FPGA design compared with the CPU, and similar speedup but better convergence compared with an alternative parallelisation scheme using Techila Middleware on a multi-CPU environment.

关键词： field programmable gate arrays Maximum likelihood estimation Kernel Computational modeling Parameter estimation Bandwidth

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