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Incremental distributed trigger insertion for efficient FPGA debug

Incremental distributed trigger insertion for efficient FPGA...

引用

international conference on field programmable logic and applications

作者： Fatemeh Eslami Steven J.E. Wilton The University of British Columbia Faculty of Medicine Vancouver BC CA

FPGA-based prototyping enables evaluating complex designs directly in hardware, at speeds orders of magnitude faster than simulation. However, this approach suffers from the lack of observability during debugging. To enhance observability, designers insert debug instrumentation; trace buffers are used to record a small subset of data. Since these buffers have limited capacity, trigger circuits are required to start and/or stop recording based on the values of selected signals in the circuit. Although it is possible to insert trigger circuits at compile time, changing the trigger behaviour requires re-compiling the design, increasing the cost of each debug iteration. In this paper, we propose inserting trigger circuits at run-time by distributing trigger logic over spare resources of a fully placed-and-routed design such that its mapping is completely preserved. We also propose CAD optimizations which improve routability of the trigger circuitry, and minimize the impact on circuit delay. We find that using our techniques to implement the trigger logic can be an order of magnitude faster than a full recompilation.

关键词： Routing field programmable gate arrays Delays Benchmark testing Trigger circuits Design automation Random access memory

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An FPGA-optimized architecture of horn and schunck optical flow algorithm for real-time applications

An FPGA-optimized architecture of horn and schunck optical f...

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international conference on field programmable logic and applications

作者： Michael Kunz Alexander Ostrowski Peter Zipf Digital Technology Group University of Kassel Kassel Germany

Optical flow estimation of image sequences is one of the key elements for motion detection. However, processing the optical flow in real-time is still an open task due to its computationally expensive nature. In this paper we present an FPGA-optimized architecture for optical flow estimation based on the algorithm of Horn and Schunck. While existing FPGA-realizations are only partly real-time capable, on a Stratix IV our architecture enables the computation of the optical flow for each pixel of a frame with 640 × 512 pixels at a framerate of 30 fps in iterative and up to 4k resolution (4,096 × 2,304 pixels) at a framerate of 20 fps in full-pipelined form.

关键词： Optical imaging Hardware Computer architecture Kernel Integrated optics Real-time systems Vectors

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A survey of open source processors for FPGAs

A survey of open source processors for FPGAs

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international conference on field programmable logic and applications

作者： Rui Jia Colin Yu Lin Zhenhong Guo Rui Chen Fei Wang Tongqiang Gao Haigang Yang University of Chinese Academy of Sciences Beijing China System on Programmable Chip Research Department Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781479933624

FPGA-based SoCs have been gaining great favors among traditional applications and expanding the application domains to some new areas. Reusing and sharing components is an attractive and pratical methodology for system designers to reduce the design complexity of the SoC architectures. Open source hardware has become an effective method of improving the design productivity. As the core functional component, processors affects the performance of SoC systems. this paper investigates existing open source processors, and gives an overview. From the points of usability and stability, the main features of open source processors are summarized. Following these features, some open source processors with high usability and stability are selected. these open source processors and existing vendor-provided soft processors are implemented on Stratix V and Virtex-7 FPGAs using corresponding EDA tools, Quart us n and ISE. the implementation results are compared and discussed.

关键词： field programmable gate arrays Java Registers Licenses Multicore processing Reduced instruction set computing

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A bit-interleaved embedded hamming scheme to correct single-bit and multi-bit upsets for SRAM-based FPGAs

A bit-interleaved embedded hamming scheme to correct single-...

引用

international conference on field programmable logic and applications

作者： Shyamsundar Venkataraman Rui Santos Anup Das Akash Kumar Department of Electrical and Computer Engineering National University of Singapore

Single Event Upsets (SEUs) inadvertently change the configuration bits of Static-RAM (SRAM)-based field programmable Gate Arrays (FPGAs), leading to erroneous output until the error has been corrected. Scrubbing using an Error Correction Code (ECC) such as hamming is a popular method to correct such faults. However, current works either require a large external memory to store the ECCs or can at most correct only one error in a frame. this paper proposes a novel bit-interleaved embedded hamming scheme along with scrubbing, to correct single (SBUs) and multi-bit upsets (MBUs) in SRAM-based FPGAs. this scheme does not require an external memory to store the ECCs, as they are embedded within the configuration memory itself. Experiments conducted on various benchmarks show that the proposed scheme can handle multiple errors per frame very well, with an embedding efficiency of over 99.3%.

关键词： field programmable gate arrays Memory management Benchmark testing Error correction Error correction codes Random access memory Runtime

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An FPGA sliding window-based architecture harris corner detector

An FPGA sliding window-based architecture harris corner dete...

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international conference on field programmable logic and applications

作者： Alexandru Amaricai Constantina-Elena Gavriliu Oana Boncalo Computer Engineering Department University Politehnica Timisoara Timisoara Romania

this paper proposes a FPGA implementation based on sliding processing window for Harris corner algorithm. It represents one of the most frequently used pre-processing method, for a wide variety of image processing algorithms, such as feature detection, motion tracking, image registration, etc.. It relies on a series of sequential steps, each processing an image outputted by the previous step. the purpose of the sliding window is to avoid storing intermediate results of processing stages in the external FPGA memory or to avoid utilize large line buffers typically implemented with BRAM blocks. therefore, the entire processing pipeline benefits from data locality. Implementation results for Virtex5 and Spartan-6 devices show that the proposed solution has very good performance (more than 130 fps for 1280×720 images in Xilinx Spartan-6) with significant less BRAM usage with respect to other approaches.

关键词： Computer architecture field programmable gate arrays Smoothing methods Buffer storage Pipelines Clocks Image processing

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Educating hardware design — From primary school children to postgraduate engineers

Educating hardware design — From primary school children to...

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international conference on field programmable logic and applications

作者： Oliver Knodel Martin Zabel Patrick Lehmann Rainer G. Spallek Department of Computer Science Technische Universitat Dresden Germany

the future of hardware development lies in massively parallel hardware architectures as used in embedded as well as high-performance systems, for instance streaming-based, real-time and database applications. Especially field-programmable gate arrays provide a platform for the rapid development of integrated circuits and the accompanied software. For reasons of energy efficiency, it is increasingly important to tailor hardware directly to the application. As such systems are very complex, the training of engineers has to start early. Furthermore, the usual curricula in computer science and electrical engineering teach only basic skills. Our approach does not start with specialized courses in master or diploma programs, but already with the motivation of primary school children for technical disciplines. Girls and boys are addressed equally. In school, children are made familiar with programmable circuits and thus motivated to study computer science with a specialization in computer engineering. In this paper we present our lectures and practical courses for bachelor and master students. With examples from final bachelor and master projects we demonstrate the quality of our education and its integration into current research.

关键词： Hardware Educational institutions Computer architecture Computers field programmable gate arrays Computer science

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Aging effects in FPGAs: an experimental analysis

Aging effects in FPGAs: an experimental analysis

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international conference on field programmable logic and applications

作者： Abdulazim Amouri Florent Bruguier Saman Kiamehr Pascal Benoit Lionel Torres Mehdi Tahoori Institute of Computer Engineering Karlsruhe Institute of Technology (KIT) Karlsruhe Germany LIRMM CNRS - University of Montpellier 2 Montpellier France

Modern field programmable Gate Arrays (FPGAs) are built using the most advanced technology nodes to meet performance and power demands. this makes them susceptible to various reliability challenges at nano-scale, and in particular to transistor aging. In this paper, an experimental analysis is made to identify the main parameters and phenomena influencing the performance degradation of FPGAs. For that purpose, a set of controlled ring-oscillator-based sensors with different frequencies and tunable activity control are implemented on a Spartan-6 FPGA. thus, the internal switching activities (SAs) and signal probabilities (SPs) of the sensors can be varied. We performed accelerated-lifetime conditions using elevated temperatures and voltages in a controlled setting to stress the FPGA. A novel monitoring method based on measuring the electromagnetic emissions of the FPGA is used to accurately monitor the performance of the sensors before and after the stress. the experiments reveal the extent of performance degradations, the impact of SPs and SAs, and the relative impacts of BTI and HCI aging factors.

关键词： field programmable gate arrays Aging Stress Degradation Transistors Temperature sensors

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Pipelined compressor tree optimization using integer linear programming

Pipelined compressor tree optimization using integer linear ...

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international conference on field programmable logic and applications

作者： Martin Kumm Peter Zipf University of Kassel Germany Digital Technology Group

Compressor trees offer an effective realization of the multiple input addition needed by many arithmetic operations. However, mapping the commonly used carry save adders (CSA) of classical compressor trees to FPGAs suffers from a poor resource utilization. this can be enhanced by using generalized performance counters (GPCs). Prior work has shown that high efficient GPCs can be constructed by exploiting the low-level structure of the FPGA. However, due to their irregular shape, the selection of those is not straight forward. Furthermore, the compressor tree has to be pipelined to achieve the potential FPGA performance. then, a selection between registered GPCs or flip-flops has to be done to balance the pipeline. this work defines the pipelined compressor tree synthesis as an optimization problem and proposes a (resource) optimal method using integer linear programming (ILP). Besides that, two new GPC mappings with high efficiency are proposed for Xilinx FPGAs.

关键词： Adders field programmable gate arrays Radiation detectors Delays Pipeline processing Table lookup Optimization

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FPGA acceleration of short read mapping based on sort and parallel comparison

FPGA acceleration of short read mapping based on sort and pa...

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international conference on field programmable logic and applications

作者： Youkou Sogabe Tsutomu Maruyama Systems and Information Engineering University of Tsukuba Tsukuba Ibaraki JAPAN Tsukuba Daigaku Tsukuba Ibaraki JP

Short read mapping is a process to align the short reads, which are fixed-length fragments of the target genome, to a given reference genome to identify the mutations in the target genome. Because of the rapid development of Next Generation Sequencing (NGS) technologies, faster short read mapping is required. In this paper, we propose an FPGA system for the short read mapping based on sort and parallel comparison of seeds. Seeds are fixed-length sub-strings in the short reads used to map the short read to the reference genome efficiently. In our system, (1) seeds are sorted using bucket sort, and the seeds in a bucket are compared in parallel with the candidate locations on the reference genome, (2) in this comparison, one nucleotide substitution, insertion, and deletion are allowed to achieve higher mapping rate, and (3) two stage search by reconfiguration is used to achieve higher performance. the mapping rate and search time by this approach outperforms existing systems.

关键词： Bioinformatics Genomics Indexes field programmable gate arrays Random access memory Acceleration Hardware

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Efficient implementation of a single-precision floating-point arithmetic unit on FPGA

Efficient implementation of a single-precision floating-poin...

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international conference on field programmable logic and applications

作者： Wilson José Ana Rita Silva Horácio Neto Mário Véstias INESC-ID Universidade de Lisboa Portuzal INESC-ID Instituto Superior de Engenharia de Lisboa IPL Portugal

this paper presents a single precision floating point arithmetic unit with support for multiplication, addition, fused multiply-add, reciprocal, square-root and inverse square-root with high-performance and low resource usage. the design uses a piecewise 2 nd order polynomial approximation to implement reciprocal, square-root and inverse square-root. the unit can be configured with any number of operations and is capable to calculate any function with a throughput of one operation per cycle. the floating-point multiplier of the unit is also used to implement the polynomial approximation and the fused multiply-add operation. We have compared our implementation with other state-of-the-art proposals, including the Xilinx Core-Gen operators, and conclude that the approach has a high relative performance/area efficiency.

关键词： Digital signal processing field programmable gate arrays Polynomials Adders Function approximation Table lookup

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