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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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A secure and unclonable embedded system using instruction-level PUF authentication

A secure and unclonable embedded system using instruction-le...

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international conference on field programmable logic and applications

作者： Jason X. Zheng Dongfang Li Miodrag Potkonjak Computer Science Department University of California Los Angeles USA School of Optical and Electronic Information Huazhong University of Science and Technology Wuhan China

In this paper we present a secure and unclonable embedded system design that can target either an FPGA or an ASIC technology. the premise of the security is that the executed machine code and the executing environment (the embedded processor) will authenticate each other at a per-instruction basis using Physical Unclonable Functions (PUFs) that are built into the processor. the PUFs ensure that the execution of the binary code may only proceed if the binary is compiled with the correct intrinsic knowledge of the PUFs, and that such intrinsic knowledge is virtually unique to each processor and therefore unclonable. We will explain how to implement and integrate the PUFs into the processor's execution environment such that each instruction is authenticated and de-obfuscated on-demand and how to transform an ordinary binary executable into PUF-aware, obfuscated binaries. We will also present a prototype system on a Xilinx Spartan6-based FPGA board.

关键词： field programmable gate arrays Security Delays Benchmark testing Embedded systems

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Bandwidth compression of multiple numerical data streams for high performance custom computing

Bandwidth compression of multiple numerical data streams for...

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international conference on Application Specific Systems (ASAP), Architectures and Processors

作者： Tomohiro Ueno Ryo Ito Kentaro Sano Satoru Yamamoto Graduate School of Information Sciences Tohoku University Sendai Japan

Bandwidth compression improves the performance of stream computing by enhancing an effective bandwidth. To apply the bandwidth compression to numerical applications such as numerical simulations, a compressor has to handle multiple data streams. In this paper, we describe a design of an FPGA-based bandwidth compressor for high performance stream computation. For synchronization of original data in multiple compressed streams with different bit-rate, we propose a data block transmission scheduler and explore a design space to reduce the size of their barrel shifters.

关键词： Bandwidth Hardware field programmable gate arrays Registers Educational institutions Indium tin oxide Space exploration

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Run-time power gating in hybrid ARM-FPGA devices

Run-time power gating in hybrid ARM-FPGA devices

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international conference on field programmable logic and applications

作者： Mohammad Hosseinabady Jose Luis Nunez-Yanez Department of Electrical and Electronic Engineering University of Bristol UK

Energy proportional computing (EPC) enables the allocation of energy to tasks depending on computational demands. Computing at full speed and then dynamically turning off modules when they are not required for a period of time can be used to obtain EPC and it is an alternative to voltage scaling techniques in which the computation is slowed down. this paper investigates the viability of physical power gating FPGA devices that incorporate a hardened processor in a different power domain. the run-time power gating approach is applied to Xilinx ZYNQ devices that incorporate a hardened Cortex A9 multi-processor. the paper demonstrates that power down followed by a full reconfiguration can be controlled by the embedded processor autonomously. the results show that the minimum time that the FPGA fabric must remain in power-off state for the technique to be energy efficient is in the order of milliseconds and up to 96% power reduction occurs when the fabric voltage is lowered below critical level. these results take into account the overheads of controlling the programmable voltage regulators interfaced to the FPGA and the overhead of the reconfiguration needed when the device must be returned to the active state.

关键词： field programmable gate arrays Power demand Turning Transistors Switching circuits Software Clocks

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the LEAP FPGA operating system

The LEAP FPGA operating system

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international conference on field programmable logic and applications

作者： Kermin Fleming Hsin-Jung Yang Michael Adler Joel Emer VSSAD Group Intel Corporation Computer Science and A.I. Laboratory Massachusetts Institute of Technology

FPGAs offer attractive power and performance for many applications, especially relative to traditional sequential architectures. In spite of these advantages, FPGAs have been deployed in only a few, niche *** argue that the difficulty of programming FPGAs all but precludes their use in more general systems: FPGA programmers are currently exposed to all the gory system details that software operating systems long ago abstracted away. In this work, we present the Latency-insensitive Environment for Application Programming (LEAP), an FPGA operating system built around latency-insensitive communications channels. LEAP alleviates the FPGA programming problem by providing a rich set of portable latency-insensitive abstraction layers for program development. Unlike software operating systems services, which are generally dynamic, the nature of FPGAs requires that many configuration decisions be made at compile time. We present an extensible interface for compile-time management of resources. We demonstrate that LEAP provides design portability, while consuming as little as 3% of FPGA area, by mapping several designs on to various FPGA platforms.

关键词： field programmable gate arrays Operating systems Libraries Program processors Hardware Abstracts

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Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security

Balancing WDDL dual-rail logic in a tree-based FPGA to enhan...

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international conference on field programmable logic and applications

作者： Emna Amouri Shivam Bhasin Yves Mathieu Tarik Graba Jean-Luc Danger Habib Mehrez CNRS LTCI (UMR 5141) Departement COMELEC Institut TELECOM/TELECOM ParisTech. Paris France LIP6 Universite Pierre et Marie Curie 4 Paris France

the Tree-based FPGA offers better density and timing determinism than traditional mesh-based FPGA. Moreover, thanks to its multilevel structure, it offers greater easiness to balance dual signals in terms of routing resources number. In this paper, we study the use of the Wave Dynamic Differential logic (WDDL) on a custom tree-based FPGA of 2048 cells. the WDDL technique offers an effective way to withstand Differential Power Attacks (DPA). However, the effectiveness of this countermeasure is guaranteed provided a symmetry is maintained between the routing of both the direct and complementary paths, which is very hard to achieve in FPGA. thus, balancing aware Computer-Aided Design (CAD) tools must be developed. In this work, we propose first adjacent placement and balancing-aware routing techniques for tree-based FPGA to counter the routing unbalance. then side channel analyses are performed on FPGA circuit implementing PRESENT crypto-processor. Experimental results show that the balancing methods enhance the design security against side channel attacks.

关键词： Routing field programmable gate arrays Delays Cryptography Switches

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High-throughput implementation of a million-point sparse Fourier Transform

High-throughput implementation of a million-point sparse Fou...

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international conference on field programmable logic and applications

作者： Abhinav Agarwal Haitham Hassanieh Omid Abari Ezz Hamed Dina Katabi Arvind Computer Science & Artificial Intelligence Laboratory Massachusetts Institute of Technology MA USA Massachusetts Institute of Technology Cambridge MA US

the emergence of data-intensive problems in areas like computational biology, astronomy, medical imaging, etc. has emphasized the need for fast and efficient very large Fourier Transforms. Recent work has shown that we can compute million-point transforms efficiently provided the data is sparse in the frequency domain. Processing input samples at rates approaching 1 GHz would allow real-time processing in several such applications. In this paper, we present a high-throughput FPGA implementation that performs a million-point sparse Fourier Transform on frequency-sparse input data, generating the largest 500 frequency component locations and values every 1.16 milliseconds. this design can process streamed input data at 0.86 Giga samples per second, and does not make any assumptions of the distribution of the frequency components beyond sparsity.

关键词： field programmable gate arrays Computer architecture Vectors Indexes Fourier transforms Noise Algorithm design and analysis

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A soft-core processor for finite field arithmetic with a variable word size accelerator

A soft-core processor for finite field arithmetic with a var...

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international conference on field programmable logic and applications

作者： Aiko Iwasaki Keisuke Dohi Yuichiro Shibata Kiyoshi Oguri Ryuichi Harasawa Graduate School of Engineering Nagasaki University Bunkyo Nagasaki Japan

this paper presents implementation and evaluation of an accelerator architecture for soft-cores to speed up reduction process for the arithmetic on GF(2 m ) used in Elliptic Curve Cryptography (ECC) systems. In this architecture, the word size of the accelerator can be customized when the architecture is configured on an FPGA. Focusing on the fact that the number of the reduction processing operations on GF(2 m ) is affected by the irreducible polynomial and the word size, we propose to employ an unconventional word size for the accelerator depending on a given irreducible polynomial and implement a MIPS-based soft-core processor coupled with a variable-word size accelerator. As a result of evaluation with several polynomials, it was shown that the performance improvement of up to 10.2 times was obtained compared to the 32-bit word size, even taking into account the maximum frequency degradation of 20.4% caused by changing the word size. the advantage of using unconventional word sizes was also shown, suggesting the promise of this approach for low-power ECC systems.

关键词： Polynomials Error correction codes Elliptic curve cryptography field programmable gate arrays Clocks Registers

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FPGA architecture support for heterogeneous, relocatable partial bitstreams

FPGA architecture support for heterogeneous, relocatable par...

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international conference on field programmable logic and applications

作者： Christophe Huriaux Olivier Sentieys Russell Tessier Universite de Rennes 1 Rennes Bretagne FR IRISA Rennes Bretagne FR University of Massachusetts Amherst Amherst MA US

the use of partial dynamic reconfiguration in FPGA-based systems has grown in recent years as the spectrum of applications which use this feature has increased. For these systems, it is desirable to create a series of partial bitstreams which represent tasks which can be located in multiple regions in the FPGA fabric. While the transferal of homogeneous collections of lookup-table based logic blocks from region to region has been shown to be relatively straightforward, it is more difficult to transfer partial bitstreams which contain fixed-function resources, such as block RAMs and DSP blocks. In this paper we consider FPGA architecture enhancements which allow for the migration of partial bitstreams including fixed-function resources from region to region even if these resources are not located in the same position in each region. Our approach does not require significant, time-consuming place-and-route during the migration process. We quantify the cost of inserting additional routing resources into the FPGA architecture to allow for easy migration of heterogeneous, fixed-function resources. Our experiments show that this flexibility can be added for a relatively low overhead and performance penalty.

关键词： field programmable gate arrays Routing Fabrics Arrays Switches Wires

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Transparent insertion of latency-oblivious logic onto FPGAs

Transparent insertion of latency-oblivious logic onto FPGAs

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international conference on field programmable logic and applications

作者： Eddie Hung Tim Todman Wayne Luk Imperial College London London London GB

We present an approach for inserting latency-oblivious functionality into pre-existing FPGA circuits transparently. To ensure transparency - that such modifications do not affect the design's maximum clock frequency - we insert any additional logic post place-and-route, using only the spare resources that were not consumed by the pre-existing circuit. the typical challenge with adding new functionality into existing circuits incrementally is that spare FPGA resources to host this functionality must be located close to the input signals that it requires, in order to minimise the impact of routing delays. In congested designs, however, such co-location is often not possible. We overcome this challenge by using flow techniques to pipeline and route signals from where they originate, potentially in a region of high resource congestion, into a region of low congestion capable of hosting new circuitry, at the expense of latency. We demonstrate and evaluate our approach by augmenting realistic designs with self-monitoring circuitry, which is not sensitive to latency. We report results on circuits operating over 200MHz and show that our insertions have no impact on timing, are 2-4 times faster than compile-time insertion, and incur only a small power overhead.

关键词： Routing Pipeline processing field programmable gate arrays Registers Clocks Delays Table lookup

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Accelerate NDN name lookup using FPGA: Challenges and a scalable approach

Accelerate NDN name lookup using FPGA: Challenges and a scal...

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international conference on field programmable logic and applications

作者： Yanbiao Li Dafang Zhang Xian Yu Wei Liang Jing Long Hong Qiao College of Computer Science and Electronic Engineering Hunan University Changsha China College of Computer Science and Engineering Hunan University of Science and Technology Xiangtan China

Recently, Graphic Processing Units (GPUs) have been shown to be of value in supporting wire-speed name lookup in Named Data Networking (NDN). However, due to the computing model on GPU, the lookup latency is not so encouraging. In this paper, we shift the focus from GPU to field-programmable Gate Arrays (FPGA). We highlight three key challenges in accelerating name lookup using FPGA, and then present a scalable approach to address them. In our approach, a hierarchical and compact data structure is proposed to represent the name trie, which achieves not only effective pipeline mapping but also high memory efficiency. Further, it is finally implemented as a linear pipeline on the FPGA platform, enabling both fast lookup speed and low lookup latency. the experimental results show that our approach gains a reduction of memory cost over 90% compared with the referred GPU-based solution. Besides, the lookup throughput of our approach is almost 2.4 times higher, and the latency is up to 3 orders of magnitude lower.

关键词： Pipelines field programmable gate arrays Random access memory Graphics processing units throughput Silicon Acceleration

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