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检索条件"任意字段=25th International Conference on Field Programmable Logic and Applications"

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FPGA implementation of low-power split-radix FFT processors

FPGA implementation of low-power split-radix FFT processors

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international conference on field programmable logic and applications

作者： Zhuo Qian Nasibeh Nasiri Oren Segal Martin Margala University of Massachusetts Lowell Lowell MA USA

Fast Fourier Transform (FFT) is one of the fundamental operations in digital signal processing area. Split-radix Fast Fourier Transform (SRFFT) approximates the minimum number of multiplications by theory among all the FFT algorithms, therefore SRFFT is a good candidate for the implementation of a low power FFT processor. In this PhD work, we aim to implement a novel low power Split-Radix FFT processor using shared-memory architecture and extend this work to a parallel structure based on FPGA. We started by designing a new radix-2 butterfly unit using clock gating approach to block unnecessary switching activity in the multiplier. Compared to existing SRFFT processors which are based on the “L” shaped butterfly, our implementation simplifies the address generation process for FFT data. Furthermore, because the number of multiplications required by SRFFT algorithm significantly decreases as the FFT size increases, it is reasonable to assume the proposed architecture will save more power when it comes to larger points of FFT.

关键词： Program processors field programmable gate arrays Algorithm design and analysis Signal processing algorithms Network topology Topology Clocks

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High-precision self-characterization for the LUT burn-in information leakage threat

High-precision self-characterization for the LUT burn-in inf...

引用

international conference on field programmable logic and applications

作者： Kenneth M. Zick Sen Li Matthew French University of Southern California Information Sciences Institute (USC ISI) Arlington Virginia USA

Information security in FPGAs is at risk; during system operation, data and usage patterns can potentially get imprinted into a chip's physical characteristics, allowing an attacker to later recover intellectual property or cryptographic secrets. Can “data burn-in” vulnerabilities in FPGAs be characterized at low cost? Specifically, can slight shifts in path delays due to burn-in be measured with enough precision? this paper contributes methods for self-characterization of delay changes using novel isolation of key FPGA transistors, improved clock sweeping, and enhanced estimation from launch-andcapture data. Hardware experiments on 2048 Xilinx Kintex-7 paths demonstrate measurement precision of 30-60 femtoseconds, which is more than 10× finer than previous self-characterization results. Further, results show that unintentional burn-in of FPGA LUT contents does indeed occur and can in some cases be detected within a single week, highlighting the need to deploy countermeasures.

关键词： Delays field programmable gate arrays Clocks Table lookup Transistors Temperature measurement Temperature sensors

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A high performance alternating projections image demosaicing hardware

A high performance alternating projections image demosaicing...

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international conference on field programmable logic and applications

作者： Hasan Azgin Serkan Yaliman Ilker Hamzaoglu Faculty of Engineering and Natural Sciences Sabanci University Tuzla Istanbul Turkey

Since capturing three color channels (red, green, and blue) per pixel increases the cost of digital cameras, most digital cameras capture only one color channel per pixel using a single image sensor. the images pass through a color filter array before being captured by the image sensor. Demosaicing is the process of reconstructing the missing color channels of the pixels in the color filtered image using their available neighboring pixels. Alternating Projections (AP) is one of the highest quality image demosaicing algorithms, and it has very high computational complexity. therefore, in this paper, a high performance AP image demosaicing hardware is proposed. this is the first AP image demosaicing hardware in the literature. the proposed hardware is implemented using Verilog HDL. the Verilog RTL code is verified to work correctly in a Xilinx Virtex 6 FPGA. the FPGA implementation can process 31 full HD (1920×1080) images per second.

关键词： Interpolation Image reconstruction Hardware Manganese Image color analysis System-on-chip field programmable gate arrays

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Multi-FPGA reconfigurable system for accelerating MATLAB simulations

Multi-FPGA reconfigurable system for accelerating MATLAB sim...

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international conference on field programmable logic and applications

作者： Muhammed Al Kadi Max Ferger Volker Stegemann Michael Hübner Ruhr-University Bochum Bochum Germany

the use of reconfigurable FPGA devices to support the execution of computationally intensive software tasks is discussed in this paper. A system architecture consisting of multiple serially-connected FPGAs is developed, where each FPGA holds a pool of reconfigurable regions. An accelerator can be reconfigured into a region, replaced or discarded at runtime. Configurable connection blocks are responsible of directing data between any two accelerators. the whole system is connected via PCIe-interface to a host PC, where a middleware layer hides all hardware management operations, e.g. routing the data sent among the accelerators, and provides the end-user with an API to use the whole system. Recently, the very fast interfaces for reconfiguring parts of the used FPGAs minimize the overhead caused for hardware modifications. In addition, a manual design of hardware accelerators is not more needed with the continuously improving quality of high-level synthesis tools. In this paper, we considered the case where our system is used within MATLAB. We build a small library to compare and improve upon the execution times of some often used functions.

关键词： field programmable gate arrays Hardware MATLAB Switches Middleware Ports (Computers) Acceleration

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Criticality-aware scrubbing mechanism for SRAM-based FPGAs

Criticality-aware scrubbing mechanism for SRAM-based FPGAs

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international conference on field programmable logic and applications

作者： Rui Santos Shyamsundar Venkataraman Anup Das Akash Kumar Department of Electrical & Computer Engineering National University of Singapore

Scrubbing has been considered as an effective mechanism to provide fault-tolerance in Static-RAM (SRAM)-based field programmable Gate Arrays (FPGAs). However, the current scrubbing techniques execute without considering the criticality and timing of the user tasks implemented in the FPGA. they often do not execute the scrubbing process in the right instant, which minimizes the probability of each task being executed without transient faults. Moreover, these current solutions are not adapted to the tasks' fault-tolerance requirements, since they may not properly protect the most critical tasks in the system. However, if they do it, they waste resources with the less critical tasks. In this paper, a new scrubbing mechanism is proposed. this new approach adapts the scrubbing mechanism to the tasks' execution, by a proper scheduling and according to their criticality. A proposed heuristic finds a feasible scrubbing schedule for each hardware task. Firstly, the minimum scrubbing periods are computed according to the criticality of each implemented hardware task. Secondly, a proper scrubbing schedule following the EDL (Earliest Deadline as Late as possible) algorithm is found, maximizing the reliability of the system. the experimental results show up to 79% improvements on the system reliability, achieved without wasting scrubbing resources.

关键词： field programmable gate arrays Hardware Schedules Equations Fault tolerance Fault tolerant systems

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Method for dynamic power monitoring on FPGAs

Method for dynamic power monitoring on FPGAs

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international conference on field programmable logic and applications

作者： Mohamad Najem Pascal Benoit Florent Bruguier Gilles Sassatelli Lionel Torres LIRMM - UMR CNRS 5506 - University of Montpellier 2 Montpellier France Universite de Montpellier Montpellier Languedoc-Roussillon FR

the ever-increasing integration densities make it possible to configure multi-core systems composed of hundreds of blocks on existing FPGAs that may influence overall consumption differently. Observing total consumption is not sufficient to accurately assess internal circuit activity to be able to deploy effective adaptation strategies. In this case monitoring techniques are required. this paper presents a CAD flow for high-level dynamic power estimation on FPGAs. the method is based on the monitoring of toggling activity for relevant signals by introducing event counters. the appropriate signals are selected using the Greedy Stepwise filter. Our approach is based on a generic method that is able to produce a power model for any block-based circuit. We evaluated our contribution on a SoC RTL model implemented on Spartan3, Virtex5, and Spartan6 FPGAs. A power model and monitors are automatically generated to achieve the best tradeoff between accuracy and overhead.

关键词： Solid modeling field programmable gate arrays Estimation Hidden Markov models Monitoring Clocks Integrated circuit modeling

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Heterogeneous dataflow architectures for FPGA-based sparse LU factorization

Heterogeneous dataflow architectures for FPGA-based sparse L...

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international conference on field programmable logic and applications

作者： Siddhartha Nachiket Kapre Nanyang Technological University Singapore Singapore SG

FPGA-based token dataflow architectures with heterogeneous computation and communication subsystems can accelerate hard-to-parallelize, irregular computations in sparse LU factorization. We combine software pre-processing and architecture customization to fully expose and exploit the underlying heterogeneity in the factorization algorithm. We perform a one-time pre-processing of the sparse matrices in software to generate dataflow graphs that capture raw parallelism in the computation through substitution and reassociation transformations. We customize the dataflow architecture by picking the right mixture of addition and multiplication processing elements to match the observed balance in the dataflow graphs. Additionally, we modify the network-on-chip to route certain critical dependencies on a separate, faster communication channel while relegating less-critical traffic to the existing channels. Using our techniques, we show how to achieve speedups of up to 37% over existing state-of-the-art FPGA-based sparse LU factorization systems that can already run 3-4× faster than CPU-based sparse LU solvers using the same hardware constraints.

关键词： Benchmark testing Computer architecture field programmable gate arrays Sparse matrices Hardware Parallel processing Optimization

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Exploring architecture parameters for dual-output LUT based FPGAs

Exploring architecture parameters for dual-output LUT based ...

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international conference on field programmable logic and applications

作者： Zhenghong Jiang Colin Yu Lin Liqun Yang Fei Wang Haigang Yang University of Chinese Academy of Sciences Beijing China System on Programmable Chip Research Department Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781479933624

Dual-output lookup tables (LUTs) are mainstream in the design of commercial FPGA products. A detailed exploration of architectural parameters of FPGAs based on dualoutput LUTs is presented. Different from traditional single-output LUT based architecture, “shared inputs” between the sub-LUTs is a new parameter specific to dual-output architecture. In this paper, we focus on the effect of ratio of shared inputs on the performance and area-efficiency. First, we study the required cluster inputs and derive a relationship between cluster inputs, LUT size and cluster size under different ratios of shared inputs. Secondly, our evaluation results show that a FPGA with 4-LUTs and a shared input ratio of two thirds is preferred for area-efficiency, while a large LUT size of 9 with no shared inputs achieves best performance. Finally, we determine that a LUT size of 4, a cluster size from 3 to 8, and a shared input ratio between 1/3 and 2/3, provide the best area-delay product for dual-output LUT based FPGAs.

关键词： Table lookup field programmable gate arrays

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Scalable parallel architecture for singular value decomposition of large matrices

Scalable parallel architecture for singular value decomposit...

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international conference on field programmable logic and applications

作者： Unai Martinez-Corral Koldo Basterretxea Raul Finker Grupo de Disefio en Electronica Digital (GDED) Dept. Electronics Technology University of the Basque Country (UPV IEHU) Bilbao Basque Spain

Singular Value Decomposition (SVD) is a key linear algebraic operation in many scientific and engineering applications, many of them involving high dimensionality datasets and real-time response. In this paper we describe a scalable parallel processing architecture for accelerating the SVD of large m × n matrices. Based on a linear array of simple processing-units (PUs), the proposed architecture follows a double data-flow paradigm (FIFO memories and a shared-bus) for optimizing the time spent in data transferences. the PUs, which perform elemental column-pair evaluations and rotations, have been designed for an efficient utilization of available FPGA resources and to achieve maximum algorithm speed-ups. the architecture is fully scalable from a two-PU scheme to an arrangement with as many as n/2 PUs. this allows for a trade-off between occupied area and processing acceleration in the final implementation, and permits the SVD processor to be implemented both on low-cost and high-end FPGAs. the system has been prototyped on Spartan-6 and Kintex-7 devices for performance comparison.

关键词： Arrays field programmable gate arrays Jacobian matrices Singular value decomposition Algorithm design and analysis Matrix decomposition

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PR-HMPSoC: A versatile partially reconfigurable heterogeneous Multiprocessor System-on-Chip for dynamic FPGA-based embedded systems

PR-HMPSoC: A versatile partially reconfigurable heterogeneou...

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international conference on field programmable logic and applications

作者： Tuan D. A. Nguyen Akash Kumar National University of Singapore Singapore SG

FPGA-based heterogeneous Multiprocessor Systems-on-Chip (HMPSoCs) are becoming quite popular for high performance embedded systems because of their powerful computational ability and relatively flexible architecture to adapt to unexpected system requirement changes. However, with the insatiable demands of supporting an extensive range of applications beyond the limited resources of FPGA chip and shorter time-to-market, many research works on partially reconfigurable (PR) FPGA architectures have been conducted to fulfill the needs. those have yet to fully provide a versatile framework to exploit the flexibility of PR such as hardware/software task migration and bitstream relocation; more importantly, the on-chip debug features to access all processors currently loaded in the system are compromised because of the lack of native-support from vendor tools. In this paper, a novel PR-HMPSoC architecture for dynamic FPGA-based embedded system is proposed to provide solutions for all of the above issues. the results from the experimental system consisting of one static Microblaze and three PR Microblaze/hardware accelerators connected by a Network-on-Chip show that the architecture is very promising with just 8% reduction in operating frequency.

关键词： Program processors Hardware field programmable gate arrays Clocks Loading Memory management

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