检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

115 篇 会议
2 册 图书
1 篇 期刊文献

馆藏范围

118 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

93 篇 工学
- 90 篇 计算机科学与技术...
- 84 篇 软件工程
- 6 篇 电气工程
- 5 篇 电子科学与技术（可...
- 4 篇 信息与通信工程
- 2 篇 机械工程
- 2 篇 安全科学与工程
- 1 篇 仪器科学与技术
- 1 篇 动力工程及工程热...
- 1 篇 控制科学与工程
- 1 篇 建筑学
- 1 篇 土木工程
- 1 篇 交通运输工程
- 1 篇 核科学与技术
9 篇 理学
- 8 篇 数学
- 2 篇 统计学（可授理学、...
- 1 篇 物理学
2 篇 管理学
- 2 篇 管理科学与工程(可...
- 2 篇 工商管理
1 篇 经济学
- 1 篇 应用经济学

主题

89 篇 field programmab...
33 篇 hardware
18 篇 computer archite...
15 篇 table lookup
13 篇 tools
13 篇 acceleration
11 篇 field programmab...
9 篇 parallel process...
9 篇 routing
9 篇 throughput
9 篇 pipelines
9 篇 kernel
9 篇 software
8 篇 delays
8 篇 bandwidth
8 篇 random access me...
8 篇 pipeline process...
7 篇 neural networks
7 篇 computational mo...
7 篇 clocks

机构

2 篇 department of te...
2 篇 univ waterloo wa...
2 篇 univ manchester ...
2 篇 univ illinois ur...
2 篇 brigham young un...
2 篇 the university o...
2 篇 escuela super po...
2 篇 vrije univ bruss...
2 篇 hong kong univ s...
2 篇 univ toronto dep...
2 篇 tech univ crete ...
2 篇 tsinghua univ in...
2 篇 univ rennes 1 ir...
2 篇 politecn milan m...
2 篇 imperial coll lo...
1 篇 louisiana tech u...
1 篇 mahindra ecole c...
1 篇 imperial college...
1 篇 inria irisa rocq...
1 篇 nanyang technol ...

作者

4 篇 luk wayne
4 篇 koch dirk
3 篇 li shuguo
3 篇 diessel oliver
2 篇 kekely michal
2 篇 dollas apostolos
2 篇 dominguez federi...
2 篇 chrysos grigorio...
2 篇 kapre nachiket
2 篇 betz vaughn
2 篇 ienne paolo
2 篇 maruyama tsutomu
2 篇 pnevmatikatos di...
2 篇 gong lingkan
2 篇 ordaz jose raul ...
2 篇 derrien steven
2 篇 da silva bruno
2 篇 alonso gustavo
2 篇 owaida muhsen
2 篇 korenek jan

语言

118 篇 英文

检索条件"任意字段=27th International Conference on Field Programmable Logic and Applications, FPL 2017"

共 118 条记录，以下是1-10 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

2017 27th international conference on field programmable logic and applications, fpl 2017

2017 27th International Conference on Field Programmable Log...

引用

27th international conference on field programmable logic and applications, fpl 2017

ISBN: (纸本)9789090304281

the proceedings contain 109 papers. the topics discussed include: evaluating FPGA clusters under wide ranges of design parameters;a high-performance system-on-chip architecture for direct tracking for SLAM;Taiga: a new RISC-V soft-processor framework enabling high performance CPU architectural features;a generic high throughput architecture for stream processing;enabling partial reconfiguration and low latency routing using segmented FPGA NOCs;rapid implementation of a partially reconfigurable video system with PYNQ;a partial reconfiguration based microphone array network emulator;a dynamic partial reconfigurable overlay concept for PYNQ;ARMHEX: a hardware extension for DIFT on arm-based SOCs;voltage drop-based fault attacks on FPGAs using valid bitstreams;high throughput AES encryption/decryption with efficient reordering and merging techniques;comparison of hardware and software implementations of selected lightweight block ciphers;one size does not fit all: implementation trade-offs for iterative stencil computations on FPGAs;FPGA-based design of a self-checking TMR voter;accelerator-in-switch: a framework for tightly coupled switching hub and an accelerator with FPGA;stripe: signal selection for runtime power estimation;a programming model and runtime system for approximation-aware heterogeneous computing;Vivado design interface: an export/import capability for Vivado FPGA designs;optimizing streaming stencil time-step designs via FPGA floorplanning;and in-switch approximate processing: delayed tasks management for MapReduce applications.

关键词：

来源：评论

学校读者我要写书评

暂无评论

4th international Workshop on FPGAs for Software Programmers, FSP 2017, co-located with international conference on field programmable logic and applications, fpl 2017

4th International Workshop on FPGAs for Software Programmers...

引用

international Workshop on FPGAs for Software Programmers, FSP 2017, co-located with international conference on field programmable logic and applications, fpl 2017

ISBN: (纸本)9783800744435

the proceedings contain 10 papers. the topics discussed include: a case for better integration of host and target compilation when using OpenCL for FPGAs;PCIeHLS: an OpenCL HLS framework;SOCAO: source-to-source OpenCL compiler for Intel-Altera FPGAs;a highly efficient and comprehensive image processing library for C++-based high-level synthesis;accelerating Linux bash commands on FPGAs using partial reconfiguration;acceleration of solving quadratic assignment problems on programmable SoC using High level synthesis;spatial memory trace prediction;on the HLS design of bit-level operations and custom data types;and using GCC analysis techniques to enable parallel memory accesses in HLS.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Mapping of P4 Match Action Tables to FPGA 27

Mapping of P4 Match Action Tables to FPGA

引用

27th international conference on field programmable logic and applications (fpl)

作者： Kekely, Michal Korenek, Jan Brno Univ Technol Fac Informat Technol Brno Czech Republic

ISBN: (纸本)9789090304281

Current networks are changing very fast. Network administrators need more flexible and powerful tools to be able to support new protocols or services very fast. the P4 language provides new level of abstraction for flexible packet processing. therefore, we have designed new architecture for memory efficient mapping of P4 match/action tables to FPGA. the architecture is based on DCFL algorithm and is able to balance the processing speed and available memory resources.

关键词： throughput field programmable gate arrays Hardware Memory management Algorithm design and analysis Protocols

来源：评论

学校读者我要写书评

暂无评论

Phase Calibrated Ring Oscillator PUF Design and Implementation on FPGAs 27

Phase Calibrated Ring Oscillator PUF Design and Implementati...

引用

27th international conference on field programmable logic and applications (fpl)

作者： Yan, Wei Jin, Chenglu Tehranipoor, Fatemeh Chandy, John A. Univ Connecticut Storrs CT 06269 USA

ISBN: (纸本)9789090304281

A ring oscillator physical unclonable function (RO PUF) is an application-constrained hardware security primitive that can be used for authentication and key generation. PUFs depend on variability during the fabrication process to produce random outputs that are nevertheless stable across multiple measurements. Unfortunately, RO PUFs are known to be unstable especially when implemented on an field programmable Gate Array (FPGA). In this work, we comprehensively evaluate the RO PUF's stability on FPGAs, and we propose a phase calibration process to improve the stability of RO PUFs. the results show that the bit errors in our PUFs are reduced to less than 1%.

关键词： Physical Unclonable Function Ring Oscillator Phase Calibration field programmable Gate Array

来源：评论

学校读者我要写书评

暂无评论

FISH: Linux System Calls for FPGA Accelerators 27

FISH: Linux System Calls for FPGA Accelerators

引用

27th international conference on field programmable logic and applications (fpl)

作者： Nam, Kevin Fort, Blair Brown, Stephen Univ Toronto ECE Dept Toronto ON Canada

ISBN: (纸本)9789090304281

this paper presents the FISH (FPGA-Initiated Software-Handled) framework which allows FPGA accelerators to make system calls to the Linux operating system in CPU-FPGA systems. A special FISH Linux kernel module running on the CPU provides a system call interface for FPGA accelerators, much like the ABI which exists for software programs. We provide a proofof-concept implementation of this framework running on the Intel Cyclone V SoC device, and show that an FPGA accelerator can seamlessly make system calls as if it were the host program. We see the FISH framework being especially useful for high-level synthesis (HLS) by making it possible to synthesize software code that contains system calls.

关键词： Fish Kernel Linux field programmable gate arrays Registers Acceleration

来源：评论

学校读者我要写书评

暂无评论

Application-Specific Soft-Core Vector Processor for Advanced Driver Assistance Systems 27

Application-Specific Soft-Core Vector Processor for Advanced...

引用

27th international conference on field programmable logic and applications (fpl)

作者： Nolting, Stephan Giesemann, Florian Hartig, Julian Schmider, Achim Paya-Vaya, Guillermo Leibniz Univ Hannover Inst Microelect Syst Appelstr 4 D-30167 Hannover Germany

ISBN: (纸本)9789090304281

Implementing convolutional neural networks for scene labelling is a current hot topic in the field of advanced driver assistance systems. the massive computational demands under hard real-time and energy constraints can only be tackled using specialized architectures. Also, cost-effectiveness is an important factor when targeting lower quantities. In this PhD thesis, a vector processor architecture optimized for FPGA devices is proposed. Amongst other hardware mechanisms, a novel complex operand addressing mode and an intelligent DMA are used to increase perfromance. Also, a C-compiler support for creating applications is introduced.

关键词： field programmable gate arrays Random access memory Computer architecture Vector processors Advanced driver assistance systems Biological neural networks Parallel processing

来源：评论

学校读者我要写书评

暂无评论

Optimizing Streaming Stencil Time-step Designs via FPGA Floorplanning 27

Optimizing Streaming Stencil Time-step Designs via FPGA Floo...

引用

27th international conference on field programmable logic and applications (fpl)

作者： Rabozzi, Marco Natale, Giuseppe Festa, Biagio Miele, Antonio Santambrogio, Marco D. Politecn Milan Milan Italy

ISBN: (纸本)9789090304281

Stencil computations represent a highly recurrent class of algorithms in various high performance computing scenarios. the Streaming Stencil Time-step (SST) architecture is a recent implementation of stencil computations on field programmable Gate Array (FPGA). In this paper, we propose an automated framework for SST-based architectures capable of achieving the maximum performance level for a given FPGA device through 1) the maximization of basic modules instantiated in the design and 2) optimization of the design floorplanning. Experimental results show that the proposed approach reduces the design time up to 15x w.r.t. naive design space exploration approaches, and improves the performance of the 13%.

关键词： field programmable Gate Arrays Floorplanning Stencil Computations

来源：评论

学校读者我要写书评

暂无评论

Accelerated analysis of Boolean gene regulatory networks 27

Accelerated analysis of Boolean gene regulatory networks

引用

27th international conference on field programmable logic and applications (fpl)

作者： Purandare, Mitra Polig, Raphael Hagleitner, Christoph IBM Res Zurich Zurich Switzerland

ISBN: (纸本)9789090304281

In Systems Biology, Boolean models are gaining popularity in modeling and analysis of qualitative dynamics of gene regulatory mechanisms. With the development of advanced high-throughput technologies, the availability of experimental data on gene-gene, gene-protein interactions is ever increasing. Consequently, modern Boolean models are increasing in size and complexity. Software simulation of Boolean models does not scale for such state-of-the-art complex Boolean models. We propose field programmable Gate Arrays (FPGAs) for emulation of Boolean models, exploiting the highly parallel nature of FPGAs. Our emulation framework consists of converting a Boolean model to Verilog, connecting it to an execution core, which runs on an FPGA coherently attached to a POWER8 processor. We report an order of magnitude speed up over a multi-threaded software simulation tool running on the same processor.

关键词： Biological system modeling Registers field programmable gate arrays Software Mathematical model Computational modeling Clocks

来源：评论

学校读者我要写书评

暂无评论

Dynamic Bitwidth Assignment for Efficient Dot Products 27

Dynamic Bitwidth Assignment for Efficient Dot Products

引用

27th international conference on field programmable logic and applications (fpl)

作者： Schmidt, Simon Joel Boland, David Monash Univ Dept Elect & Comp Syst Engn Clayton Vic Australia Univ Sydney Sch Elect & Informat Engn Sydney NSW Australia

ISBN: (纸本)9789090304281

the benefits of customising the precision throughout an FPGA design according to a design tolerance are well known. However, customising the precision of a design at run-time has the potential for an even greater performance impact. In this paper, we add the ability to dynamically choose the internal precision of a datapath. this enables a result that is at least as accurate as the worst-case under standard precisions, whilst internally operating at a lower precision. We demonstrate this technique on fused floating-point dot-product circuits. We show that for circuits with inputs that have a wide dynamic range, we can see substantial resource savings. We provide examples with savings of up to 75% of the DSPs and 16% of the ALMs over an optimised fused dot-product design.

关键词： Multiplexing Random access memory Algorithm design and analysis Adders Clocks field programmable gate arrays Hardware

来源：评论

学校读者我要写书评

暂无评论

A Security Library for FPGA Interlays 27

A Security Library for FPGA Interlays

引用

27th international conference on field programmable logic and applications (fpl)

作者： Vaishnav, Anuj Ordaz, Jose Raul Garcia Koch, Dirk Univ Manchester Sch Comp Sci Manchester Lancs England

ISBN: (纸本)9789090304281

Many CPU design houses have added dedicated support for cryptography in recent processor generations, including Intel, IBM, and ARM. While adding accelerators and/or dedicated instructions boosts performance on cryptography, we are investigating a different approach that is not adding extra silicon area: We study to replace the hardened NEON SIMD unit of an ARM Cortex-A9 with an identical sized FPGA fabric, called an interlay. this will be used for implementing cryptographic instructions in soft-logic. We show that this approach can outperform the hardened NEON by up to 7.7 x on AES and provide functionality that is not available in the hardened ARM.

关键词： Neon field programmable gate arrays Cryptography Pipeline processing Fabrics Table lookup throughput

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共12页 << < 1 2 3 4 5 6 7 8 9 10 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：