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检索条件"任意字段=27th International Conference on Field Programmable Logic and Applications, FPL 2017"

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2017 27th international conference on field programmable logic and applications, fpl 2017

2017 27th International Conference on Field Programmable Log...

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27th international conference on field programmable logic and applications, fpl 2017

ISBN: (纸本)9789090304281

the proceedings contain 109 papers. the topics discussed include: evaluating FPGA clusters under wide ranges of design parameters;a high-performance system-on-chip architecture for direct tracking for SLAM;Taiga: a new RISC-V soft-processor framework enabling high performance CPU architectural features;a generic high throughput architecture for stream processing;enabling partial reconfiguration and low latency routing using segmented FPGA NOCs;rapid implementation of a partially reconfigurable video system with PYNQ;a partial reconfiguration based microphone array network emulator;a dynamic partial reconfigurable overlay concept for PYNQ;ARMHEX: a hardware extension for DIFT on arm-based SOCs;voltage drop-based fault attacks on FPGAs using valid bitstreams;high throughput AES encryption/decryption with efficient reordering and merging techniques;comparison of hardware and software implementations of selected lightweight block ciphers;one size does not fit all: implementation trade-offs for iterative stencil computations on FPGAs;FPGA-based design of a self-checking TMR voter;accelerator-in-switch: a framework for tightly coupled switching hub and an accelerator with FPGA;stripe: signal selection for runtime power estimation;a programming model and runtime system for approximation-aware heterogeneous computing;Vivado design interface: an export/import capability for Vivado FPGA designs;optimizing streaming stencil time-step designs via FPGA floorplanning;and in-switch approximate processing: delayed tasks management for MapReduce applications.

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4th international Workshop on FPGAs for Software Programmers, FSP 2017, co-located with international conference on field programmable logic and applications, fpl 2017

4th International Workshop on FPGAs for Software Programmers...

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international Workshop on FPGAs for Software Programmers, FSP 2017, co-located with international conference on field programmable logic and applications, fpl 2017

ISBN: (纸本)9783800744435

the proceedings contain 10 papers. the topics discussed include: a case for better integration of host and target compilation when using OpenCL for FPGAs;PCIeHLS: an OpenCL HLS framework;SOCAO: source-to-source OpenCL compiler for Intel-Altera FPGAs;a highly efficient and comprehensive image processing library for C++-based high-level synthesis;accelerating Linux bash commands on FPGAs using partial reconfiguration;acceleration of solving quadratic assignment problems on programmable SoC using High level synthesis;spatial memory trace prediction;on the HLS design of bit-level operations and custom data types;and using GCC analysis techniques to enable parallel memory accesses in HLS.

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TTA-SIMD Soft Core Processors 30

TTA-SIMD Soft Core Processors

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30th international conference on field-programmable logic and applications (fpl)

作者： Tervo, Kati Malik, Samawat Leppanen, Topi Jaaskelainen, Pekka Tampere Univ Tampere Finland

ISBN: (纸本)9781728199023

Soft processors are an important tool in the field programmable Gate Array (FPGA) designer's toolkit, and their Single Instruction Multiple Data (SIMD) organizations are an efficient means to utilize the parallelism of FPGAs. However, the state-of-the-art SIMD processors are hindered by the additional logic complexity resulting from dynamic features. By minimizing such constructs, it is possible to design soft processors that are efficient but still flexible enough to operate within an application domain. To this end, we propose a family of instruction set programmable multi-issue wide SIMD soft cores. the template is based on a highly static Transport Triggered Architecture (TTA) and a design time customizable shuffle unit to minimize inefficient dynamic features while remaining compiler programmable. the cores are evaluated on the PYNQ-Z1 board against the ARM A9 hard processor system with NEON vector extensions. the proposed cores reach up to 2.4x performance improvement over the ARM, can fit up to 1024 bit wide SIMD units onto the relatively small FPGA, while still operating at above 100 MHz. the scalability of TTA enables state of the art vector widths. the multicore scalability of the template is preliminarily tested with a 14-core design on a XCZU9EG FPGA customized for real-time convolutional neural net inference.

关键词： field-programmable Gate Array (FPGA) Transport-Triggered Architecture (TTA) Single Instruction Multiple Data (SIMD)

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New FPGA design solution using quantum computation concepts 27

New FPGA design solution using quantum computation concepts

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IEEE 27th international Symposium for Design and Technology in Electronic Packaging (SIITME)

作者： Mazare, Alin Gheorghita Ionescu, Laurentiu Mihai Lita, Ioan Serban, Gheorghe Belu, Nadia Univ Pitesti Dept Elect Comp & Elect Engn Pitesti Romania Univ Pitesti Dept Mfg & Ind Management Pitesti Romania

ISBN: (纸本)9781665421102

Quantum computer emulators implemented on FPGA are generally designed to illustrate possible applications in which these concepts can be used - as a method of functional testing of possible applications involving quantum computing. In this paper we try to present another possible use of a quantum computation emulator, proposed by the authors, for the synthesis of circuits in FPGA with superior performance to conventional or parallel design methods. the paper presents a synthesis solution of parallel structures based on concepts from quantum computation emulated on FPGA. As will be seen in the paper, using the solution improves the computation time compared to the conventional method and reduces the number of resources allocated compared to the parallel solution. So, the solution which we propose is somewhere between conventional sequential logic circuit design methods - it has a shorter response time than these and parallel circuit design methods - it provides a smaller number of resources than these. In order to show the advantages of the proposed solution, we presented the implementation of a circuit for determining the parity of a binary function. the solution was implemented using the conventional solution, the parallel solution and the proposed solution using quantum computing concepts. It will show the performance of the proposed solution compared to the other design models.

关键词： Quantum computing Quantum computer emulator field programmable Gates Array (FPGA) Circuits design

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On-the-Fly Parallel Data Shuffling for Graph Processing on OpenCL-based FPGAs 29

On-The-Fly Parallel Data Shuffling for Graph Processing on O...

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29th international conference on field-programmable logic and applications (fpl)

作者： Chen, Xinyu Bajaj, Ronak Chen, Yao He, Jiong He, Bingsheng Wong, Weng-Fai Chen, Deming Natl Univ Singapore Singapore Singapore Adv Digital Sci Ctr Singapore Singapore Alibaba Grp Hangzhou Peoples R China Univ Illinois Urbana IL 61801 USA

ISBN: (纸本)9781728148847

Graph processing has attracted much attention recently due to its popularity in many big data analytic applications. With high performance and energy efficiency, FPGAs can be an attractive architecture for graph processing. A number of techniques such as caching using block RAMs (BRAMs) to reduce random accesses of global memory and multiple processing element (PE) instances for high throughput have been explored. OpenCL-based FPGAs natively support a high-level programming paradigm, providing good programmability to developers. However, challenges remain because the run-time dependency introduced by multiple PEs usually cannot be handled efficiently by OpenCL's high-level control granularity. In this paper, we propose a novel on-the-fly parallel data shuffling technique that can be implemented in OpenCL to solve this problem. We have integrated our shuffling technique to an edge-centric graph processing framework which achieves a throughput of more than 1,000 million traversed edges per second (MTEPS) on PageRank, SpMV, BFS and SSSP applications and is even better than existing RTL-based designs.

关键词： field programmable gate arrays Parallel processing throughput Hardware Layout Engines Computer architecture

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Data stream statistics over sliding windows: How to summarize 150 Million updates per second on a single node 29

Data stream statistics over sliding windows: How to summariz...

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29th international conference on field-programmable logic and applications (fpl)

作者： Chrysos, Grigorios Papapetrou, Odysseas Pnevmatikatos, Dionisios Dollas, Apostolos Garofalakis, Minos Tech Univ Crete Sch Elect & Comp Engn Iraklion Greece Eindhoven Univ Technol Dept Math & Comp Sci Eindhoven Netherlands ATHENA Res & Innovat Ctr Athens Greece

ISBN: (纸本)9781728148847

Traditional data management systems map information using centralized and static data structures. Modern applications need to process in real time datasets much larger than system memory. To achieve this, they use dynamic entities that are updated with streaming input data over a sliding window. For efficient and high performance processing, approximate sketch synopses of input streams have been proposed as effective means for the summarization of streaming data over large sliding windows with probabilistic accuracy guarantees. this work presents a system-level solution to accelerate the Exponential Count-Min (ECM) sketch algorithm on reconfigurable technology. Different reconfigurable architectures for the sketch structure that correspond to different cost and performance tradeoffs are presented. We map the proposed system-level ECM sketch architectures to a high-end modern HPC platform to achieve guaranteed and best-effort update rates up to 150 and 180 million tuples per second respectively. We compare the performance of the implemented system against the best optimized multi-thread software alternative and show that our scalable full-system accelerators outperform software solutions by 5-7.5x for Virtex6 devices and in excess of 10x for current Ultrascale devices.

关键词： Electronic countermeasures Microsoft Windows Complexity theory Histograms field programmable gate arrays IP networks throughput

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Resource Reduction of BFGS Quasi-Newton Implementation on FPGA using Fixed-Point Matrix Updating 28

Resource Reduction of BFGS Quasi-Newton Implementation on FP...

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28th international conference on field programmable logic and applications (fpl)

作者： Liu, Jia Liu, Qiang Tianjin Univ Tianjin Key Lab Imaging & Sensing Microelect Tech Sch Microelect Tianjin Peoples R China

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Quasi-Newton (QN) methods are now widely used for NN training due to their high effectiveness. In practice, the iterative process of the QN methods implemented in software is often very time-consuming. To accelerate the training process, floating-point BFGS-QN implementation has been realized on FPGA. By analyzing the performance of the BFGS-QN implementation, it is found that updating the inverse of approximate Hessian matrix B is the most computation and memory intensive part. therefore, a fixed-point hardware design of B matrix updating is proposed in this paper. the fixed-point representation could lead to overflow and underflow during the computation, which degrade the convergence performance of the training process. To address the issues, matrix property checking and precision scaling schemes are proposed, giving a tradeoff between resource and precision. the experimental results show that compared with the single-precision floating-point BFGS-QN, the mixed precision BFGS-QN with fixed-point B matrix updating design achieves up to 10.9% LUTs, 20.2% FFs and 18.1% BRAMs reduction, while the training speed is not satisfied.

关键词： Training field programmable gate arrays Training data Hardware Convergence Artificial neural networks

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Mapping of P4 Match Action Tables to FPGA 27

Mapping of P4 Match Action Tables to FPGA

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27th international conference on field programmable logic and applications (fpl)

作者： Kekely, Michal Korenek, Jan Brno Univ Technol Fac Informat Technol Brno Czech Republic

ISBN: (纸本)9789090304281

Current networks are changing very fast. Network administrators need more flexible and powerful tools to be able to support new protocols or services very fast. the P4 language provides new level of abstraction for flexible packet processing. therefore, we have designed new architecture for memory efficient mapping of P4 match/action tables to FPGA. the architecture is based on DCFL algorithm and is able to balance the processing speed and available memory resources.

关键词： throughput field programmable gate arrays Hardware Memory management Algorithm design and analysis Protocols

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Phase Calibrated Ring Oscillator PUF Design and Implementation on FPGAs 27

Phase Calibrated Ring Oscillator PUF Design and Implementati...

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27th international conference on field programmable logic and applications (fpl)

作者： Yan, Wei Jin, Chenglu Tehranipoor, Fatemeh Chandy, John A. Univ Connecticut Storrs CT 06269 USA

ISBN: (纸本)9789090304281

A ring oscillator physical unclonable function (RO PUF) is an application-constrained hardware security primitive that can be used for authentication and key generation. PUFs depend on variability during the fabrication process to produce random outputs that are nevertheless stable across multiple measurements. Unfortunately, RO PUFs are known to be unstable especially when implemented on an field programmable Gate Array (FPGA). In this work, we comprehensively evaluate the RO PUF's stability on FPGAs, and we propose a phase calibration process to improve the stability of RO PUFs. the results show that the bit errors in our PUFs are reduced to less than 1%.

关键词： Physical Unclonable Function Ring Oscillator Phase Calibration field programmable Gate Array

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Optimizing Streaming Stencil Time-step Designs via FPGA Floorplanning 27

Optimizing Streaming Stencil Time-step Designs via FPGA Floo...

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27th international conference on field programmable logic and applications (fpl)

作者： Rabozzi, Marco Natale, Giuseppe Festa, Biagio Miele, Antonio Santambrogio, Marco D. Politecn Milan Milan Italy

ISBN: (纸本)9789090304281

Stencil computations represent a highly recurrent class of algorithms in various high performance computing scenarios. the Streaming Stencil Time-step (SST) architecture is a recent implementation of stencil computations on field programmable Gate Array (FPGA). In this paper, we propose an automated framework for SST-based architectures capable of achieving the maximum performance level for a given FPGA device through 1) the maximization of basic modules instantiated in the design and 2) optimization of the design floorplanning. Experimental results show that the proposed approach reduces the design time up to 15x w.r.t. naive design space exploration approaches, and improves the performance of the 13%.

关键词： field programmable Gate Arrays Floorplanning Stencil Computations

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