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检索条件"任意字段=27th International Conference on Field Programmable Logic and Applications, FPL 2017"

共 118 条记录，以下是31-40 订阅

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PolyPC: Polymorphic Parallel Computing Framework on Embedded Reconfigurable System 27

PolyPC: Polymorphic Parallel Computing Framework on Embedded...

引用

27th international conference on field programmable logic and applications (fpl)

作者： Ding, Hongyuan Huang, Miaoqing Univ Arkansas Dept Comp Sci & Comp Engn Fayetteville AR 72701 USA

ISBN: (纸本)9789090304281

With the help of parallelism provided by the fine-grained architecture, hardware accelerators on field programmable Gate Arrays (FPGAs) can significantly improve the performance of many applications. However, designers are typically required to have excellent hardware programming skills and unique optimization techniques to fully explore the potential of FPGA resources. In this work, we propose the PolyPC (Polymorphic Parallel Computing) framework that aims to improve productivity while achieving performance speedup. the PolyPC framework implements a custom hardware platform on which the PolyPC framework extends vendor-provided tools to convert OpenCL-like programs into executables by using high-level synthesis (HLS) tools. the PolyPC framework is evaluated regarding performance, area efficiency, and multitasking. the results show a maximum of 66 folds of speedup over a dual-core ARM processor, and 1,043 folds of speedup over a high-performance MicroBlaze soft processor, with 125 folds of area efficiency. In addition, it delivers a significant improvement in response time to high-priority PolyTasks with the priority-aware scheduling.

关键词： Hardware Kernel Computer architecture field programmable gate arrays Multitasking Parallel processing

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F-C3D: FPGA-based 3-Dimensional Convolutional Neural Network 27

F-C3D: FPGA-based 3-Dimensional Convolutional Neural Network

引用

27th international conference on field programmable logic and applications (fpl)

作者： Fan, Hongxiang Niu, Xinyu Liu, Qiang Luk, Wayne Tianjin Univ Sch Microelect Tianjin Peoples R China Imperial Coll London Dept Comp Sch Engn London England

ISBN: (纸本)9789090304281

In recent years, 3-dimension convolutional neural networks (3D CNNs) have been widely used for video analysis, 3-dimension geometric data and medical image diagnosis. While conventional CNNs are computationally intensive, 3D CNNs push the computational requirements into another level, since each computation depends on multiple image frames. this paper describes a novel hardware architecture for a 3D convolutional neural network, and design strategies to resolve memory usage and bandwidth limitations. the proposed architecture F-C3D is implemented on zc706 at 172MHz, showing 231 times speed up compared with software implementation on 1 GHz ARM CPU, 7.4 times speed up on 3.07 GHz Intel CPU and nearly 10 times lower power consumption than GPU.

关键词： three-dimensional displays Convolution Two dimensional displays Kernel Computer architecture Hardware field programmable gate arrays

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FPGA-based Design of a Self-checking TMR Voter 27

FPGA-based Design of a Self-checking TMR Voter

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27th international conference on field programmable logic and applications (fpl)

作者： Afzaal, Umar Lee, Jeong A. Chosun Univ Dept Comp Engn Gwangju South Korea

ISBN: (纸本)9789090304281

the most common error mitigation scheme used for hardening designs against radiation-induced upsets on FPGAs is Triple Modular Redundancy (TMR). In a TMR system, there are three copies of a module and voting circuits that mask errors by voting for the majority. there are several types of voting circuits which can be classified based on their insertion sites in the design, functionality or the type of data structure to be mitigated. these voters are mostly built from Look-up Tables (LUTs) but these voters just like the design that is hardened by applying TMR are also susceptible to radiation-induced effects. In this paper, we present the design of a self-checking LUT based 1-bit voter intended for those sites where a TMR system reduces to a duplex or a simplex system. Voters on these sites make a single point of failure and the proposed design avoids this situation by attaching multiple voter redundancies to the same output. the operation of the proposed voter has been verified through its hardware implementation and timing simulation.

关键词： Tunneling magnetoresistance Table lookup field programmable gate arrays Switches Redundancy Integrated circuit reliability

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A Programming Model and Runtime System for Approximation-Aware Heterogeneous Computing 27

A Programming Model and Runtime System for Approximation-Awa...

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27th international conference on field programmable logic and applications (fpl)

作者： Parnassos, Ioannis Bellas, Nikolaos Katsaros, Nikolaos Patsiatzis, Nikolaos Gkaras, Athanasios Kanellis, Konstantinos Antonopoulos, Christos D. Spyrou, Michalis Maroudas, Manolis Univ Thessaly Elect & Comp Engn Dept Volos Greece

ISBN: (纸本)9789090304281

Heterogeneous platforms that include diverse architectures such as multicore CPUs, FPGAs and GPUs are becoming very popular due to their superior performance and energy efficiency. Besides heterogeneity, a promising approach for minimizing energy consumption is through approximate computing which relaxes the requirement that all parts of a program are considered equally important to the output quality, thus, all should be executed at full accuracy. Our work extends a traditional OpenMP-like programming model and runtime system to support seamless execution on hybrid architectures with approximation semantics. Starting from a common application code, annotated with our programming model, the programmer can not only target heterogeneous architectures comprising CPU, FPGA and GPU components, but can also regulate the amount of approximation. We evaluate our framework on a number of large-scale applications and demonstrate that the combination of heterogeneous and approximate computing can provide a powerful dynamic interplay between performance and output quality.

关键词： field programmable gate arrays Kernel Runtime Graphics processing units Programming Histograms

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TAIGA: A NEW RISC-V SOFT-PROCESSOR FRAMEWORK ENABLING HIGH PERFORMANCE CPU ARCHITECTURAL FEATURES 27

TAIGA: A NEW RISC-V SOFT-PROCESSOR FRAMEWORK ENABLING HIGH P...

引用

27th international conference on field programmable logic and applications (fpl)

作者： Matthews, Eric Shannon, Lesley Simon Fraser Univ Sch Engn Sci Burnaby BC Canada

ISBN: (纸本)9789090304281

Recently, there has been an increased focus on integration of reconfigurable fabric with modern processors. However, existing soft-processors are optimized to leverage older FPGA fabrics, focus primarily on resource minimization and have fixed-pipeline designs that limit the scope for tightly integrated hardware accelerators. In this work, we present Taiga: a RISC-V, 32-bit, soft-processor architecture supporting the RISC-V Multiply/Divide and Atomic operations extensions (RV32IMA) designed to support Linux-based shared-memory systems. the processor design is highly configurable and features a standardized interface for functional units allowing for ease of integration of new functional units. Despite a more complex pipeline, our design uses approximately 33% fewer slices while clocking 39% faster than a LEON3 based system built on a Xilinx Zynq X7CZ020.

关键词： Program processors field programmable gate arrays Pipelines Rockets Table lookup Fabrics

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Dynamic Power Estimation Based on Switching Activity Propagation 27

Dynamic Power Estimation Based on Switching Activity Propaga...

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27th international conference on field programmable logic and applications (fpl)

作者： Nasser, Y. Prevotet, J. -C. Helard, M. Lorandel, J. INSA Rennes IETR Rennes France Univ Cergy Pontoise ENSEA CNRS ETIS Univ Paris SeineUMR 8051 Cergy Pontoise France

ISBN: (纸本)9789090304281

A new power estimation approach based on the decomposition of a digital system into basic operators is presented. this approach aims to estimate the energy consumption at early design phases of digital blocks implemented on FPGAs. Each operator has its own model which estimates the switching activity and the power consumption. By interconnecting several operators, statistical information is then propagated to provide a global power estimation of a given system. A simple sum of the power dissipation contribution of each operator is enough to compute the total power consumption. this is performed by taking into account the switching activities relative to a given input pattern. Earlier, faster and more flexible power analysis for system designers are the advantages. this approach has been evaluated in a use-case application. the preliminary results indicate a promising speed-up of the design process and an error which is less than 8.0% compare to the classical power estimation tools.

关键词： Estimation Integrated circuit modeling field programmable gate arrays Switches Computational modeling Power demand Neural networks

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Voltage Drop-based Fault Attacks on FPGAs using Valid Bitstreams 27

Voltage Drop-based Fault Attacks on FPGAs using Valid Bitstr...

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27th international conference on field programmable logic and applications (fpl)

作者： Gnad, Dennis R. E. Oboril, Fabian Tahoori, Mehdi B. Karlsruhe Inst Technol Inst Comp Engn Karlsruhe Germany

ISBN: (纸本)9789090304281

Due to the widespread use of FPGAs in many critical application domains, their security is of high concern. In recent systems, such as FPGAs in the Cloud or in Systems-on-Chip (SoCs), users can gain access, even remotely, to the reconfigurable fabric to implement custom accelerators. this access can expose new security vulnerabilities in the entire system through malicious use of the FPGA fabric. In the past, attacks on the power supply level required local access to the hardware. In this paper, we reveal a security vulnerability in FPGAs that allows a valid configuration to generate severe voltage fluctuations, which crashes the FPGA within a few microseconds. Moreover, the extent of this crash is so severe, that manual power-cycling is required to be able to access and use the system again. this vulnerability has been systematically exploited in two different generations of FPGAs, and a SoC containing an FPGA. Because this vulnerability can lead to severe security attacks in systems using FPGA-based accelerators, we also analyze its underlying mechanism, and discuss possibilities for mitigation.

关键词： field programmable gate arrays Security Delays Clocks Latches Fabrics Computer crashes

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Demonstration of a Partial Reconfiguration based Microphone Array Network Emulator 27

Demonstration of a Partial Reconfiguration based Microphone ...

引用

27th international conference on field programmable logic and applications (fpl)

作者： da Silva, Bruno Dominguez, Federico Braeken, An Touhafi, Abdellah Vrije Univ Brussel Dept Ind Sci INDI Brussels Belgium Escuela Super Politecn Litoral ESPOL Guayaquil Ecuador

ISBN: (纸本)9789090304281

the current Micro-Electro-Mechanical System (MEMS) technology allows to deploy relatively low-cost Wireless Sensor Networks (WSN) composed of MEMS microphone arrays for accurate sound-source localization. However, the evaluation and the selection of the most accurate and power-efficient network's topology is not trivial when considering dynamic MEMS microphone arrays. Despite software simulators are usually considered, they are high-computational intensive tasks which require hours to days to be completed. Our demonstrator is an FPGA-based network emulator, which provides a fast network design-space exploration. the user can easily evaluate a network's topology with different nodes' configurations and multiple sound sources in matter of seconds. An intuitive graphical user interface hides from the user the dynamic partial reconfigurations needed by the network emulator to set the node's configurations. As a result, a probability map generated from the fusion of the output data from the nodes and an error on the estimation of the sound-source location are graphically represented.

关键词： field programmable gate arrays Microphone arrays Network topology Micromechanical devices Data integration Wireless sensor networks

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A Demonstration of the GUINNESS: A GUI based Neural NEtwork SyntheSizer for an FPGA 27

A Demonstration of the GUINNESS: A GUI based Neural NEtwork ...

引用

27th international conference on field programmable logic and applications (fpl)

作者： Nakahara, H. Yonekawa, H. Fujii, T. Shimoda, M. Sato, S. Tokyo Inst Technol Tokyo Japan

ISBN: (纸本)9789090304281

the GUINNESS is a tool flow for the deep neural network toward FPGA implementation [3,4,5] based on the GUI (Graphical User Interface) including both the binarized deep neural network training on GPUs and the inference on an FPGA. It generates the trained the Binarized deep neural network [2] on the desktop PC, then, it generates the bitstream by using standard the FPGA CAD tool flow. All the operation is done on the GUI, thus, the designer is not necessary to write any scripts to descript the neural network structure, training behaviour, only specify the values for hyper parameters. After finished the training, it automatically generates C++ codes to synthesis the bitstream using the Xilinx SDSoC system design tool flow. thus, our tool flow is suitable for the software programmers who are not familiar with the FPGA design.

关键词： Neural networks field programmable gate arrays Training Tools Graphical user interfaces Acceleration C++ languages

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One Size Does Not Fit All: Implementation Trade-Offs for Iterative Stencil Computations on FPGAs 27

One Size Does Not Fit All: Implementation Trade-Offs for Ite...

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27th international conference on field programmable logic and applications (fpl)

作者： Deest, Gael Yuki, Tomofumi Rajopadhye, Sanjay Derrien, Steven Univ Rennes 1 IRISA Rennes France INRIA IRISA Rocquencourt France Colorado State Univ Ft Collins CO 80523 USA

ISBN: (纸本)9789090304281

Iterative stencils are kernels in various application domains such as numerical simulations and medical imaging, that merit FPGA acceleration. the best architecture depends on many factors such as the target platform, off-chip memory bandwidth, problem size, and performance requirements. We generate a family of FPGA stencil accelerators targeting emerging System on Chip platforms, (e.g., Xilinx Zynq or Intel SoC). Our designs come with design knobs to explore trade-offs. We also propose performance models to hone in on the most interesting design points, and show how they accurately lead to optimal designs. the optimal choice depends on problem sizes and performance goals.

关键词： field programmable gate arrays System-on-chip Pipeline processing Memory management Acceleration Bandwidth Hardware

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