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检索条件"任意字段=28th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2022"

共 11 条记录，以下是1-10 订阅

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Proceedings - 2022 ieee 28th international symposium on On-line testing and robust system design, iolts 2022

Proceedings - 2022 IEEE 28th International Symposium on On-L...

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28th ieee international symposium on on-line testing and robust system design, iolts 2022

ISBN: (纸本)9781665473552

the proceedings contain 37 papers. the topics discussed include: experimental evaluation of neutron-induced errors on a multicore RISC-V platform;functional and timing implications of transient faults in critical systems;a closer look at evaluating the bit-flip attack against deep neural networks;a new decoding method for double error correcting cross parity codes;all digital low-cost built-in defect testing strategy for operational amplifiers with high coverage;an experimentally tuned compact electrical model for laser fault injection simulation;compressed learning in MCA architectures to tolerate malicious noise;microcontroller performance screening: optimizing the characterization in the presence of anomalous and noisy data;recent trends and perspectives on defect-oriented testing;a novel fault-tolerant logic style with self-checking capability;effective hardware-trojan feature extraction against adversarial attacks at gate-level netlists;understanding the impact of cutting in quantum circuits reliability to transient faults;and quantum noise in the flow of time: a temporal study of the noise in quantum computers.

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A synergistic fault tolerance framework for Mbit 28nm embedded RRAM 30

A synergistic fault tolerance framework for Mbit 28nm embedd...

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30th ieee international symposium on On-line testing and robust system design (iolts)

作者： Panagiota, Papavramidou Ricavy, Sebastien Mounet, Christopher Jahan, Carine Castellani, Niccolo Andrieu, Francois Univ Grenoble Alpes CEA Leti F-38000 Grenoble France

ISBN: (纸本)9798350370560;9798350370553

Resistive Random Access Memory (RRAM) technologies represent a promising frontier in next-generation non-volatile memory devices. they combine an operating speed and endurance superior to Flash memories with cost-effectiveness that challenges DRAMs. this paper delves into the RRAM challenges, examining the fault distribution in advanced RRAM configurations and the interplay between existing error correction codes (ECCs) and design assist techniques like Write Verify Algorithms. Our investigation reveals the limitations of current approaches and underscores the necessity for a holistic system-level fault detection, analysis, and repair solution. through a comprehensive case study, we introduce and evaluate a novel scheme aimed at co-optimizing these elements to enhance RRAM reliability. the contributions of this work not only address a critical gap in the current understanding and application of RRAM but also lay the groundwork for future research and development in memory technologies.

关键词： RRAM Error Correcting Code (ECC) Built-In Self-Test (BIST) Built-In Self-Repair (BISR) Reliability

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All Digital Low-Cost Built-in Defect testing Strategy for Operational Amplifiers with High Coverage 28

All Digital Low-Cost Built-in Defect Testing Strategy for Op...

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28th ieee international symposium on on-line testing and robust system design (iolts)

作者： Sekyere, Michael Saikiran, Marampally Chen, Degang Iowa State Univ Dept Elect & Comp Engn Ames IA 50011 USA

ISBN: (数字)9781665473552

ISBN: (纸本)9781665473552

Backed by standards like ISO26262, achieving near 100% defect coverage is becoming a common reliability requirement in the ever-growing automotive industry. However, achieving high defect coverage in an analog circuit has been proven to be a difficult/expensive task even with sophisticated analog and digital testing circuitry. In this work, we present a simple design for testability (DfT) technique that achieves 98% defect coverage for operational amplifiers including Widlar current reference and biasing circuitry. Our robust testing method utilizes purely digital testing circuits and is extremely time-efficient reducing the test cost. the proposed method can be used both at production test and for on-line health monitoring post-deployment to detect zero-time and latent defects. Also, the digital nature of our method presents a way for defect localization through the recorded bit streams. In this work, we also introduce a simple method to detect defects in the Widlar current reference and the bias current circuit. We validate all our results using extensive transistor-level simulations in UMC65nm technology.

关键词： defect coverage on-line health monitoring operational amplifier DPPM

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LIN-MM: Multiplexed Message Authentication Code for Local Interconnect Network message authentication in road vehicles 28

LIN-MM: Multiplexed Message Authentication Code for Local In...

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28th ieee international symposium on on-line testing and robust system design (iolts)

作者： Oberti, Franco Sanchez, Ernesto Savino, Alessandro Parisi, Filippo Brero, Mirco Di Carlo, Stefano Politecn Torino Control & Comp Engn Dept Turin Italy PUNCH Softronix Srl Turin Italy

ISBN: (数字)9781665473552

ISBN: (纸本)9781665473552

the automotive market is profitable for cyberattacks with the constant shift toward interconnected vehicles. Electronic Control Units (ECUs) installed on cars often operate in a critical and hostile environment. Hence, both carmakers and governments have supported initiatives to mitigate risks and threats belonging to the automotive domain. the Local Interconnect Network (LIN) is one of the most used communication protocols in the automotive field. Today's LIN buses have just a few light security mechanisms to assure integrity through Message Authentication Codes (MAC). However, several limitations with strong constraints make applying those techniques to LIN networks challenging, leaving several vehicles still unprotected. this paper presents LIN Multiplexed MAC (LIN-MM), a new approach for exploiting signal modulation to multiplex MAC data with standard LIN communication. LIN-MM allows for transmitting MAC payloads, maintaining full-back compatibility with all versions of the standard LIN protocol.

关键词： LIN Protocol Automotive Secure Embedded system Secure LIN Network Multiplexed MAC

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Novel BTI robust Ring-Oscillator-Based Physically Unclonable Function 28

Novel BTI Robust Ring-Oscillator-Based Physically Unclonable...

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28th ieee international symposium on on-line testing and robust system design (iolts)

作者： Grossi, Marco Omana, Martin Rossi, Daniele Marzulli, Biagio Metra, Cecilia Univ Bologna Dept Elect Energy & Informat Engn Bologna Italy Univ Pisa Dept Informat Engn Pisa Italy Amaris Technol Srl Brindisi Italy

ISBN: (数字)9781665473552

ISBN: (纸本)9781665473552

Physically Unclonable Functions (PUFs) have become a promising low-cost solution for authentication and key generation in cryptosystems. However, it has been shown in the literature that the reliability of PUFs is undermined by aging mechanisms, such as Bias Temperature Instability (BTI), which may compromise their correct operation. In this paper, we present a novel ring oscillator (RO) based PUF design that is robust against BTI degradation, hereinafter referred to as Low-sensitive-BTI RO - LBTIRO. We compare our proposed LBTIRO to the standard RO-based PUF and to an alternative NBTI-robust RO-PUF recently presented in the literature, for 90 nm and 32 nm CMOS technology nodes. We show that, for considered technology nodes, our proposed LBTIRO features a higher robustness against BTI. Particularly, our LBTIRO enables a reduction of the impact of BTI on the oscillation frequency over circuit lifetime, which reaches 85.3% and 72.1% against the standard RO and the recent alternate solution, respectively, for the 90 nm technology. Moreover, we show that our proposed LBTIRO features a reduction in terms of power consumption if compared to the alternative NBTI-robust RO-PUF.

关键词： PUF ring oscillators BTI aging reliability

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Microcontroller Performance Screening: Optimizing the Characterization in the Presence of Anomalous and Noisy Data 28

Microcontroller Performance Screening: Optimizing the Charac...

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28th ieee international symposium on on-line testing and robust system design (iolts)

作者： Bellarmino, Nicolo Cantoro, Riccardo Huch, Martin Kilian, Tobias Schlichtmann, Ulf Squillero, Giovanni Politecn Torino Turin Italy Infineon Technol AG Munich Germany Tech Univ Munich Munich Germany

ISBN: (数字)9781665473552

ISBN: (纸本)9781665473552

In safety-critical applications, microcontrollers must satisfy strict quality constraints and performances in terms of F-max, that is, the maximum operating frequency. It has been demonstrated that data extracted from on-chip speed monitors can model the F-max of integrated circuits by means of machine learning models, and that those models are suitable for the performance screening process. However, while acquiring data from these monitors is quite an accurate process, the labelling is time-consuming, costly, and may be subject to different measurements errors, impairing the final quality. this paper presents a methodology to cope with anomalous and noisy data in the context of the multi-label regression problem of microcontroller performance screening. We used outlier detection based on Inter Quartile Range (IQR) and Zscore and imputation techniques to detect errors in the labels and to avoid to drop incomplete samples, building higher-quality training set for our models, optimizing the devices characterization phase. Experiments showed that the proposed methodology increases the performance of existing models, making them more robust. these techniques permitted us to use a significantly smaller number of samples (about one third of the devices available for characterization) , thus making the costly data acquisition process more efficient.

关键词： Performance Screening Fmax Speed Monitors Machine Learning Active Learning Device testing

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Sources of Single Event Effects in the NVIDIA Xavier SoC Family under Proton Irradiation 28

Sources of Single Event Effects in the NVIDIA Xavier SoC Fam...

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28th ieee international symposium on on-line testing and robust system design (iolts)

作者： Rodriguez-Ferrandez, Ivan Tali, Maris Kosmidis, Leonidas Rovituso, Marta Steenari, David Univ Politecn Catalunya UPC Barcelona Spain Barcelona Supercomp Ctr BSC Barcelona Spain European Space Agcy ESA Noordwijk Netherlands Holland PTC Delft Netherlands

ISBN: (数字)9781665473552

ISBN: (纸本)9781665473552

In this paper we characterise two embedded GPU devices from the NVIDIA Xavier family system-on-Chip (SoC) using a proton beam. We compare the NVIDIA Xavier NX and Industrial devices, that respectively target commercial and automotive applications. We evaluate the Single-Event Effect (SEE) rate of both modules and their sub-components, both the CPU and GPU, using different power modes, and we try for the first time to identify their exact sources using the on-line testing facilities included in their ARM based system. Our conclusion is that the most sensitive part of the CPU complex of the SoC is the tag array of the various cache structures, while no errors were observed in the GPU, probably because of its fast execution compared to the CPU part of the application during the radiation campaign.

关键词： Space vehicles Protons Radiation effects Satellites Graphics processing units Single event upsets system-on-chip

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On Attacking IJTAG Architecture based on Locking SIB with Security LFSR 28

On Attacking IJTAG Architecture based on Locking SIB with Se...

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28th ieee international symposium on on-line testing and robust system design (iolts)

作者： Kumar, Gaurav Riaz, Anjum Prasad, Yamuna Ahlawat, Satyadev Indian Inst Technol Jammu Dept EE Jammu India Indian Inst Technol Jammu Dept CSE Jammu India

ISBN: (数字)9781665473552

ISBN: (纸本)9781665473552

In recent decennium, hardware security has gained a lot of attention due to different types of attacks being launched, such as IP theft, reverse engineering, counterfeiting, etc. the critical testing infrastructure incorporated into ICs is very popular among attackers to mount side-channel attacks. the ieee standard 1687 (IJTAG) is one such testing infrastructure that is the focus of attackers these days. To secure access to the IJTAG network, various techniques based on Locking SIB (LSIB) have been proposed. One such very effective technique makes use of Security linear Feedback Shift Register (SLFSR) along with LSIB. the SLFSR obfuscates the scan chain information from the attacker and hence makes the brute-force attack against LSIB ineffective. In this work, it is shown that the SLFSR based Locking SIB is vulnerable to side-channel attacks. A power analysis attack along with known-plaintext attack is used to determine the IJTAG network structure. First, the known-plaintext attack is used to retrieve the SLFSR design information. this information is further used along with power analysis attack to determine the exact length of the scan chain which in turn breaks the whole security scheme. Further, a countermeasure is proposed to prevent the aforementioned hybrid attack.

关键词： ieee standard 1687 Power analysis LSIB SLFSR Known-plaintext attack

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Recent Trends and Perspectives on Defect-Oriented testing 28

Recent Trends and Perspectives on Defect-Oriented Testing

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28th ieee international symposium on on-line testing and robust system design (iolts)

作者： Bernardi, P. Cantoro, R. Coyette, A. Dobbeleare, W. Fieback, M. Floridia, A. Gielen, G. Gomez, J. Grosso, M. Guerriero, A. M. Guglielminetti, I. Hamdioui, S. Insinga, G. Mautone, N. Mirabella, N. Sartoni, S. Reorda, M. Sonza Ullmann, R. Vanhooren, R. Xama, N. Wu, L. Onsemi Oudenaarde Belgium Infineon Technol Neubiberg Germany STMicroelectronics Catania Italy Politecn Torino Turin Italy Delft Univ Technol Delft Netherlands Katholieke Univ Leuven Leuven Belgium

ISBN: (数字)9781665473552

ISBN: (纸本)9781665473552

Electronics employed in modern safety-critical systems require severe qualification during the manufacturing process and in the field, to prevent fault effects from manifesting themselves as critical failures during mission operations. Traditional fault models are not sufficient anymore to guarantee the required quality levels for chips utilized in mission-critical applications. the research community and industry have been investigating new test approaches such as device-aware test, cell-aware test, path-delay test, and even test methodologies based on the analysis of manufacturing data to move the scope from OPPM to OPPB. this special session presents four contributions, from academic researchers and industry professionals, to enable better chip quality. We present results on various activities towards this objective, including device-aware test, software-based self-test, and memory test.

关键词： cell-aware test DPPM DPPB device-aware test emerging technologies Flash non-volatile memories data analytics visual inspection

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system-Level Test: State of the Art and Challenges 27

System-Level Test: State of the Art and Challenges

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27th ieee international symposium on On-line testing and robust system design (iolts)

作者： Appello, D. Chen, H. H. Sauer, M. Polian, I Bernardi, P. Reorda, M. Sonza STMicroelect Srl Automot Prod Grp Geneva Switzerland MediaTek Inc Hsinchu Taiwan Advantest Europe Munich Germany Univ Stuttgart Stuttgart Germany Politecn Torino Turin Italy

ISBN: (纸本)9781665433709

system-level test (SLT) is gaining in importance in modern test flows. this paper summarizes recent industrial findings from three companies and discusses some of the still open questions. the first two reports focus on the optimization potentials due to defect coverage overlaps between SLT and other test insertions. Results observed on approximately 20 million manufactured 28nm and 40nm automotive system-on-chip (SoC) designs are reported. Costs and benefits of SLT are discussed and the potentials of a test results analytics platform are identified. the third report explores the role of marginalities among SLT fails. the post-silicon investigation of a CPU block in a 7nm 5G mobile SoC product aims at achieving a better understanding, whose fails are due to random variations versus systematic factors.

关键词： system Level Test reliability quality ATE

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