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检索条件"任意字段=28th International Conference on Logic Programming, ICLP 2012"

共 106 条记录，以下是31-40 订阅

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Mutation-Based Test Generation for PLC Embedded Software Using Model Checking 28th

Mutation-Based Test Generation for PLC Embedded Software Usi...

引用

28th IFIP WG 6.1 international conference on Testing Software and Systems (ICTSS)

作者： Enoiu, Eduard P. Sundmark, Daniel Causevic, Adnan Feldt, Robert Pettersson, Paul Malardalen Univ Software Testing Lab Vasteras Sweden Blekinge Inst Technol Karlskrona Sweden

ISBN: (纸本)9783319474434;9783319474427

Testing is an important activity in engineering of industrial embedded software. In certain application domains (e.g., railway industry) engineering software is certified according to safety standards that require extensive software testing procedures to be applied for the development of reliable systems. Mutation analysis is a technique for creating faulty versions of a software for the purpose of examining the fault detection ability of a test suite. Mutation analysis has been used for evaluating existing test suites, but also for generating test suites that detect injected faults (i.e., mutation testing). To support developers in software testing, we propose a technique for producing test cases using an automated test generation approach that operates using mutation testing for software written in IEC 61131-3 language, a programming standard for safety-critical embedded software, commonly used for Programmable logic Controllers (PLCs). this approach uses the Uppaal model checker and is based on a combined model that contains all the mutants and the original program. We applied this approach in a tool for testing industrial PLC programs and evaluated it in terms of cost and fault detection. For realistic validation we collected industrial experimental evidence on how mutation testing compares with manual testing as well as automated decision-coverage adequate test generation. In the evaluation, we used manually seeded faults provided by four industrial engineers. the results show that even if mutation-based test generation achieves better fault detection than automated decision coverage-based test generation, these mutation-adequate test suites are not better at detecting faults than manual test suites. However, the mutation-based test suites are significantly less costly to create, in terms of testing time, than manually created test suites. Our results suggest that the fault detection scores could be improved by considering some new and improved mutation operato

关键词： Programmable logic controllers

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Geometric programming Formulation for Gate Sizing with Pipelining Constraints 28

Geometric Programming Formulation for Gate Sizing with Pipel...

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28th international conference on VLSI Design (VLSID) / 14th international conference on Embedded Systems

作者： Naidu, Srinath R. Int Inst Informat Technol Bangalore 560100 Karnataka India

ISBN: (纸本)9781479966585

We propose a novel framework to solve the combined retiming/gate sizing problem in the context of optimization of acyclic pipelines. the adjustment of sizes to gates in a combinational circuit is a continuous problem, solvable by a variety of convex optimization tools provided the delay model for each gate is placed in a convex framework. Retiming is a discrete problem since it involves physically moving registers from one location to another. In this paper, we enhance an existing convex optimization framework proposed by Boyd et al [1] to handle registers as 0-1 variables. We solve the relaxed formulation as a geometric program and glean valuable information about the circuit's performance. Another significant contribution of our paper is that we show that our problem is NP-hard.

关键词： combinational circuits computational complexity convex programming flip-flops geometric programming sizing (materials processing) NP-hard problems acyclic pipelining constraint optimization combinational circuit performance combined retiming-gate sizing problem convex optimization tool framework delay model geometric programming formulation glean valuable information physically moving registers Capacitance Delays Linear programming logic gates Pipeline processing Registers Resistance NP-hard convex optimization gate sizing retiming Nondeterministic polynomial-time hard GEOMETRIC programming Pipeline processing Combinational circuits Registers flip-flops convex programming logic gates linear programming Convex function capacitance gates complexity classes Gate dimension Circuit optimization

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Bridging Representations of Laws, of Implementations and of Behaviours 28

Bridging Representations of Laws, of Implementations and of ...

引用

28th Annual international conference on Legal Knowledge and Information Systems (JURIX)

作者： Sileno, Giovanni Boer, Alexander Van Engers, Tom Univ Amsterdam Leibniz Ctr Law Amsterdam Netherlands

To align representations of law, of implementations of law and of concrete behaviours, we designed a common ground representational model for the three domains, based on the notion of position, building upon Petri net... 详细信息

ISBN: (纸本)9781614996095;9781614996088

关键词： Representational alignment Positional programming logic programming Petri Nets Subsumption

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Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic programming 28

Design of a Compact Reversible Carry Look-Ahead Adder Using ...

引用

28th international conference on VLSI Design (VLSID) / 14th international conference on Embedded Systems

作者： Lisa, Nusrat Jahan Babu, Hafiz Md. Hasan Ahasnaullah Univ Sci & Technol Dept Comp Sci & Engn Dhaka Bangladesh Univ Dhaka Dept Comp Sci & Engn Dhaka 1000 Bangladesh

ISBN: (纸本)9781479966585

this paper presents a new method for designing a reversible carry look-ahead adder (RCLA) based on dynamic programming. In this method, we propose a faster technique for generating carry output, which also outperforms the existing ones in terms of number of operations. In addition, we design a compact reversible carry look-ahead circuit based on the proposed technique. In order to optimize our design, we propose a first ever known Reversible Partial Adder (RPA) circuit with the optimum numbers of the quantum cost and garbage outputs which concurrently produce carry propagation signal, carry generation signal and summation of the inputs. Using RPA as a unit element of RCLA construction, we optimize the designs of RCLA and show that the proposed design is better than the existing ones in terms of the number of gates, quantum cost, garbage outputs and delay with the help of Microwind DSCH 3.5, e.g., the proposed 128-bit adder improves 77.55% on number of gates, 10% on garbage outputs, 2.16% on delay and 77.61% on quantum cost over the existing best one.

关键词： Quantum Cost Garbage Output logic Design Reversible Computing Carry Look-Ahead Adder

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A case based approach to concrete deterioration assessment 28

A case based approach to concrete deterioration assessment

引用

28th international conference on Computer Applications in Industry and Engineering, CAINE 2015

作者： Neves, Jose Gomes, Guida Machado, Jose Vicente, Henrique Centro Algoritmi Universidade Do Minho Braga Portugal Departamento de Química Centro de Química de Évora Escola de Ciências e Tecnologia Universidade de Évora Évora Portugal

ISBN: (纸本)9781510812284

the deterioration of concrete infrastructures is of concern since maintenance and repair require large amounts of resources. It is a multifaceted and complex phenomenon, with multiple causes, namely age, use, maintenance, type of environmental exposure and aggression by biological, chemical, mechanical and physical agents. However, it may be prevented if proactive strategies were embraced (e.g., taking into account similar past experiences). Indeed, this work will start with the development of a decision support system to prevent these events from happening, centered on a formal framework based on logic programming for knowledge representation, complemented with a Case-Based Reasoning (CBR) approach to problem solving, which caters for the handling of incomplete, unknown, or even contradictory information. the CBR cycle was adapted in order to cater for the developments referred to above, and clustering methods were enforced to distinguish and aggregate collections of historical records in order to reduce the search space and enhance the retrieve phase.

关键词： logic programming

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2SAT based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids 28

2SAT based Infeasibility Resolution during Design Rule Corre...

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28th international conference on VLSI Design (VLSID) / 14th international conference on Embedded Systems

作者： Salodkar, Nitin Rajagopalan, Subramanian Bhattacharya, Sambuddha Batterywala, Shabbir Samsung Res Inst Bangalore Karnataka India Synopsys India Pvt Ltd Bangalore Karnataka India

ISBN: (纸本)9781479966585

Traditionally, automatic design rule correction (DRC) problem is modeled as a linear program with technology rules and design intents modeled as difference constraints under a minimum perturbation objective. However, these linear programs are often infeasible due to conflicts arising from rules and intents, lack of space or due to incomplete modeling. It is then required to identify problematic constraints and either dilute or drop them to make the linear program feasible. In presence of uniform grid and only difference type constraints, a weighted constraint graph is constructed and infeasibilities are detected as positive cycles. However, this approach breaks down in presence of multiple layer specific grids or discrete track patterns. In this paper, we suggest a novel method for Infeasible Constraint Set Identification (ICSI) for such layouts. Our method transforms the constraint set into a Boolean implications set. Since each implication has only two variables, solving the ICSI problem amounts to determining 2-Satisfiability of the implications set. We then suggest various strategies to resolve infeasibilities.

关键词： Boolean functions computability integrated circuit layout logic design 2SAT based infeasibility resolution Boolean implications set ICSI design rule correction discrete track patterns infeasible constraint set identification multiple layer specific grids Algorithm design and analysis Geometry Layout Shape Transforms Vectors Very large scale integration DRC VLSI grid Very large scale integration layouts Algorithm design and analysis grids Intracytoplasmic Sperm Injections integrated circuit layout logic design computability Transform Boolean functions linear programming geometry distributed revision control system

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Conditional Permissions in Contracts 28

Conditional Permissions in Contracts

引用

28th Annual international conference on Legal Knowledge and Information Systems (JURIX)

作者： Pace, Gordon J. Schapachnik, Fernando Schneider, Gerardo Univ Malta Msida Malta Univ Buenos Aires Buenos Aires DF Argentina Univ Gothenburg Gothenburg Sweden

ISBN: (纸本)9781614996095;9781614996088

Defining and characterising conditional permissions has never been easy. Part of the problem, we believe, comes from the fact that there is not one but a whole family of possible deontic operators, all of them distinct and reasonable, that can be labelled as conditional permissions. In this article, rather than disputing the correct interpretation, we revisit a number of different interpretations the term has received in the literature, and propose appropriate formalisations for these interpretations within the context of contract automata.

关键词： Deontic logic Automata Normative Systems Interactive Two-Party Systems Contract Representation Conditional Permission

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Reasoning about the state change of authorization policie 28th

Reasoning about the state change of authorization policie

引用

28th international conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems, IEA/AIE 2015

作者： Bai, Yun Caprin, Edward Zhang, Yan Artificial Intelligence Research Group School of Computing Engineering and Mathematics University of Western Sydney South Penrith Australia

ISBN: (纸本)9783319190655

Reasoning about authorization policies has been a prominent issue in information security research. In a complex information sharing and exchange environment, a user’s request may initiate a sequence of executions of authorization commands in order to decide whether such request should be granted or denied. Becker and Nanz’s logic of State- Modifying Policies (SMP) is a formal system addressing such problem in access control. In this paper, we provide a declarative semantics for SMP through a translation from SMP to Answer Set programming (ASP). We show that our translation is sound and complete for bounded SMP reasoning. With this translation, we are able not only to directly compute users’ authorization query answers, but also to specifically extract information of how users’ authorization states change in relation to the underlying query answering. In this way, we eventually avoid SMP’s tedious proof system and significantly simply the SMP reasoning process. Furthermore, we argue that the proposed ASP translation of SMP also provides a flexibility to enhance SMP’s capacity for accommodating more complex authorization reasoning problems that the current SMP lacks. © Springer international Publishing Switzerland 2015.

关键词： logic programming

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Geometric programming Formulation for Gate Sizing with Pipelining Constraints

Geometric Programming Formulation for Gate Sizing with Pipel...

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international conference on VLSI Design

作者： Srinath R. Naidu International Institute of Information Technology Bangalore

关键词： logic gates Registers Delays Capacitance Linear programming Pipeline processing Resistance

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Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic programming

Design of a Compact Reversible Carry Look-Ahead Adder Using ...

引用

international conference on VLSI Design

作者： Nusrat Jahan Lisa Hafiz Md. Hasan Babu Department of Computer Science and Engineering Ahasnaullah University of Science and Technology Dhaka Bangladesh Dhaka University Dhaka Dhaka District BD

this paper presents a new method for designing a reversible carry look-ahead adder (RCLA) based on dynamic programming. In this method, we propose a faster technique for generating carry output, which also outperforms the existing ones in terms of number of operations. In addition, we design a compact reversible carry look-ahead circuit based on the proposed technique. In order to optimize our design, we propose a first ever known Reversible Partial Adder (RPA) circuit with the optimum numbers of the quantum cost and garbage outputs which concurrently produce carry propagation signal, carry generation signal and summation of the inputs. Using RPA as a unit element of RCLA construction, we optimize the designs of RCLA and show that the proposed design is better than the existing ones in terms of the number of gates, quantum cost, garbage outputs and delay with the help of Micro wind DSCH 3.5, e.g., the proposed 128-bit adder improves 77.55% on number of gates, 10% on garbage outputs, 2.16% on delay and 77.61% on quantum cost over the existing best one.

关键词： Adders logic gates Delays Complexity theory Hardware Dynamic programming Algorithm design and analysis

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